With Plural Paths In Network Patents (Class 327/293)
  • Patent number: 10444786
    Abstract: A sectioned mesh which includes multiple sections to distribute a clock signal to logic gates. Each section includes interconnected wires operable to deliver the clock signal to the logic gates. The interconnected wires in a same section are shorted together and the interconnected wires in different sections are not shorted. The sectioned mesh also includes clock input structure connecting to one or more contact points in an input section of the sectioned mesh. The sectioned mesh also includes multiple groups of repeater drivers to repower the clock signal. Different groups are in different sections, and each group in a respective section receives the clock signal from a neighboring section.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: October 15, 2019
    Assignee: MEDIATEK SINGAPORE PTE. LTD.
    Inventor: Shih-Kuang Ou
  • Patent number: 10396790
    Abstract: An integrated circuit includes a digital logic circuit, a multiplexer (MUX) having a first and a second data input, a control input, and an output coupled to an input of the digital logic circuit. The second data input is coupled to receive a high frequency clock signal. The integrated circuit includes a very low frequency (VLF) clock is configured to provide a VLF clock signal when enabled, and a counter coupled to receive the VLF clock signal and configured to toggle an output of the counter upon counting a predetermined number of cycles of the VLF clock signal. The output of the counter is coupled to the first data input of the MUX. The MUX is configured to provide the first data input as the output of the MUX during a low power mode, and otherwise to provide the second data input as the output of the MUX.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: August 27, 2019
    Assignee: NXP USA, Inc.
    Inventors: Luis Francisco P. Junqueira De Andrade, Ivan Carlos Ribeiro Do Nascimento, Armando Gomes Da Silva, Jr., Marcos Da Costa Barros
  • Patent number: 10050610
    Abstract: Clock distribution schemes with wide operating voltage ranges are disclosed. In one aspect, an operating voltage level or condition within a computing device is sensed. In a first voltage condition, delay elements are used within a clock tree to minimize clock skew. In a second voltage condition, one or more delay and/or clocked elements are bypassed to minimize clock skew at the second voltage condition. In addition to controlling clock skew, power may be conserved by depowering the bypassed elements. Controlling clock skew in this fashion improves operation of a computing device that includes the clock tree and may improve battery life.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: August 14, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Giby Samson, Yu Pu, Kendrick Hoy Leong Yuen
  • Patent number: 10009027
    Abstract: Three state latch. In accordance with a first embodiment, an electronic circuit includes n pairs of cascaded logical gates. Each of the n pairs of cascaded logical gates includes a first logical gate including n?1 first gate inputs and one first gate output, and a second logical gate including two second gate inputs and one second gate output. One of the second gate inputs is coupled to the first gate output. The second gate output is cross coupled to one of the first gate inputs of all other the pairs of cascaded logical gates, and n is greater than 2.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: June 26, 2018
    Assignee: NVIDIA Corporation
    Inventors: Andreas J. Gotterba, Jesse S. Wang
  • Patent number: 9906024
    Abstract: Devices (20) for coupling sources (11, 12) to loads (13) comprise first converters (21) for converting first input signals from first sources (11) into first output signals. The first converters (21) comprise control inputs for receiving control signals. Control values of the control signals define first parameters of the first output signals. Circuits (23) in the devices (20) receive the first output signals and receive second output signals originating from second sources (12) or from second converters (22) coupled to the second sources (12) and provide power signals to the loads (13). The second sources (12) comprise solar panels. Controllers (24) adapt the control values of the control signals in response to detections of changes in second parameters of the first input or output signals. The controllers (24) may operate independently from the second output signals and from second input signals.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: February 27, 2018
    Assignee: PHILIPS LIGHTING HOLDING B.V.
    Inventors: Priya Ranjan Mishra, Rakeshbabu Panguloori, Vandana Prabhu
  • Patent number: 9231603
    Abstract: There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. The clock distribution circuit includes, on each of the two or more strata, phase detectors, a logic circuit, and a phase de-skewing element. Each phase detector has a respective output for providing phase information relating to a phase difference between two of the global clocks signals on respective different ones of the two or more strata. The logic circuit is connected to the respective outputs of the phase detectors for determining a phase adjustment plan for a given one of the two or more strata upon which the logic circuit is located responsive to the phase information. The phase de-skewing element is for adjusting a clock skew of a same stratum located one of the two of the global clock signals responsive to the phase adjustment plan.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: January 5, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yong Liu, Liang-Teck Pang, Phillip J. Restle
  • Patent number: 9148145
    Abstract: A clock gating circuit for generating a clock enable signal with respect to a clock input signal and a logic enable signal includes: a first plurality of transistors coupled in series between a power supply and ground, for receiving at least the logic enable signal and generating a first output; a second plurality of transistor coupled in series between the power supply and ground, for receiving at least the first output and generating a second output; a third plurality of transistors coupled in series between the power supply and ground, for receiving at least the second output and an inverted second output; and an AND gate circuit, for receiving the second output and generating the clock enable signal.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: September 29, 2015
    Assignee: MediaTek Singapore Pte. Ltd.
    Inventor: Sumanth Katte Gururajarao
  • Patent number: 9148192
    Abstract: An apparatus relating generally to a transmitter-side of a transceiver or a transmitter used to provide a clock signal is disclosed. In this apparatus, a first signal source is to provide a first periodic signal. A second signal source is to provide a second periodic signal. A first multiplexer is coupled to receive the first periodic signal and the second periodic signal to provide a selected one thereof as a first selected output. A phase interpolator is coupled to the first multiplexer to receive the first selected output. The phase interpolator includes a second multiplexer. The second multiplexer is coupled to receive the first selected output and a phase-interpolated version of the first selected output to output a selected one thereof as a second selected output. A divider is coupled to the second multiplexer to receive the second selected output to provide the clock signal.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: September 29, 2015
    Assignee: XILINX, INC.
    Inventors: Alan C. Wong, Christopher J. Borrelli, Loren Jones, Seu Wah Low, Parag Upadhyaya, Robert M. Ondris, Sarosh I. Azad
  • Patent number: 9041451
    Abstract: A resonant clock distribution network architecture is proposed that enables a resonant clock network to track the impact of parameter variations on the insertion delay of a conventional clock distribution network, thus limiting clock skew between the two networks and yielding increased performance. Such a network is generally applicable to semiconductor devices with various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: May 26, 2015
    Assignee: Cyclos Semiconductor, Inc.
    Inventors: Marios C. Papaefthymiou, Alexander Ishii
  • Patent number: 9024672
    Abstract: Digital signals with higher resolution are generated from dual-phase encode signals indicating phase changes of a position or an angle of a target. A signal processing apparatus for processing dual-phase encode signals indicating changes in position of a target, comprises: a first noise reduction unit configured to remove high frequency noise from each of the dual-phase encode signals before interpolation processing; an interpolating unit configured to apply interpolation processing to the dual-phase encode signals output from the first noise reduction unit to generate dual-phase encode signals with higher resolution; and a second noise reduction unit configured to remove noise from the dual-phase encode signals output from the interpolating unit.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: May 5, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventor: Koji Kawamura
  • Patent number: 9018999
    Abstract: A hardware/PLC logic combination which enables measurement of a plurality of analog voltage points (e.g., multiples of 8 points) on a single high speed PLC input without separate synchronization inputs or outputs. This is accomplished through the use of a multiplexer circuit [clock, binary counter, analog multiplexer, voltage to frequency converter], and a high speed counter function at the PLC. Synchronization between the PLC and circuit is through the detection of a fixed voltage on channel “one” of the circuit, which is set well above the typical range (e.g., 0-10V) of the remaining analog inputs.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: April 28, 2015
    Assignee: M&R Printing Equipment, Inc.
    Inventor: Keith R. Falk
  • Patent number: 9000840
    Abstract: An integrated with a block including first and second oppositely doped semiconductor wells. There are standard cells placed next to one another, each standard cell including first transistors and a clock tree cell encircled by standard cells. The clock tree cell has a third semiconductor well with the same doping type as the doping of the first well and second transistors. The clock tree cell also has a semiconductor strip extending continuously around the third well and having the opposite doping type to the doping of the third well to electrically isolate the third well from the first well.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: April 7, 2015
    Assignees: Commissariat à l'énergie atomique et aux énergies alternatives, STMicroeletronics SA, STMicroeletronics (Crolles 2) SAS
    Inventors: Yvain Thonnart, Bastien Giraud, Fady Abouzeid, Sylvain Clerc, Jean-Philippe Noel
  • Patent number: 8994433
    Abstract: A fully on-chip clock generator on an integrated circuit (“IC”) includes a frequency detector for receiving a reference current and providing a first voltage; an error integrator for receiving the first voltage from the frequency detector, comparing it with a reference voltage, and providing a control voltage; a voltage controlled oscillator (“VCO”) for receiving the control voltage from the error integrator, and providing an output clock; and a logic controller on the IC, coupled between the VCO and the frequency detector, and generating logic control signals for controlling the frequency detector. The fully on-chip clock generator requires no external crystal, but its power consumption is significantly lower than a relaxation oscillator that generates the same clock frequency.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: March 31, 2015
    Assignee: Analog Devices, Inc.
    Inventor: Yijing Lin
  • Patent number: 8963587
    Abstract: Embodiments of an apparatus are disclosed that may allow for changing the frequency of a clock coupled to a functional block within an integrated circuit. The apparatus may include a plurality of clock dividers and a multiplex circuit. Each of the plurality of clock dividers may divide the frequency of a base clock signal be a respective one of a plurality of divisors. The multiplex circuit may be configured to receive a plurality of selection signals, select an output from one of the plurality of clock dividers dependent upon the received selection signals, and coupled the selected output of the plurality of clock dividers to the functional block.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: February 24, 2015
    Assignee: Apple Inc.
    Inventors: Erik P. Machnicki, Raman S. Thiara, Shane J. Keil, Timothy J. Millet
  • Patent number: 8963605
    Abstract: Disclosed is a multi-phase clock signal generation circuit including two circuit blocks, each of which includes a cross-coupled structure and two delay units, and the delay units are adjustable. One circuit block (MD1) includes two NMOS transistors, two PMOS transistors, and two delay units, and the other circuit block (MD2) may include two NMOS transistors, two PMOS transistors, and two delay units. The circuit can generate clock signals with respective phases whose relationship is relatively independent of integration process, operating voltage and temperature, thereby allowing guaranteed efficiency for a multi-phase charge pump.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: February 24, 2015
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Weiwei Chen, Lan Chen, Shuang Long
  • Publication number: 20150048873
    Abstract: A clock distribution network having a separate power supply for top levels thereof is disclosed. In one embodiment, an integrated circuit includes a clock distribution network configured to distribute a clock signal to each of a number of clock consumers. The clock distribution network is arranged in a hierarchy of levels, with each of the levels including at least one buffer, and with the upper levels being closer to a source of the clock signal and the lower levels being closer to the clock consumers. The buffers of the upper levels are coupled to receive power from a first power source, via a first power grid. The buffers of the lower levels are coupled to receive power from a second power source, separate from the first, via a second power grid.
    Type: Application
    Filed: August 16, 2013
    Publication date: February 19, 2015
    Applicant: Apple Inc.
    Inventor: Rohit Kumar
  • Patent number: 8947149
    Abstract: Embodiments of a clock distribution device and a method of clock distribution are described. In one embodiment, a clock distribution device includes a stacked clock driver circuit configured to perform clock signal charge recycling on input clock signals that swing between different voltage ranges and a load circuit. The stacked clock driver circuit includes stacked driver circuits configured to generate output clock signals that swing between the different voltage ranges. The load circuit includes load networks of different semiconductor types. Each of the load networks are configured to be driven by one of the output clock signals. Other embodiments are also described.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: February 3, 2015
    Assignee: NXP B.V.
    Inventors: Ajay Kapoor, Ralf Malzahn, Rinze Ida Mechtildis Peter Meijer, Peter Thueringer
  • Patent number: 8928386
    Abstract: A circuit for asynchronously transmitting data in an integrated circuit is described. The circuit comprises a transmitter circuit generating data to be transmitted at an output; a first register having an input, an output and a clock input, wherein the input of the first register is coupled to the output of the transmitter and the clock input of the first register is coupled to receive a clock signal; at least one asynchronous buffer having an input and an output, wherein the input is coupled to the output of the first register; a receiver circuit coupled to the output of the at least one buffer; and a second register having an input, and output and a clock input, wherein the input of the at least one asynchronous buffer is coupled to the output of the transmitter and the clock input of the second register is coupled to receive the clock signal. A method of implementing of asynchronously transmitting data in an integrated circuit device is also disclosed.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: January 6, 2015
    Assignee: Xilinx, Inc.
    Inventors: Ilya Ganusov, Brian C. Gaide
  • Patent number: 8922264
    Abstract: Clock alignment circuitry may include phase comparator circuitry with a first input terminal that receives as first clock signal from a first clock tree and a second input terminal that receives a second clock signal from a second clock tree. The phase comparator circuitry may compare the first and second clock signals and generate different control signals based on the first and second clock signals. The integrated circuit may further include phase interpolator circuitry that generates an output clock signal based on at least one of the control signals received from the phase comparator circuitry. Edges of the generated output clock signal may align with edges of either the first clock signal or the second clock signal.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: December 30, 2014
    Assignee: Altera Corporation
    Inventors: Yan Chong, Warren Nordyke, Sean Shau-Tu Lu, Weiqi Ding
  • Patent number: 8890596
    Abstract: A clock signal generating apparatus includes a first frequency generating circuit, a second frequency generating circuit, and an output circuit. The first frequency generating circuit is arranged to generate a first clock signal having a first oscillation frequency. The second frequency generating circuit is arranged to generate a second clock signal having a second oscillation frequency. The output circuit is arranged to receive the first and second clock signals. The output circuit is able to output one of the first and second clock signals as an output clock signal according to an oscillation frequency control setting provided by an external bounding pad included within the clock signal generating apparatus.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: November 18, 2014
    Assignee: MediaTek Singapore Pte. Ltd.
    Inventor: Xiao-Fei Chen
  • Patent number: 8872565
    Abstract: Digital signals with higher resolution are generated from dual-phase encode signals indicating phase changes of a position or an angle of a target. A signal processing apparatus for processing dual-phase encode signals indicating changes in position of a target, comprises: a first noise reduction unit configured to remove high frequency noise from each of the dual-phase encode signals before interpolation processing; an interpolating unit configured to apply interpolation processing to the dual-phase encode signals output from the first noise reduction unit to generate dual-phase encode signals with higher resolution; and a second noise reduction unit configured to remove noise from the dual-phase encode signals output from the interpolating unit.
    Type: Grant
    Filed: May 8, 2013
    Date of Patent: October 28, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Koji Kawamura
  • Patent number: 8866525
    Abstract: A plurality of PWM generators have user configurable time delay circuits for each PWM control signal generated therefrom. The time delay circuits are adjusted so that each of the PWM control signals arrive at their associated power transistors at the same time. This may be accomplished by determining a maximum delay time of the PWM control signal that has to traverse the longest propagation time and then setting the delay for that PWM control signal to substantially zero delay. Thereafter, all other delay time settings for the other PWM control signals may be determined by subtracting the propagation time for each of the other PWM control signals from the longest propagation time. Thereby insuring that all of the PWM control signals arrive at their respective power transistor control nodes with substantially the same time relationships as when they left their respective PWM generators.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: October 21, 2014
    Assignee: Microchip Technology Incorporated
    Inventors: Bryan Kris, John Day, Alex Dumais, Stephen Bowling
  • Patent number: 8854100
    Abstract: A clock driver for a resonant clock network includes a delay circuit that receives and supplies a delayed clock signal. A first transistor is coupled to receive a first pulse control signal and supply an output clock node of the clock driver. An asserted edge of the first control signal is responsive to the falling edge of the delayed clock signal. A second transistor is coupled to receive a second control signal and to supply the output clock node of the clock driver. An asserted edge of the second control signal is responsive to a rising edge of the delayed clock signal.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: October 7, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Visvesh S. Sathe, Samuel D. Naffziger, Srikanth Arekapudi
  • Publication number: 20140266376
    Abstract: A multi-stage clock distribution circuit for an integrated circuit is provided. The clock distribution circuit may route a common clock signal to a plurality of clock receiver circuits. Each stage in the distribution circuit may include a plurality of buffers. Outputs of at least some, perhaps all, of the buffers may be connected to each other by an interconnect. The interconnect may align clock signals that are output by the interconnected buffers and thereby encourage synchronization of those clock signals. Other stages of the clock distribution signal may be connected as well.
    Type: Application
    Filed: August 14, 2013
    Publication date: September 18, 2014
    Applicant: ANALOG DEVICES, INC.
    Inventors: Shawn S. KUO, Steven C. ROSE
  • Publication number: 20140253203
    Abstract: An integrated circuit having a programmable clock spreader configured to generate a plurality of controllably skewed clock signals, each applied to a corresponding region within the integrated circuit with circuitry configured to be triggered off the applied clock signal. The programmable clock spreader is designed to enable customization of the current-demand characteristics exhibited by the integrated circuit, e.g., based on the circuit's spectral impedance profile, to cause transient voltage droops in the power-supply network of the integrated circuit to be sufficiently small to ensure proper and reliable operation of the integrated circuit.
    Type: Application
    Filed: May 24, 2013
    Publication date: September 11, 2014
    Applicant: LSI CORPORATION
    Inventors: James G. Monthie, Vineet Sreekumar, Ranjit Yashwante
  • Patent number: 8823437
    Abstract: Embodiments of the present invention provide a clock signal generator, and the clock signal generator is applied to a physical layer subsystem supporting data transmission at multiple baud rates. The clock signal generator includes: a source clock signal generator, and two or more processors connected to an output end of the source clock signal generator; where the source clock signal generator outputs multiple source clock signals with the same frequency according to a reference signal of a reference clock in the subsystem; the processors perform frequency dividing processing on the multiple source clock signals through a digital logic circuit according to an oversampling technology, to obtain a synchronous clock signal corresponding to a baud rate of data transmission in the subsystem, so as to implement timing and transceiving functions when data is transmitted at the baud rate.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: September 2, 2014
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Wei Cao, Jindi Zhang, Yingyan Shan
  • Patent number: 8803583
    Abstract: A polyphase clock generator for use in clock data recovery (CDR) includes a phase selector and a four-to-eight phase converter further including a plurality of delay paths, switches, and phase interpolators. The switches switch over the delay paths so as to select a group of delay paths suited to a clock frequency which is determined in advance. A plurality of reference clock signals with a predetermined phase difference (e.g. 90°) therebetween is selectively delayed while passing through the selected group of delay paths. The phase interpolators interpolate the delayed reference clock signals, passing through the selected group of delay paths, into the reference clock signals, thus generating a plurality of clock signals. The phase selector selectively combines the clock signals with a mixing ratio according to clock data recovery, thus generating a plurality of recovery clock signals with a precise phase difference (e.g.) 45°) therebetween.
    Type: Grant
    Filed: August 23, 2012
    Date of Patent: August 12, 2014
    Assignee: NEC Corporation
    Inventor: Takaaki Nedachi
  • Patent number: 8797082
    Abstract: A system and method for efficiently performing timing characterization of high-speed clocks signals with low-speed input/output pins. An integrated circuit includes a clock generator that generates a high-speed clock signal. A clock characterizer circuit receives the high-speed clock signal. The clock characterizer generates a corresponding low-speed clock signal. The generated low-speed clock signal is output through a low-speed general-purpose input/output (GPIO) pin for measurement. The generated low-speed clock signal is sent to a sequential element for staging. The staging of the generated low-speed clock signal is done with sequential elements that use a reverse polarity of a clock signal than the polarity used by a previous stage. The high-speed clock signal is used for the staging. The output of each stage is sent to a low-speed GPIO pin for measurement.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: August 5, 2014
    Assignee: Apple Inc.
    Inventors: Ravi K. Ramaswami, Geertjan Joordens
  • Patent number: 8750346
    Abstract: A method for integrating signals transmitted from a transmitter to at least one ultra wide band receiver, includes initializing a measurement by estimating an initial clock drift ?DHinit between said transmitter and said at least one ultra wide band receiver, thereby generating an estimated clock drift, executing an iterative loop, wherein executing said iterative loop comprises integrating at least one received primary signal, said at least one received primary signal composed of at least two samples, wherein integrating said at least one received primary signal comprises a first integration, and at least one of a second integration and a third integration, wherein said first integration uses said estimated clock drift, said second integration uses said estimated clock drift increased by a predetermined value, and said third integration uses said estimated clock drift decreased by a predetermined value, and selecting from among said integrations an integration that maximizes a quality criterion.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: June 10, 2014
    Assignee: Commissariat à L'Ènergie Atomique et aux Ènergies Alternatives
    Inventors: Christophe Villien, Norbert Daniele
  • Patent number: 8749289
    Abstract: A multi-phase clock generator may receive an input clock signal as an input. The clock generator may also receive an inverse of the input clock signal. The clock generator may produce a plurality of output clock signals having different phases. The phases of the output clock signals may be evenly spaced. The output clock signals may have a similar waveform to the input clock signal, with a frequency that is lower than the input clock signal by a division factor.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: June 10, 2014
    Assignee: Intel Corporation
    Inventors: Shenggao Li, Roan M. Nicholson
  • Patent number: 8736337
    Abstract: A clock signal capable of changing the frequency in a wide range and with high resolution is generated. An operational amplifier AMP1 is subject to feedback control so that the voltage of a positive input part equals that of a negative input part. The voltage of a circuit node fbck equals a reference voltage VREFI. A decoder DEC decodes control signals CNT7 and CNT6 and turns on one of transistors T2 to T5. This configuration provides feedback control so that the voltage of the circuit node fbck equals the reference voltage VREFI. This significantly reduces the on-resistances of the transistors T2 to T5 and prevents the degradation of the frequency accuracy.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: May 27, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Kosuke Yayama, Takashi Nakamura
  • Patent number: 8736339
    Abstract: This invention includes a clock tree to which clock signals are distributed, and a phase comparison circuit configured to detect the phase difference between a plurality of feedback clock signals upon receiving the plurality of feedback clock signals output from different branching points of the clock tree. The invention includes a feedback clock signal generation circuit configured to generate a variation-corrected feedback clock signal for correcting a manufacture variation in the semiconductor integrated circuit based on the phase difference detected by the phase comparison circuit. The invention includes a phase regulation circuit configured to delay the clock signal so as to reduce the phase difference between a reference clock signal and the variation-corrected feedback clock signal generated by the feedback clock signal generation circuit.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: May 27, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Shigeo Kawaoka
  • Patent number: 8710892
    Abstract: A clock distribution circuit is provided with a clock generation circuit configured to generate a clock signal, a clock distribution network in which the clock signal is distributed, and a sequential circuit configured to operate on the clock signal distributed through a branch point of the clock distribution network. The clock distribution circuit is further provided with a clock generation circuit configured to input as a feedback signal the clock signal that has branched from the branch point and to output the clock signal to the clock distribution network based on the inputted feedback signal and a reference clock signal. The branch point is provided at a clock driver near the clock generation circuit, among preceding stage clock drivers of the sequential circuit of the clock distribution network.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: April 29, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Kazuya Fujimori
  • Patent number: 8704577
    Abstract: A clock mesh network synthesis method is proposed which enables clock gating on the local sub-trees of the clock mesh network in order to reduce the clock power dissipation. Clock gating is performed with a register clustering strategy that considers both i) the similarity of switching activities between registers in a local area and ii) the timing slack on every local data path of the design area. The method encapsulates the efficient implementation of the gated local trees and activity driven register clustering with timing slack awareness for clock mesh synthesis. With gated local tree and activity driven register clustering, the switching capacitance on the mesh network can be reduced by 22% with limited skew degradation. The method has two synthesis modes as low power mode and high performance mode to serve different design purposes.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: April 22, 2014
    Assignee: Drexel University
    Inventors: Baris Taskin, Jianchao Lu
  • Patent number: 8704555
    Abstract: An integrated circuit comprises reference voltage generation circuitry for providing a reference voltage for use within a transmission of electrical signals. The reference voltage generation circuitry comprises a reference voltage node operably coupled via a plurality of resistance elements to a plurality of signal nodes such that the reference voltage node assumes as the reference voltage an average of the voltage values of the signal nodes to which it is coupled.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: April 22, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Anton Rozen, Dan Kuzmin, Michael Priel
  • Patent number: 8692586
    Abstract: An output circuit providing isolation between inputs and the output employs first and second opto-couplers for isolation. Pulse activation of the first opto-coupler turns on an output transistor and pulse activation of the second opto-coupler turns off the output transistor. An input stage of the output circuit is and light emitting devices of the first and second opto-couplers are powered by a first power source and an output stage of the output circuit is powered from an external power source. Power consumption by the input stage of output circuit occurs only during pulse activation of the first and second opto-couplers.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: April 8, 2014
    Assignee: Precision Digital Corporation
    Inventor: Wayne Shumaker
  • Patent number: 8664996
    Abstract: A clock generator utilized for providing a clock signal includes: a first oscillator and a switching circuit. The switching circuit is coupled to the first oscillator and a second oscillator, and utilized for receiving a first oscillating signal generated from the first oscillator and a second oscillating signal generated from the second oscillator, and selecting one of the first oscillating signal and the second oscillating signal as the clock signal according to a status signal.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: March 4, 2014
    Assignee: Mediatek Inc.
    Inventors: Chun-Ming Kuo, Wen-Chi Chao, Keng-Jan Hsiao, Song-Yu Yang, Chun-Chi Chen
  • Publication number: 20140055180
    Abstract: A clock driver includes a clock interconnect running to multiple lanes of an integrated circuit chip, the interconnect including a positive clock line and a negative clock line. A clock generator generates a clock signal and a source inductor, through which the clock generator draws DC power, helps drive the clock signal down the interconnect. The source inductor may be tunable. A distributed (or tunable) inductor is connected to and positioned along the positive and negative clock lines between the source inductor and an end of the interconnect. Multiple distributed inductors may be positioned and optionally tuned such as to create a resonant response in the clock signal with substantially similar quality and amplitude as delivered to the multiple lanes. Any of the distributed and source inductors may be switchable to change inductance of the distributed inductors and thus change the clock frequency in the lanes for different communication standards.
    Type: Application
    Filed: September 18, 2012
    Publication date: February 27, 2014
    Applicant: Broadcom Corporation
    Inventors: Adesh Garg, Jun Cao
  • Patent number: 8659588
    Abstract: A display substrate includes a base substrate including a display area and a peripheral area, a pixel disposed on the display area, wherein the pixel includes; a pixel transistor connected to a gate line and a data line which cross each other, and a pixel electrode connected to the pixel transistor and the pixel electrode, and a gate driving circuit disposed on the peripheral area, wherein the gate driving circuit outputs a gate signal to the gate line and comprises a plurality of stages, an n-th stage of the gate driving circuit including a plurality of circuit transistors and a boosting capacitor including a first capacitor and a second capacitor, the plurality of circuit transistors and the first capacitor being disposed on a first area and the second capacitor being disposed on a second area of the peripheral area positioned between the first area and the display area.
    Type: Grant
    Filed: May 19, 2011
    Date of Patent: February 25, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventor: Bon-Yong Koo
  • Patent number: 8638153
    Abstract: Systems and methods for generating pulse clocks with programmable edges and pulse widths configured for varying requirements of different memory access operations. A pulse clock generation circuit includes a selective delay logic to provide a programmable rising edge delay of the pulse clock, a selective pulse width widening logic to provide a programmable pulse width of the pulse clock, and a built-in level shifter for shifting a voltage level of the pulse clock. A rising edge delay for a read operation is programmed to correspond to an expected read array access delay, and the pulse width for a write operation is programmed to be wider than the pulse width for a read operation.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: January 28, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Shaoping Ge, Chiaming Chai, Stephen Edward Liles, Lam V. Nguyen, Jeffrey Herbert Fischer
  • Publication number: 20140021998
    Abstract: A circuit for skew reduction, includes: first signal lines configured to transmit first signals delayed by first paths respectively; second signal lines configured to transmit second signals delayed by second paths respectively; and a first swap circuit, wherein the first swap circuit is configured to swap and connect the at least one of the first signal lines to the at least one of the second signal lines, when a mutual delay time difference of the second signals in a state where the at least one of the first signal lines is swapped and connected to the at least one of the second signal lines is smaller than a mutual delay time difference of the second signal lines in a state where the first signal lines is connected to the second signal lines without being swapped.
    Type: Application
    Filed: July 18, 2013
    Publication date: January 23, 2014
    Inventors: Yutaka NEMOTO, Yoshimasa OGAWA
  • Patent number: 8633774
    Abstract: Improvements in and relating to electronic pulse generation or oscillation circuitry based on a signal path exhibiting endless electromagnetic continuity and affording signal phase inversion in setting pulse duration or half-cycles of oscillation within time of signal traverse of said signal path, and having active switching means associated with said signal path to set rise and fall times of each said pulse or said half-cycle of oscillation, including for frequency adjustment by selective inductance and power saving without stopping pulse generation or oscillation.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: January 21, 2014
    Assignee: Analog Devices, Inc.
    Inventor: John Wood
  • Patent number: 8618858
    Abstract: A pulse generator is provided. The pulse generator includes: a time delayed pulse generation unit including a plurality of delay cells for receiving a first pulse having a first pulse width and outputting pulses delayed by a particular time delay value on the basis of one of a rising edge and a falling edge of the first pulse; an edge combiner configured to receive the plurality of time delayed pulses from the time delayed pulse generation unit and generate second pulses having a second pulse width; and a channel selector configured to regulate the number of outputs of the second pulses generated by the edge combiner.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: December 31, 2013
    Assignees: Electronics and Telecommunications Research Institute, Unist Academy—Industry Corporation
    Inventors: Jae Hwan Kim, Hyung Soo Lee, Sang Sung Choi, Kyeong Deok Moon, Yun Ho Choi, Young Su Kim, Franklin Bien
  • Publication number: 20130342257
    Abstract: A hardware/PLC logic combination which enables measurement of a plurality of analog voltage points (e.g., multiples of 8 points) on a single high speed PLC input without separate synchronization inputs or outputs. This is accomplished through the use of a multiplexer circuit [clock, binary counter, analog multiplexer, voltage to frequency converter], and a high speed counter function at the PLC. Synchronization between the PLC and circuit is through the detection of a fixed voltage on channel “one” of the circuit, which is set well above the typical range (e.g., 0-10V) of the remaining analog inputs.
    Type: Application
    Filed: June 19, 2013
    Publication date: December 26, 2013
    Applicant: M&R Printing Equipment, Inc.
    Inventor: Keith R. Falk
  • Patent number: 8593200
    Abstract: A clock generator includes a counter unit receiving a reference clock signal to generate a timing signal, a selector receiving the timing signal to output a clock enable based on bit string data stored in a storage unit and a clock gate cell receiving the reference clock signal based on the clock, thinning some pulses out from the reference clock signal based on the clock enable so that a clock signal is maskable, and outputting an inter intermittent clock signal.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: November 26, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Takahiro Minaki
  • Patent number: 8581654
    Abstract: A method of compensating clock skew may include generating (2M+1) detected values by applying (2M+1) delay clock signals to (2M+1) pieces of delay data, wherein M is a natural number, determining a dominant logic value based on a comparison of a number of logic high detected values and a number of logic low detected values from among the (2M+1) detected values, determining a median delay time based on a number of the (2M+1) detected values having the dominant logic value, and adjusting a phase of a clock signal using the median delay time.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: November 12, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hee-dong Kim
  • Patent number: 8570088
    Abstract: There is provided a synchronization circuit for a 3D chip stack having multiple circuits and multiple strata interconnected using a first and a second stack-wide broadcast connection chain. The synchronization circuit includes the following, on each stratum. A synchronizer connected to the first connection chain receives an asynchronous signal therefrom and performs a synchronization to provide a synchronous signal. A driver is connected to the second chain for driving the synchronous signal. A latch connected to the second chain receives the synchronous signal driven by the driver on a same or different stratum within a next clock cycle from the synchronization to provide the stack-wide synchronous signal to a circuit on a same stratum. An output of a single driver on one stratum is selected at any given time for use by the latch on all strata.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: October 29, 2013
    Assignee: International Business Machines Corporation
    Inventors: Joel A. Silberman, Matthew R. Wordeman
  • Patent number: 8564354
    Abstract: Circuits and methods for latch-tracking pulse generation across process, voltage and temperature (PVT) variations are disclosed. In one embodiment, the method includes receiving a clock input at a pulse generation circuit and generating a pulse at the pulse generation circuit in response to the clock input. The method further includes distributing the pulse to a mimic latch, which writes a mimic storage node through a mimic storage circuit of the mimic latch in response to the pulse. The method further includes terminating generation of the pulse at the pulse generation circuit in response to a transition of the mimic storage node. The method may include receiving a clock enable input at a pulse control circuit coupled to the pulse generation circuit and either suppressing or allowing generation of a pulse in response to a value of the clock enable input.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: October 22, 2013
    Assignee: QUALCOMM Incorporated
    Inventor: Fadi Adel Hamdan
  • Patent number: 8558600
    Abstract: A clock signal generation circuit includes a first oscillation circuit for generating a first oscillation clock signal having a first frequency; a second oscillation circuit for generating a second oscillation clock signal having a second frequency; a frequency division circuit for generating a frequency division clock signal obtained through dividing the first oscillation clock signal; and a clock selection circuit for outputting the first oscillation clock signal as a high speed clock signal. The clock selection circuit is configured to output the second oscillation clock signal as the low speed clock signal when the second oscillation circuit transmits the second oscillation clock signal, and to output the frequency division clock signal as the low speed clock signal when the second oscillation circuit does not transmit the second oscillation clock signal.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: October 15, 2013
    Assignee: Lapis Semiconductor Co., Ltd.
    Inventor: Kenichi Natsume
  • Patent number: 8558599
    Abstract: A clock network includes a first plurality of shield wires associated with a first plurality of clock lines and a second plurality of shield wires associated with a second plurality of clock lines. The clock network also includes a first plurality of clock activity program circuits associated with the first plurality of clock lines and a second plurality of clock activity program circuits associated with the second plurality of clock lines, wherein the first and second plurality of shield wires and the first and second plurality clock activity program circuits are configured to reduce power spikes.
    Type: Grant
    Filed: October 16, 2009
    Date of Patent: October 15, 2013
    Assignee: Altera Corporation
    Inventors: David Lewis, Ryan Fung