Single Clock Output With Single Clock Input Or Data Input Patents (Class 327/299)
  • Patent number: 10249283
    Abstract: The handling of disturbances to audio signals may be improved with an adaptive noise cancellation (ANC) system that performs tone suppression and howl suppression in a collaborative manner. Such ANC systems may be configured to detect a first tone in an input signal at a first tone frequency and extract the detected first tone from the input signal. The ANC systems may also be configured to adaptively filter the extracted first tone to generate a second tone that has a magnitude that is approximately equal to a magnitude of the extracted first tone and a phase that is approximately opposite the phase of the extracted first tone. The ANC systems may be further configured to add the second tone to an intermediate signal that is based, at least in part, on the input signal to generate the output signal.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: April 2, 2019
    Assignee: Cirrus Logic, Inc.
    Inventors: Dayong Zhou, Yang Lu, Jeffrey D. Alderson, Eric King
  • Patent number: 9997829
    Abstract: A Near Field Communication (NFC) enabled device is disclosed. The NFC device includes an antenna. The NFC device also includes an impedance matching network, a carrier frequency generator to generate a carrier wave, a receiver for receiving a magnetic induction wave, a transmitter, a driver circuit configured to alter an impedance of an antenna network associated with the antenna between a first impedance and a second impedance and a control unit. The control unit is configured to derive a first phase difference between the received magnetic induction wave and an internal clock at the first impedance and a second phase difference between the received magnetic induction wave and the internal clock at the second impedance. The control unit is further configured to change a phase of the carrier wave based on a difference between the first phase difference and a second phase difference.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: June 12, 2018
    Assignee: NXP B.V.
    Inventors: Michael Gebhart, Fred George Nunziata, Hubert Watzinger
  • Patent number: 9831858
    Abstract: A clock generator comprises a first capacitor, a current source, and a voltage node. A first switch is coupled between the first capacitor and the current source. A second switch is coupled between the first capacitor and voltage node.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: November 28, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Martin Podzemny
  • Patent number: 9577615
    Abstract: A circuit for reducing duty-cycle distortion in an integrated circuit implementing dual-edge clocking is described. The circuit also comprises a plurality of circuit elements that enable the routing of data generated at outputs of the circuit elements; a plurality of register circuits that store data at outputs of the plurality of circuit elements; a clock circuit routing a clock signal to clock inputs of the plurality of register circuits; and a pulsed-controlled register circuit coupled to an output of a circuit element and generating a pulsed output coupled to a clock input of a register of the pulse-controlled register circuit; wherein the pulsed output is coupled to the clock input of the register to enable the pulse-controlled register circuit to store data at a time that is different than an edge of the clock signal. A method of reducing duty-cycle distortion in an integrated circuit implementing dual-edge clocking is also described.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: February 21, 2017
    Assignee: XILINX, INC.
    Inventors: Ilya K. Ganusov, Benjamin S. Devlin
  • Patent number: 9537477
    Abstract: A semiconductor apparatus includes a multiplication control block configured to generate a plurality of frequency control signals according to an input clock and a multiplication determination signal; and a clock output block configured to generate an output clock according to the input clock, the multiplication determination signal and the plurality of frequency control signals.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: January 3, 2017
    Assignee: SK Hynix Inc.
    Inventor: Choung Ki Song
  • Patent number: 9275711
    Abstract: A command processing circuit of a memory device includes a clock divider, a clock controller and a command decoder. The clock divider generates a plurality of divided clock signals based on an external clock signal having a first frequency. The divided clock signals have a second frequency lower than the first frequency. Each of the divided clock signals has a phase that is different from phases of the other divided clock signals. The clock controller generates an operating clock signal based on a command signal and the divided clock signals, where the command signal is transferred in synchronization with the external clock signal. The operating clock signal has the second frequency and a phase corresponding to reception timing of the command signal. The command decoder decodes the command signal in synchronization with the operating clock signal.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: March 1, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Tae-Young Oh
  • Patent number: 9154118
    Abstract: A pulse delay circuit includes a pull down element, a first pull up element, a first delay unit, a second delay unit, a second pull up element, and an inverted buffer. The pull down element is connected to an input pulse signal, a node b and a first voltage. The first pull up element is connected to a node c, a second voltage and the node b. The first delay unit has a reset terminal. The first delay unit is connected to the node b and the node c. The second delay unit is connected to the node c and the node d. The second pull up element is connected to the node d, the second voltage and the node c. The inverted buffer is connected to the node c and the reset terminal. Moreover, a delayed pulse signal is outputted from the inverted buffer.
    Type: Grant
    Filed: April 10, 2014
    Date of Patent: October 6, 2015
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventor: Huan-Min Lin
  • Patent number: 9094034
    Abstract: A digital to analog converting system, which comprises: a first data converting circuit, for receiving a first digital data stream transmitted at a first clock frequency, for converting the first digital data stream to a plurality of second digital data streams transmitted at a second clock frequency, and for outputting the second digital data streams in parallel; a second data converting circuit, for receiving the second digital data streams from the first data converting circuit, and for converting the second digital data streams to a third digital data stream transmitted at a third clock frequency; and a first digital to analog converter, for converting the third digital data stream to a first output analog data stream. The second clock frequency is lower than the first clock frequency and the third clock frequency.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: July 28, 2015
    Assignee: MEDIATEK INC.
    Inventors: Sheng-Hao Chen, Yen-Chuan Huang, Min-Hua Wu, Chun-Hao Liao, Hung-Pin Ma, Tzu-Hao Yu, Jen-Che Tsai
  • Patent number: 9030246
    Abstract: The disclosed invention provides a semiconductor device capable of suitably controlling the level of an enable signal to resolve NBTI in a PMOS transistor. An input node receives an input signal alternating between high and low levels during normal operation and fixed to a high level during standby. A detection unit receives a signal through the input node and outputs an enable signal. The detection unit sets the enable signal to a low level upon detecting that the input node remains at a high level for a predetermined period. A signal transmission unit includes a P-channel MOS transistor and transmits a signal input to the input node according to control by the enable signal.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: May 12, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Hideki Uchiki, Satoru Kishimoto
  • Patent number: 9024671
    Abstract: Apparatus and methods are provided for an extraction circuit. In one configuration, an apparatus includes: an edge extraction circuit for receiving a first clock signal and outputting a second clock signal, wherein a duty cycle of the second clock is substantially smaller than a duty cycle of the first clock; a transistor for receiving the second clock signal and outputting a current signal; a transmission line for receiving the current signal on a first end and transmitting the current signal to a second end; a termination circuit for receiving the current signal at the second end and converting the current signal into a voltage signal; and an edge detection circuit for outputting a third clock by detecting an edge of the voltage signal. In one embodiment, the edge detection circuit comprises an inverter. In another embodiment, the edge detection circuit comprises a comparator.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: May 5, 2015
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chia-Liang Leon Lin, Joseph Gerchih Chou
  • Patent number: 9024699
    Abstract: Various techniques for generating an output clock based on a reference clock. This disclosure relates to generating an output clock signal based on a reference clock signal. In one embodiment, a method includes generating, using information received from a control circuit, an output clock signal using both a first number of edges or an input clock signal and a second, different number of edges of the input clock signal. In this embodiment, the control circuit runs at a frequency that is less than a frequency of the input clock signal. The received information may indicate, for a pulse of the output clock signal, whether the pulse should be generated using the first number of edges or the second number of edges. In some cases, the second number of edges may be the first number of edges plus one. The first and second number of edges may be programmable quantities.
    Type: Grant
    Filed: January 21, 2013
    Date of Patent: May 5, 2015
    Assignee: Apple Inc.
    Inventors: Kleanthes G. Koniaris, Erik P. Machnicki, Shane J. Keil
  • Patent number: 9018999
    Abstract: A hardware/PLC logic combination which enables measurement of a plurality of analog voltage points (e.g., multiples of 8 points) on a single high speed PLC input without separate synchronization inputs or outputs. This is accomplished through the use of a multiplexer circuit [clock, binary counter, analog multiplexer, voltage to frequency converter], and a high speed counter function at the PLC. Synchronization between the PLC and circuit is through the detection of a fixed voltage on channel “one” of the circuit, which is set well above the typical range (e.g., 0-10V) of the remaining analog inputs.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: April 28, 2015
    Assignee: M&R Printing Equipment, Inc.
    Inventor: Keith R. Falk
  • Publication number: 20150109029
    Abstract: A method for generating a digital signal of tunable frequency may include generating a periodic first analog signal, determining a sign of a first difference between a value of the first analog signal and a first control value to determine sign flips, wherein the first control value is a variable value, and generating the digital signal of tunable frequency on the basis of the determined sign of the first difference, wherein the digital signal of tunable frequency is generated such that a subset of switches of the signal level are coincident with a respective sign flip of the determined sign of the first difference.
    Type: Application
    Filed: May 11, 2012
    Publication date: April 23, 2015
    Applicant: EUROPEAN SPACE AGENCY
    Inventors: Enrico Lia, Andreas Lauer, Dietmar Koether, Rüdiger Follmann
  • Patent number: 9013220
    Abstract: Provided is a semiconductor apparatus including a plurality of semiconductor chips coupled through an electrical coupling unit. Each of the semiconductor chips includes: a chip ID signal generation unit configured to generate a chip ID signal; and a chip enable signal generation unit configured to receive a clock enable signal in response to the chip ID signal, wherein one of the semiconductor chips shares the received clock enable signal as a transfer clock enable signal with the other semiconductor chips, and the chip enable signal generation unit detects whether or not an error occurs in the chip ID signals of the plurality of semiconductor chips, selects any one of the transfer clock enable signal and the clock enable signal applied, and outputs the selected signal as a chip enable signal.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: April 21, 2015
    Assignee: SK Hynix Inc.
    Inventor: Heat Bit Park
  • Patent number: 8994432
    Abstract: A semiconductor integrated circuit and a method operating the same are provided. The semiconductor integrated circuit includes a first clock network configured to divide a clock signal into first output clock signals with a high frequency, a second clock network configured to divide the clock signal into second output clock signals with a non-high frequency, a plurality of selection circuits configured to be connected between the first clock network and the second clock network, and configured to output one of the first output clock signals and the second output clock signals, according to a power mode, and a plurality of clock sinks configured to sink output clock signals respectively output from the selection circuits.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: March 31, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hoi Jin Lee
  • Publication number: 20150069987
    Abstract: One example of generating a clock signal via an oscillator system includes increasing a first comparison voltage at a first comparison node from a first magnitude to a second magnitude in response to a clock signal. A second comparison voltage is increased at a second comparison node from the first magnitude to the second magnitude in response to the clock signal. The clock signal changes state in response to the second comparison voltage increasing to a magnitude that is greater than the first comparison voltage. The first comparison voltage decreases from the second magnitude to the first magnitude in response to the clock signal. The second comparison voltage decreases from the second magnitude to the first magnitude in response to the clock signal. The clock signal changes state in response to the second comparison voltage decreasing to a magnitude that is less than the first comparison voltage.
    Type: Application
    Filed: October 17, 2014
    Publication date: March 12, 2015
    Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: F. Dong Tan, Kwang M. Yi
  • Patent number: 8975949
    Abstract: Inventive aspects include an integrated clock gater (ICG) circuit having clocked complimentary voltage switched logic (CICG) that delivers high performance while maintaining low power consumption characteristics. The CICG circuit provides a small enable setup time and a small clock-to-enabled-clock delay. A significant reduction in clock power consumption is achieved in both enabled and disabled modes, but particularly in the disabled mode. Complimentary latches work in tandem to latch different voltage levels at different nodes depending on the voltage level of the received clock signal and whether or not an enable signal is asserted. An inverter takes the voltage level from one of the nodes, inverts it, and outputs a gated clock signal. The gated clock signal may be active or quiescent depending on the various voltage levels. Time is “borrowed” from an evaluation window and added to a setup time to provide greater tolerances for receiving the enable signal.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Matthew S. Berzins, Prashant U. Kenkare
  • Publication number: 20150062977
    Abstract: Embodiments of the invention provide a method and a circuit for generating a reference signal for controlling a peak current of a converter switch. According to at least one embodiment, the circuit includes a squarer configured to squire an input voltage signal divided from a primary-side supply voltage of an isolated converter, and a duty ratio calculator configured to calculate a duty ratio of energy transfer to a secondary side. The circuit further includes an operator configured to generate and output a reference signal for controlling the peak current of the converter switch from a square signal of the input voltage signal using the duty ratio of energy transfer calculated by the duty ratio calculator.
    Type: Application
    Filed: August 29, 2014
    Publication date: March 5, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Yun Joong LEE, Deuk Hee PARK, Chan Woo PARK, Jong Tae HWANG, Je Hyeon YU, Soo Hyun MOON, Hye Jin LEE, Chang Seok LEE, Sang Hyun CHA
  • Patent number: 8970267
    Abstract: This invention is a means to definitively establish the occurrence of various clock edges used in a design, balancing clock edges at various locations within an integrated circuit. Clocks entering from outside sources can be a source of on-chip-variations (OCV) resulting in unacceptable clock edge skewing. The present invention arranges placement of the various clock dividers on the chip at remote locations where these clocks are used. This minimizes the uncertainty of the edge occurrence.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: March 3, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Raguram Damodaran, Abhijeet Ashok Chachad, Ramakrishnan Venkatasubramanian
  • Patent number: 8970274
    Abstract: A pulse latch includes a pulse generator and a latch circuit. The pulse generator generates first and second pulse signals. The first pulse signal is generated when a test enable signal is in a first state, and the second pulse signal is generated when the test enable signal is in a second state. The latch circuit outputs the latched signal by selectively latching a normal data input signal or a test data input signal. The latch circuit includes first and second tri-state elements. The first tri-state element is controlled by the first pulse signal to enable the test data input signal to be latched when the test enable signal is in the first state. The second tri-state element is controlled by the second pulse signal to enable the normal data input signal to be latched when the test enable signal is in the second state.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: March 3, 2015
    Assignee: MediaTek Singapore Pte. Ltd.
    Inventors: Joseph Patrick Geisler, Kin Hooi Dia
  • Patent number: 8957720
    Abstract: A sampling clock generator circuit includes a reference clock generator, a sampling hold circuit, a sampling clock generator to delay an output clock signal from the reference clock generator by a predetermined delay amount to generate and supply a sampling clock signal to the sampling hold circuit, a phase determining element to compare phases of a drive clock signal for an image reading unit and the sampling clock signal to output a result of the phase comparison, the drive clock signal generated according to the output clock signal of the reference clock generator, and a controller to adjust the delay amount of the sampling clock generator on the basis of the result of the phase comparison so that a phase difference between the drive clock signal and the sampling clock signal becomes zero.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: February 17, 2015
    Assignee: Ricoh Company, Ltd.
    Inventors: Isamu Miyanishi, Tohru Kanno
  • Patent number: 8952740
    Abstract: A pulsed latching apparatus and a method for generating a pulse signal are provided. The pulsed latching apparatus consists of a pulsed latch and a pulse signal generator. A data input terminal of the pulsed latch receives input data, the pulsed latch latches the input data according to a pulse signal, and transmits the latched input data through the data output terminal to serve as output data. The pulse signal generator duplicates a data transmission delay between the data input terminal and the data output terminal of the pulsed latch to obtain a duplicated delay. The pulse signal generator receives a clock signal, and processes the clock signal according to the duplicated delay to generate the pulse signal.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: February 10, 2015
    Assignee: Industrial Technology Research Institute
    Inventor: Shien-Chun Luo
  • Patent number: 8947143
    Abstract: The duty cycle corrector for correcting a system clock signal comprises a duty cycle detector and a duty cycle adjuster. The duty cycle detector is configured for detecting a system duty cycle of the system clock signal and generating the first control signal and the second control signal, wherein the first control signal and the second control signal are complementary to each other. The duty cycle adjuster comprises an inverter and the duty cycle adjuster is configured for delaying a change in an input status of the inverter and adjusting of the inverter in accordance with the first control signal and the second control signal.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 3, 2015
    Assignee: Nanya Technology Corporation
    Inventor: Yan-Tao Ma
  • Patent number: 8937511
    Abstract: A system including a plurality of amplifiers configured to generate a clock signal having a frequency. The clock signal is input to a processor. The amplifiers are connected in series. An output of a last one of the amplifiers is fed back to an input of a first one of the amplifiers. Each of the amplifiers has a transconductance. A frequency adjustment module is configured to adjust, based on an activity level of the processor, the frequency of the clock signal by adjusting the transconductance of the amplifiers.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: January 20, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Pantas Sutardja, Sehat Sutardja
  • Publication number: 20150002204
    Abstract: An IC is disclosed which includes multiple sectors, each having a resonant clock distribution structure and a sector clock buffer. The sector clock buffer can drive a clock signal onto the resonant clock distribution structure, in response to received clock signal and control signals. The sector clock buffer includes a first driver circuit, with a first impedance to drive the clock signal during a first portion of first and second clock phases. The first driver circuit may cause oscillation of the resonant clock distribution structure. The sector clock buffer includes a second driver circuit, having a second impedance higher than the first impedance. The second driver circuit may maintain the clock signal during a second portion of the first and second clock phases, in response to the control signal. The second driver circuit may maintain the resonant clock distribution structure at one of two voltages.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Inventors: Anthony G. Aipperspach, Roger J. Gravrok, Mark G. Veldhuizen
  • Publication number: 20150003139
    Abstract: A memory storage device, a memory control circuit unit, and a clock adjusting circuit disposed on a plurality of layers are provided. The clock adjusting circuit includes a detection circuit, a control voltage generating circuit, and a voltage-controlled oscillator (VCO). The detection circuit detects a signal characteristic difference between an input signal and an output signal to generate a first signal. The control voltage generating circuit is coupled to the detection circuit and generates a control voltage according to the first signal. The VCO is coupled to the control voltage generating circuit and includes an inductor and a capacitor. The VCO receives the control voltage and starts oscillating according to an impedance characteristic of the inductor and the capacitor to generate the output signal. The inductor is disposed on a pad layer among the layers. Thereby, the manufacturing cost is reduced.
    Type: Application
    Filed: August 28, 2013
    Publication date: January 1, 2015
    Applicant: Phison Electronics Corp.
    Inventors: Wei-Yung Chen, Yan-An Lin
  • Patent number: 8922248
    Abstract: A integrated circuit includes a clock control signal generation circuit configured to generate a clock control signal using transition of a control signal, a clock control unit configured to activate a control clock in an activated period of the clock control signal, and to deactivate the control clock in a deactivated period of the clock control signal, and a control circuit configured to operate in response to the control signal and in synchronization with the control clock.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: December 30, 2014
    Assignee: SK hynix Inc.
    Inventor: Choung-Ki Song
  • Patent number: 8912830
    Abstract: A method and apparatus for atomic frequency and voltage changes in the processor. In one embodiment of the invention, the atomic frequency and voltage changes in the processor is feasible due to the enabling technology of fully integrated voltage regulators (FIVR) that are integrated in the processor. FIVR allows independent configuration of each core in the processor and the configuration includes, but is not limited to, voltage setting, frequency setting, clock setting and other parameters that affects the power consumption of each core.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: December 16, 2014
    Assignee: Intel Corporation
    Inventors: Shaun M. Conrad, Jeremy J. Shrall
  • Publication number: 20140361822
    Abstract: There are provided a pulse generator capable of securing a maximum transfer rate of an IR-UWB signal, while maintaining low power consumption characteristics of an all-digital scheme, and a method for generating a fine pulse. A bandwidth of a fine pulse is determined by adjusting a difference in delay time between two adjacent pulses and a pulse is generated by selecting only one of a rising edge and a falling edge of an input pulse, and thus there is no need to remove an unnecessary batch of pulses afterwards and a transfer rate is enhanced.
    Type: Application
    Filed: June 10, 2014
    Publication date: December 11, 2014
    Inventors: Franklin Bien, Kyung Min NA, Yun Ho CHOI, Sai Kiran Oruganti
  • Publication number: 20140355365
    Abstract: Various circuits and methods of operating circuits are disclosed. A circuit may include a pulse generator and a latch having an output configured to trigger the pulse generator, wherein the latch is configured to be set by an input signal and reset by feedback from the pulse generator. A method may include resetting a latch using feedback from a pulse generator by setting a latch using an input signal, triggering a pulse generator using an output from the latch, and resetting the latch using feedback from the pulse generator.
    Type: Application
    Filed: June 4, 2013
    Publication date: December 4, 2014
    Inventors: Changho Jung, Nishith Desai, Chulmin Jung
  • Publication number: 20140354341
    Abstract: Chip instrumentation determines, in-situ, an allowable increase over product specification in the operating frequency of at least one clock domain in an integrated circuit for a given set of environmental, power supply and/or functionality constraints. Information on the allowable increase in operating frequency for the at least one clock domain is provided to circuits and/or software to effect change in operating frequency.
    Type: Application
    Filed: June 26, 2013
    Publication date: December 4, 2014
    Inventor: Rafael CARMON
  • Publication number: 20140354340
    Abstract: Embodiments provide, among other things, a circuit including a frequency generator and a charge pump. In embodiments, the frequency generator may be configured to provide the charge pump with a clock signal at a first frequency for a predefined period of time. Thereafter, the frequency generator may provide the charge pump with a clock signal at one or more other frequencies. In embodiments, the first frequency may enable the charge pump to settle in a reduced period of time when compared with the one or more other frequencies.
    Type: Application
    Filed: June 3, 2013
    Publication date: December 4, 2014
    Inventor: Dharma Reddy Kadam
  • Patent number: 8890595
    Abstract: Embodiments of a device and circuit implementing a digitally controlled oscillator with reduced analog components. In an example, the digitally controlled oscillator can include a phase accumulator controlled by a stall circuit to selective stall the phase accumulator. In some examples, the digitally controlled oscillator can include a phase select circuit to select multiple phases of a phase select circuit based on the output of the phase accumulator. In some examples, these selected phases can then be used by a phase interpolator to generate a synthetic clock signal.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: November 18, 2014
    Assignee: Fmax Technologies, Inc.
    Inventor: Iain Ross Mactaggart
  • Patent number: 8884676
    Abstract: A clock generator circuit for producing a clock output having a controlled duty cycle is disclosed. A bi-stable circuit provides the clock output which is switchable to a first state in response to an edge of the input clock signal and to a second state in response to a feedback signal. A duty cycle detection circuit is configured to source a current to a node and to sink a current from the node depending upon the output clock state. A capacitor is connected to receive a duty cycle current relating to the current at the node, with a comparator circuit being configured to sense a voltage on the capacitor and to produce the feedback signal when the voltage is at a selected level.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: November 11, 2014
    Assignee: National Semiconductor Corporation
    Inventor: Kern Wai Wong
  • Patent number: 8878586
    Abstract: A clock synchronization system and method avoids output clock jitter at high frequencies and also achieves a smooth phase transition at the boundary of the coarse and fine delays. The system may use a single coarse delay line configured to generate two intermediate clocks from the input reference clock and having a fixed phase difference therebetween. The coarse delay line may have a hierarchical or a non-hierarchical structure. A phase mixer receives these two intermediate clocks and generates the final output clock having a phase between the phases of the intermediate clocks. The coarse shifting in the delay line at high clock frequencies does not affect the phase relationship between the intermediate clocks fed into the phase mixer. The output clock from the phase mixer is time synchronized with the input reference clock and does not exhibit any jitter or noise even at high clock frequency inputs. Because of the rules governing abstracts, this abstract should not be used to construe the claims.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: November 4, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Jongtae Kwak, Kang-Yong Kim
  • Patent number: 8872683
    Abstract: Operating capacitive sensors in force feedback mode has many benefits, such as improved bandwidth, and lower sensitivity to process and temperature variation. To overcome, the non-linearity of the voltage-to-force relation in capacitive feedback, a two-level feedback signal is often used. Therefore, a single-bit ?-? modulator represents a practical way to implement capacitive sensors interface circuits. However, high-Q parasitic modes that exist in high-Q sensors (operating in vacuum) cause a stability problem for the ?-? loop, and hence, limit the applicability of ?-? technique to such sensors. A solution is provided that allows stabilizing the ?-? loop, in the presence of high-Q parasitic modes. The solution is applicable to low or high order ?-? based interfaces for capacitive sensors.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: October 28, 2014
    Assignee: Si-Ware Systems
    Inventors: Ayman Ismail, Ahmed Elshennawy, Ahmed Mokhtar, Ayman Elsayed
  • Patent number: 8872564
    Abstract: The disclosed invention provides a semiconductor device capable of suitably controlling the level of an enable signal to resolve NBTI in a PMOS transistor. An input node receives an input signal alternating between high and low levels during normal operation and fixed to a high level during standby. A detection unit receives a signal through the input node and outputs an enable signal. The detection unit sets the enable signal to a low level upon detecting that the input node remains at a high level for a predetermined period. A signal transmission unit includes a P-channel MOS transistor and transmits a signal input to the input node according to control by the enable signal.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: October 28, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Hideki Uchiki, Satoru Kishimoto
  • Patent number: 8872567
    Abstract: A circuit adapted to generate a high speed shaped pulse comprising an input adapted to receive a data signal and a control signal. A plurality of logic elements are configures to receive the data signal and the control signal and generate a plurality of output signals representative of the shaped pulse. A digital to analog converter is adapted to receive the plurality of output signals and generate a shaped pulse.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: October 28, 2014
    Inventor: Matthias Frei
  • Patent number: 8854101
    Abstract: An adaptive clock generating apparatus is provided. The apparatus includes a fixed frequency divider, a replica, a counter, a variable frequency divider. The adaptive clock generating apparatus generates a clock whose period varies along with changes in the critical path delay of a synchronous circuit.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: October 7, 2014
    Assignee: Korea University Research and Business Foundation
    Inventors: Jong Sun Park, Woo Jin Rim
  • Publication number: 20140292391
    Abstract: A semiconductor integrated circuit includes an identification information storage, an intermediate clock generator and an operating clock generator. The identification information storage stores identification information of the semiconductor integrated circuit. The intermediate clock generator generates an intermediate clock having a frequency higher than that of a reference clock using the reference clock input to the semiconductor integrated circuit from the outside of the semiconductor integrated circuit. The operating clock generator generates the operating clock having a frequency higher than that of the reference clock and lower than that of the intermediate clock in synchronization with a timing allotted according to the identification information stored in the identification information storage, using the intermediate clock.
    Type: Application
    Filed: March 31, 2014
    Publication date: October 2, 2014
    Applicant: KYOCERA Document Solutions inc.
    Inventor: Masataka Takemura
  • Patent number: 8847625
    Abstract: A multi-valued logic (MVL) circuit includes a MVL clock generator that generates a MVL clock signal having three or more ith MVL levels, a single MVL clock signal distribution network connected to the MVL clock generator, and three or more ith MVL selection circuits connected to the single MVL clock signal distribution network where i=0 to N and N>=3. Each ith MVL selection circuit corresponds to a specified ith MVL level. The ith MVL selection circuit outputs an ith binary clock signal having: (a) a first logic level whenever the MVL clock signal is equal to the ith MVL level and the ith data input receives the first logic level, (b) a second logic level whenever the MVL clock signal is equal to the ith MVL level and the ith data input receives the second logic level, and (c) a previous logic level of the ith binary clock signal whenever the MVL clock signal is not equal to the ith MVL level.
    Type: Grant
    Filed: February 16, 2013
    Date of Patent: September 30, 2014
    Assignee: Southern Methodist University
    Inventors: Mitchell Aaron Thornton, Rohit Menon
  • Publication number: 20140283600
    Abstract: Disclosed herein are a gyro sensor driver and a pulse translation device used thereof. The gyro sensor driver, includes: a phase shifter that delays a signal output from an output terminal of a vibrating sensor to output a phase-shifted signal; a comparator that inverts a signal output from the phase shifter to output a clock signal; a reference voltage generator that generates and outputs reference voltage; and a pulse translator that receives the reference voltage output from the reference voltage generator and the clock signal output from the comparator to generate and output a signal of a predetermined pulse, thereby generating a desired driving signal with low current.
    Type: Application
    Filed: May 24, 2013
    Publication date: September 25, 2014
    Inventors: Sung Tae Kim, Young Kil Choi, Jun Kyung Na, Seung Chul Pyo, Chang Hyun Kim
  • Patent number: 8836403
    Abstract: A clock driver circuit supplies a clock signal with a drive strength determined according to one or more control signals supplied to the clock driver that vary during run-time. The clock driver is operated with a first drive strength in a non-resonant mode of operation of an associated clock network and with a second drive strength in a resonant mode of operation of the associated clock network, the first drive strength being higher than the second drive strength.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: September 16, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Visvesh S. Sathe, Srikanth Arekapudi, Samuel D. Naffziger, Manivannan Bhoopathy
  • Patent number: 8823434
    Abstract: An operation clock generation circuit performs a calculation on the basis of the frequency errors of a fundamental clock and the clock pulses of the fundamental clock, and generates an operation clock obtained by correcting the frequency errors at first intervals. A correction clock generation circuit converts a lower-bit value that is a value represented by the bits lower than the predefined bit used for judging the change of the state of the operation clock into a count number of the clock pulses of a second clock whose frequency is higher than that of the operation clock, generates a correction clock obtained by correcting the operation clock on the basis of a time required for counting the count number of the clock pulses and the clock pulses of the operation clock.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: September 2, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Tomoki Yasukawa, Kazuyoshi Kawai
  • Publication number: 20140218094
    Abstract: A method for converting a sine wave signal into a square wave signal includes inputting the sine wave signal at an input of a threshold-value device that generates the square wave signal. The square wave signal is generated by comparing a sine wave signal value to a predefined threshold value, and the square wave signal is output at an output of the threshold-value device. An actuating signal is superposed on the sine wave signal at the input of the threshold-value device. The actuating signal is generated by forming an average-value signal representing an average value of the square wave signal and inputting the average-value signal at an input of a control amplifier device for generating, as the actuating signal, a signal representing a difference between an average-value signal actual value and a predefined average-value signal nominal value.
    Type: Application
    Filed: February 1, 2014
    Publication date: August 7, 2014
    Inventor: Ralph Oppelt
  • Patent number: 8797083
    Abstract: Methods of operating timers include generating a periodic timing signal having a first frequency that differs from a desired timer frequency (1 KHz) by a first amount. This periodic timing signal having the first frequency can be generated by dividing a frequency of an input clock signal (e.g., 32.768 KHz) by N, where N is a positive integer greater than one. A typical value of N may be 32. The methods also include techniques to inhibit timing error accumulation by switching a frequency of the periodic timing signal from the first frequency to a second frequency that differs from the desired timer frequency by a second amount. This periodic timing signal having the second frequency can be generated by dividing the frequency of the input clock signal by M, where M is a positive integer unequal to N (e.g., M?N equals ±1).
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: August 5, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seung Kyu Kim
  • Patent number: 8791742
    Abstract: A clock driver includes a clock interconnect running to multiple lanes of an integrated circuit chip, the interconnect including a positive clock line and a negative clock line. A clock generator generates a clock signal and a source inductor, through which the clock generator draws DC power, helps drive the clock signal down the interconnect. The source inductor may be tunable. A distributed (or tunable) inductor is connected to and positioned along the positive and negative clock lines between the source inductor and an end of the interconnect. Multiple distributed inductors may be positioned and optionally tuned such as to create a resonant response in the clock signal with substantially similar quality and amplitude as delivered to the multiple lanes. Any of the distributed and source inductors may be switchable to change inductance of the distributed inductors and thus change the clock frequency in the lanes for different communication standards.
    Type: Grant
    Filed: September 18, 2012
    Date of Patent: July 29, 2014
    Assignee: Broadcom Corporation
    Inventors: Adesh Garg, Jun Cao
  • Publication number: 20140203884
    Abstract: Various techniques for generating an output clock based on a reference clock. This disclosure relates to generating an output clock signal based on a reference clock signal. In one embodiment, a method includes generating, using information received from a control circuit, an output clock signal using both a first number of edges or an input clock signal and a second, different number of edges of the input clock signal. In this embodiment, the control circuit runs at a frequency that is less than a frequency of the input clock signal. The received information may indicate, for a pulse of the output clock signal, whether the pulse should be generated using the first number of edges or the second number of edges. In some cases, the second number of edges may be the first number of edges plus one. The first and second number of edges may be programmable quantities.
    Type: Application
    Filed: January 21, 2013
    Publication date: July 24, 2014
    Applicant: APPLE INC.
    Inventors: Kleanthes G. Koniaris, Erik P. Machnicki, Shane J. Keil
  • Patent number: 8779824
    Abstract: Clock signals are distributed on a chip by applying an oscillating magnetic field to the chip. Local clock generation circuits including magnetic field sensors are distributed around the chip and are coupled to local clocked circuitry on the chip. The magnetic field sensors may include clock magnetic tunnel junctions (MTJs) in which a magnetic orientation of the free layer is free to rotate in the free layer plane in response to the applied magnetic field. The MTJ resistance alternates between a high resistance value and a low resistance value as the free layer magnetization rotates. Clock generation circuitry coupled to the clock MTJs senses voltage oscillations caused by the alternating resistance of the clock MTJs. The clock generation circuitry includes amplifiers, which convert the sensed voltage into local clock signals.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: July 15, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Wenqing Wu, Kendrick H. Yuen, David W. Hansquine, Robert P. Gilmore, Jeff A. Levin
  • Patent number: 8766695
    Abstract: This disclosure provides examples of circuits, devices, systems, and methods for generating a reference clock signal and delaying a received clock signal based on the reference clock signal. In one implementation, a circuit includes a control block configured to generate a control signal. The circuit includes an oscillator configured to generate a reference clock signal. The oscillator includes a plurality of delay elements each configured to receive the control signal and to introduce a delay in the reference clock signal based on the control signal. The delay elements of the oscillator are arranged to generate the reference clock signal. The circuit further includes a delay block configured to receive a clock signal and to generate a delayed clock signal. The delay block includes one or more delay elements each configured to receive the control signal and to introduce a delay in the clock signal based on the control signal.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: July 1, 2014
    Assignee: SanDisk Technologies Inc.
    Inventor: Ekram H. Bhuiyan