Abstract: The present disclosure provides a circuit and method for expanding the lock range of injection-locked oscillators. The circuit includes N injection-locked oscillators and a lock detector, where the lock detector includes an alignment monitor, a clock selector, and N self-samplers. A pulse reference signal is inputted into the N injection-locked oscillators, and the output of each injection-locked oscillator is connected to the clock selector and the corresponding self-sampler. The self-samplers sample the outputs of the N injection-locked oscillators and output the sampling results to the alignment monitor. The alignment monitor monitors the sampling results, determines the locking conditions of the injection-locked oscillators, and turns off the unlocked oscillators. The clock selector selects a locked oscillator and transmits the output of the locked oscillator as a system lock.

Abstract: An interface circuit and an electronic apparatus, including: a programmable current array (1), generating a first current and a second current transmitted to a common mode and differential mode generation circuit (2) according to an input code, and a third current and a fourth current transmitted to a driving bias generation circuit (3) according to the input code; the common mode and differential mode generation circuit (2), generating a common mode voltage according to the first current, and generating a high level voltage and a low level voltage according to the second current and the common mode voltage; a driving bias generation circuit (3), simulating a load according to the third and fourth currents, and generating a bias voltage based on the load and the low and high level voltages; an output driving circuit (4), converting an input signal into a differential signal in which the common mode voltage and a differential mode amplitude are configurable.

Abstract: A multi-feedback circuit that compares a duty cycle corrected reference clock fREF, and controls a number of identical delay lines to generate a new clock with a frequency that is a multiple (e.g., 32×, 4×, etc.) of the frequency of fREF with approximately 50% duty cycle (DC). The new clock is used as a reference clock to a phase locked loop (PLL) or a multiplying delay locked loop (MDLL) resulting in shorter lock times for the PLL/MDLL, higher bandwidth for the PLL/MDLL, lower long-term output clock jitter. The multi-feedback circuit can also be used as a low power clock generator.

Abstract: A delay synchronization circuit includes a pulse synthesizing circuit to generate a synthesized signal including a first pulse signal synchronized with a reference signal and a second pulse signal synchronized a feedback signal, a VCDL to delay the synthesized signal g and output a delayed synthesized signal, a pulse separation circuit to generate a first separation signal synchronized with a first pulse signal included in the delayed synthesized signal and generate a second separation signal synchronized with a second pulse signal included in the delayed synthesized signal, a circulator to output a first separation signal to a clock reception circuit and then output the first separation signal returned from the clock reception circuit to the pulse synthesizing circuit as the feedback signal, and a delay-amount control circuit to control a delay amount of the delayed synthesized signal according to a phase difference between the reference signal and the second separation signal.

Abstract: In certain aspects, a duty-cycle monitor includes a first oscillator, and a flop having a signal input, a clock input, and an output, wherein the signal input is coupled to an input of the duty-cycle monitor, and the clock input is coupled to the first oscillator. The duty-cycle monitor also includes a first counter having a count input, an enable input, and a count output, wherein the count input of the first counter is coupled to the first oscillator, and the enable input of the first counter is coupled to the output of the flop. The duty-cycle monitor also includes a second counter having a count input, an enable input, and a count output, wherein the count input of the second counter is coupled to the first oscillator, and the enable input of the second counter is coupled to the output of the flop.

Abstract: A clock generator includes a pulse generator and a duty cycle correction circuit. The pulse generator is configured to receive an input clock signal and generate a pulse signal according to the input clock signal. The duty cycle correction circuit, coupled to the pulse generator, is configured to adjust a duty cycle of the pulse signal to generate an output clock signal.

Abstract: The present disclosure relates to a driver for a display device. A driver for a display device according to an embodiment is characterized in generating a voltage supplied as a bias voltage of a source buffer of a data driver in conjunction with a voltage supplied to a display panel. Therefore, the driver for the display device according to the present disclosure has an advantage that the headroom margin of the source buffer can be secured and power consumption of the driver is low at the same time, even when an image data pattern causing a variation in the voltage is input to the display device.

Abstract: A display device including: a display panel including a pixel connected to a first scan line, second scan line, and data line, the pixel including: a first switch connected to the first scan line; a second switch connected to the second scan line; and a light emitting element; a low-frequency driving controller to output a power control signal having a first level in a first mode and a second power control signal having a second level in a second mode; a scan driver including first and second scan drivers to drive the first and second scan lines, wherein one of the first and second scan drivers operates in the second mode; and a data driver to operate in the second mode in response to the power control signal having the second level, wherein the data driver operates at a frequency lower than a reference frequency in the second mode.

Abstract: In an embodiment, a host controller includes a clock control circuit to cause the host controller to communicate a clock signal on a clock line of an interconnect, the clock control circuit to receive an indication that a first device is to send information to the host controller and to dynamically release control of the clock line of the interconnect to enable the first device to drive a second clock signal onto the clock line of the interconnect for communication with the information. Other embodiments are described and claimed.

Abstract: A time arbitration circuit includes: a comparator including at least first and second inputs and configured to provide at least a first data item relative to the synchronization status of the signals present on the first and second inputs; a clock signal generator connected to an output terminal of the time arbitration circuit and delivering an output clock signal; a control circuit configured to enable or disable delivery of the output clock signal on the output terminal according to the first data item from the comparator and to possibly deliver data relative to the synchronization status according to the first data item; the first and second inputs of the comparator are connected to first and second input terminals of the time arbitration circuit designed to be connected to first and second sources delivering first and second clock signals.

Abstract: Methods and apparatuses featuring a multiplying injection-locked oscillator are described. Some embodiments include a pulse-generator-and-injector and one or more injection-locked oscillators. The outputs of the pulse-generator-and-injector can be injected into corresponding injection points of an injection-locked oscillator. In embodiments that include multiple injection-locked oscillators, the outputs of each injection-locked oscillator can be injected into the corresponding injection points of the next injection-locked oscillator. Some embodiments reduce deterministic jitter by dynamically modifying the loop length of an injection-locked oscillator, and/or by using a duty cycle corrector, and/or by multiplexing/blending the outputs from multiple delay elements of an injection-locked oscillator.

Abstract: The handling of disturbances to audio signals may be improved with an adaptive noise cancellation (ANC) system that performs tone suppression and howl suppression in a collaborative manner. Such ANC systems may be configured to detect a first tone in an input signal at a first tone frequency and extract the detected first tone from the input signal. The ANC systems may also be configured to adaptively filter the extracted first tone to generate a second tone that has a magnitude that is approximately equal to a magnitude of the extracted first tone and a phase that is approximately opposite the phase of the extracted first tone. The ANC systems may be further configured to add the second tone to an intermediate signal that is based, at least in part, on the input signal to generate the output signal.

Abstract: A Near Field Communication (NFC) enabled device is disclosed. The NFC device includes an antenna. The NFC device also includes an impedance matching network, a carrier frequency generator to generate a carrier wave, a receiver for receiving a magnetic induction wave, a transmitter, a driver circuit configured to alter an impedance of an antenna network associated with the antenna between a first impedance and a second impedance and a control unit. The control unit is configured to derive a first phase difference between the received magnetic induction wave and an internal clock at the first impedance and a second phase difference between the received magnetic induction wave and the internal clock at the second impedance. The control unit is further configured to change a phase of the carrier wave based on a difference between the first phase difference and a second phase difference.

Abstract: A clock generator comprises a first capacitor, a current source, and a voltage node. A first switch is coupled between the first capacitor and the current source. A second switch is coupled between the first capacitor and voltage node.

Abstract: A circuit for reducing duty-cycle distortion in an integrated circuit implementing dual-edge clocking is described. The circuit also comprises a plurality of circuit elements that enable the routing of data generated at outputs of the circuit elements; a plurality of register circuits that store data at outputs of the plurality of circuit elements; a clock circuit routing a clock signal to clock inputs of the plurality of register circuits; and a pulsed-controlled register circuit coupled to an output of a circuit element and generating a pulsed output coupled to a clock input of a register of the pulse-controlled register circuit; wherein the pulsed output is coupled to the clock input of the register to enable the pulse-controlled register circuit to store data at a time that is different than an edge of the clock signal. A method of reducing duty-cycle distortion in an integrated circuit implementing dual-edge clocking is also described.

Abstract: A semiconductor apparatus includes a multiplication control block configured to generate a plurality of frequency control signals according to an input clock and a multiplication determination signal; and a clock output block configured to generate an output clock according to the input clock, the multiplication determination signal and the plurality of frequency control signals.

Abstract: A command processing circuit of a memory device includes a clock divider, a clock controller and a command decoder. The clock divider generates a plurality of divided clock signals based on an external clock signal having a first frequency. The divided clock signals have a second frequency lower than the first frequency. Each of the divided clock signals has a phase that is different from phases of the other divided clock signals. The clock controller generates an operating clock signal based on a command signal and the divided clock signals, where the command signal is transferred in synchronization with the external clock signal. The operating clock signal has the second frequency and a phase corresponding to reception timing of the command signal. The command decoder decodes the command signal in synchronization with the operating clock signal.

Abstract: A pulse delay circuit includes a pull down element, a first pull up element, a first delay unit, a second delay unit, a second pull up element, and an inverted buffer. The pull down element is connected to an input pulse signal, a node b and a first voltage. The first pull up element is connected to a node c, a second voltage and the node b. The first delay unit has a reset terminal. The first delay unit is connected to the node b and the node c. The second delay unit is connected to the node c and the node d. The second pull up element is connected to the node d, the second voltage and the node c. The inverted buffer is connected to the node c and the reset terminal. Moreover, a delayed pulse signal is outputted from the inverted buffer.

Abstract: A digital to analog converting system, which comprises: a first data converting circuit, for receiving a first digital data stream transmitted at a first clock frequency, for converting the first digital data stream to a plurality of second digital data streams transmitted at a second clock frequency, and for outputting the second digital data streams in parallel; a second data converting circuit, for receiving the second digital data streams from the first data converting circuit, and for converting the second digital data streams to a third digital data stream transmitted at a third clock frequency; and a first digital to analog converter, for converting the third digital data stream to a first output analog data stream. The second clock frequency is lower than the first clock frequency and the third clock frequency.

Abstract: The disclosed invention provides a semiconductor device capable of suitably controlling the level of an enable signal to resolve NBTI in a PMOS transistor. An input node receives an input signal alternating between high and low levels during normal operation and fixed to a high level during standby. A detection unit receives a signal through the input node and outputs an enable signal. The detection unit sets the enable signal to a low level upon detecting that the input node remains at a high level for a predetermined period. A signal transmission unit includes a P-channel MOS transistor and transmits a signal input to the input node according to control by the enable signal.

Abstract: Various techniques for generating an output clock based on a reference clock. This disclosure relates to generating an output clock signal based on a reference clock signal. In one embodiment, a method includes generating, using information received from a control circuit, an output clock signal using both a first number of edges or an input clock signal and a second, different number of edges of the input clock signal. In this embodiment, the control circuit runs at a frequency that is less than a frequency of the input clock signal. The received information may indicate, for a pulse of the output clock signal, whether the pulse should be generated using the first number of edges or the second number of edges. In some cases, the second number of edges may be the first number of edges plus one. The first and second number of edges may be programmable quantities.

Abstract: Apparatus and methods are provided for an extraction circuit. In one configuration, an apparatus includes: an edge extraction circuit for receiving a first clock signal and outputting a second clock signal, wherein a duty cycle of the second clock is substantially smaller than a duty cycle of the first clock; a transistor for receiving the second clock signal and outputting a current signal; a transmission line for receiving the current signal on a first end and transmitting the current signal to a second end; a termination circuit for receiving the current signal at the second end and converting the current signal into a voltage signal; and an edge detection circuit for outputting a third clock by detecting an edge of the voltage signal. In one embodiment, the edge detection circuit comprises an inverter. In another embodiment, the edge detection circuit comprises a comparator.

Abstract: A hardware/PLC logic combination which enables measurement of a plurality of analog voltage points (e.g., multiples of 8 points) on a single high speed PLC input without separate synchronization inputs or outputs. This is accomplished through the use of a multiplexer circuit [clock, binary counter, analog multiplexer, voltage to frequency converter], and a high speed counter function at the PLC. Synchronization between the PLC and circuit is through the detection of a fixed voltage on channel “one” of the circuit, which is set well above the typical range (e.g., 0-10V) of the remaining analog inputs.

Abstract: A method for generating a digital signal of tunable frequency may include generating a periodic first analog signal, determining a sign of a first difference between a value of the first analog signal and a first control value to determine sign flips, wherein the first control value is a variable value, and generating the digital signal of tunable frequency on the basis of the determined sign of the first difference, wherein the digital signal of tunable frequency is generated such that a subset of switches of the signal level are coincident with a respective sign flip of the determined sign of the first difference.

Abstract: Provided is a semiconductor apparatus including a plurality of semiconductor chips coupled through an electrical coupling unit. Each of the semiconductor chips includes: a chip ID signal generation unit configured to generate a chip ID signal; and a chip enable signal generation unit configured to receive a clock enable signal in response to the chip ID signal, wherein one of the semiconductor chips shares the received clock enable signal as a transfer clock enable signal with the other semiconductor chips, and the chip enable signal generation unit detects whether or not an error occurs in the chip ID signals of the plurality of semiconductor chips, selects any one of the transfer clock enable signal and the clock enable signal applied, and outputs the selected signal as a chip enable signal.

Abstract: A semiconductor integrated circuit and a method operating the same are provided. The semiconductor integrated circuit includes a first clock network configured to divide a clock signal into first output clock signals with a high frequency, a second clock network configured to divide the clock signal into second output clock signals with a non-high frequency, a plurality of selection circuits configured to be connected between the first clock network and the second clock network, and configured to output one of the first output clock signals and the second output clock signals, according to a power mode, and a plurality of clock sinks configured to sink output clock signals respectively output from the selection circuits.

Abstract: One example of generating a clock signal via an oscillator system includes increasing a first comparison voltage at a first comparison node from a first magnitude to a second magnitude in response to a clock signal. A second comparison voltage is increased at a second comparison node from the first magnitude to the second magnitude in response to the clock signal. The clock signal changes state in response to the second comparison voltage increasing to a magnitude that is greater than the first comparison voltage. The first comparison voltage decreases from the second magnitude to the first magnitude in response to the clock signal. The second comparison voltage decreases from the second magnitude to the first magnitude in response to the clock signal. The clock signal changes state in response to the second comparison voltage decreasing to a magnitude that is less than the first comparison voltage.

Abstract: Inventive aspects include an integrated clock gater (ICG) circuit having clocked complimentary voltage switched logic (CICG) that delivers high performance while maintaining low power consumption characteristics. The CICG circuit provides a small enable setup time and a small clock-to-enabled-clock delay. A significant reduction in clock power consumption is achieved in both enabled and disabled modes, but particularly in the disabled mode. Complimentary latches work in tandem to latch different voltage levels at different nodes depending on the voltage level of the received clock signal and whether or not an enable signal is asserted. An inverter takes the voltage level from one of the nodes, inverts it, and outputs a gated clock signal. The gated clock signal may be active or quiescent depending on the various voltage levels. Time is “borrowed” from an evaluation window and added to a setup time to provide greater tolerances for receiving the enable signal.

Abstract: Embodiments of the invention provide a method and a circuit for generating a reference signal for controlling a peak current of a converter switch. According to at least one embodiment, the circuit includes a squarer configured to squire an input voltage signal divided from a primary-side supply voltage of an isolated converter, and a duty ratio calculator configured to calculate a duty ratio of energy transfer to a secondary side. The circuit further includes an operator configured to generate and output a reference signal for controlling the peak current of the converter switch from a square signal of the input voltage signal using the duty ratio of energy transfer calculated by the duty ratio calculator.

Abstract: This invention is a means to definitively establish the occurrence of various clock edges used in a design, balancing clock edges at various locations within an integrated circuit. Clocks entering from outside sources can be a source of on-chip-variations (OCV) resulting in unacceptable clock edge skewing. The present invention arranges placement of the various clock dividers on the chip at remote locations where these clocks are used. This minimizes the uncertainty of the edge occurrence.

Abstract: A pulse latch includes a pulse generator and a latch circuit. The pulse generator generates first and second pulse signals. The first pulse signal is generated when a test enable signal is in a first state, and the second pulse signal is generated when the test enable signal is in a second state. The latch circuit outputs the latched signal by selectively latching a normal data input signal or a test data input signal. The latch circuit includes first and second tri-state elements. The first tri-state element is controlled by the first pulse signal to enable the test data input signal to be latched when the test enable signal is in the first state. The second tri-state element is controlled by the second pulse signal to enable the normal data input signal to be latched when the test enable signal is in the second state.

Abstract: A sampling clock generator circuit includes a reference clock generator, a sampling hold circuit, a sampling clock generator to delay an output clock signal from the reference clock generator by a predetermined delay amount to generate and supply a sampling clock signal to the sampling hold circuit, a phase determining element to compare phases of a drive clock signal for an image reading unit and the sampling clock signal to output a result of the phase comparison, the drive clock signal generated according to the output clock signal of the reference clock generator, and a controller to adjust the delay amount of the sampling clock generator on the basis of the result of the phase comparison so that a phase difference between the drive clock signal and the sampling clock signal becomes zero.

Abstract: A pulsed latching apparatus and a method for generating a pulse signal are provided. The pulsed latching apparatus consists of a pulsed latch and a pulse signal generator. A data input terminal of the pulsed latch receives input data, the pulsed latch latches the input data according to a pulse signal, and transmits the latched input data through the data output terminal to serve as output data. The pulse signal generator duplicates a data transmission delay between the data input terminal and the data output terminal of the pulsed latch to obtain a duplicated delay. The pulse signal generator receives a clock signal, and processes the clock signal according to the duplicated delay to generate the pulse signal.

Abstract: The duty cycle corrector for correcting a system clock signal comprises a duty cycle detector and a duty cycle adjuster. The duty cycle detector is configured for detecting a system duty cycle of the system clock signal and generating the first control signal and the second control signal, wherein the first control signal and the second control signal are complementary to each other. The duty cycle adjuster comprises an inverter and the duty cycle adjuster is configured for delaying a change in an input status of the inverter and adjusting of the inverter in accordance with the first control signal and the second control signal.

Abstract: A system including a plurality of amplifiers configured to generate a clock signal having a frequency. The clock signal is input to a processor. The amplifiers are connected in series. An output of a last one of the amplifiers is fed back to an input of a first one of the amplifiers. Each of the amplifiers has a transconductance. A frequency adjustment module is configured to adjust, based on an activity level of the processor, the frequency of the clock signal by adjusting the transconductance of the amplifiers.

Abstract: An IC is disclosed which includes multiple sectors, each having a resonant clock distribution structure and a sector clock buffer. The sector clock buffer can drive a clock signal onto the resonant clock distribution structure, in response to received clock signal and control signals. The sector clock buffer includes a first driver circuit, with a first impedance to drive the clock signal during a first portion of first and second clock phases. The first driver circuit may cause oscillation of the resonant clock distribution structure. The sector clock buffer includes a second driver circuit, having a second impedance higher than the first impedance. The second driver circuit may maintain the clock signal during a second portion of the first and second clock phases, in response to the control signal. The second driver circuit may maintain the resonant clock distribution structure at one of two voltages.

Abstract: A memory storage device, a memory control circuit unit, and a clock adjusting circuit disposed on a plurality of layers are provided. The clock adjusting circuit includes a detection circuit, a control voltage generating circuit, and a voltage-controlled oscillator (VCO). The detection circuit detects a signal characteristic difference between an input signal and an output signal to generate a first signal. The control voltage generating circuit is coupled to the detection circuit and generates a control voltage according to the first signal. The VCO is coupled to the control voltage generating circuit and includes an inductor and a capacitor. The VCO receives the control voltage and starts oscillating according to an impedance characteristic of the inductor and the capacitor to generate the output signal. The inductor is disposed on a pad layer among the layers. Thereby, the manufacturing cost is reduced.

Abstract: A integrated circuit includes a clock control signal generation circuit configured to generate a clock control signal using transition of a control signal, a clock control unit configured to activate a control clock in an activated period of the clock control signal, and to deactivate the control clock in a deactivated period of the clock control signal, and a control circuit configured to operate in response to the control signal and in synchronization with the control clock.

Abstract: A method and apparatus for atomic frequency and voltage changes in the processor. In one embodiment of the invention, the atomic frequency and voltage changes in the processor is feasible due to the enabling technology of fully integrated voltage regulators (FIVR) that are integrated in the processor. FIVR allows independent configuration of each core in the processor and the configuration includes, but is not limited to, voltage setting, frequency setting, clock setting and other parameters that affects the power consumption of each core.

Abstract: There are provided a pulse generator capable of securing a maximum transfer rate of an IR-UWB signal, while maintaining low power consumption characteristics of an all-digital scheme, and a method for generating a fine pulse. A bandwidth of a fine pulse is determined by adjusting a difference in delay time between two adjacent pulses and a pulse is generated by selecting only one of a rising edge and a falling edge of an input pulse, and thus there is no need to remove an unnecessary batch of pulses afterwards and a transfer rate is enhanced.

Abstract: Chip instrumentation determines, in-situ, an allowable increase over product specification in the operating frequency of at least one clock domain in an integrated circuit for a given set of environmental, power supply and/or functionality constraints. Information on the allowable increase in operating frequency for the at least one clock domain is provided to circuits and/or software to effect change in operating frequency.

Abstract: Various circuits and methods of operating circuits are disclosed. A circuit may include a pulse generator and a latch having an output configured to trigger the pulse generator, wherein the latch is configured to be set by an input signal and reset by feedback from the pulse generator. A method may include resetting a latch using feedback from a pulse generator by setting a latch using an input signal, triggering a pulse generator using an output from the latch, and resetting the latch using feedback from the pulse generator.

Abstract: Embodiments provide, among other things, a circuit including a frequency generator and a charge pump. In embodiments, the frequency generator may be configured to provide the charge pump with a clock signal at a first frequency for a predefined period of time. Thereafter, the frequency generator may provide the charge pump with a clock signal at one or more other frequencies. In embodiments, the first frequency may enable the charge pump to settle in a reduced period of time when compared with the one or more other frequencies.

Abstract: Embodiments of a device and circuit implementing a digitally controlled oscillator with reduced analog components. In an example, the digitally controlled oscillator can include a phase accumulator controlled by a stall circuit to selective stall the phase accumulator. In some examples, the digitally controlled oscillator can include a phase select circuit to select multiple phases of a phase select circuit based on the output of the phase accumulator. In some examples, these selected phases can then be used by a phase interpolator to generate a synthetic clock signal.

Abstract: A clock generator circuit for producing a clock output having a controlled duty cycle is disclosed. A bi-stable circuit provides the clock output which is switchable to a first state in response to an edge of the input clock signal and to a second state in response to a feedback signal. A duty cycle detection circuit is configured to source a current to a node and to sink a current from the node depending upon the output clock state. A capacitor is connected to receive a duty cycle current relating to the current at the node, with a comparator circuit being configured to sense a voltage on the capacitor and to produce the feedback signal when the voltage is at a selected level.

Abstract: A clock synchronization system and method avoids output clock jitter at high frequencies and also achieves a smooth phase transition at the boundary of the coarse and fine delays. The system may use a single coarse delay line configured to generate two intermediate clocks from the input reference clock and having a fixed phase difference therebetween. The coarse delay line may have a hierarchical or a non-hierarchical structure. A phase mixer receives these two intermediate clocks and generates the final output clock having a phase between the phases of the intermediate clocks. The coarse shifting in the delay line at high clock frequencies does not affect the phase relationship between the intermediate clocks fed into the phase mixer. The output clock from the phase mixer is time synchronized with the input reference clock and does not exhibit any jitter or noise even at high clock frequency inputs. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract: The disclosed invention provides a semiconductor device capable of suitably controlling the level of an enable signal to resolve NBTI in a PMOS transistor. An input node receives an input signal alternating between high and low levels during normal operation and fixed to a high level during standby. A detection unit receives a signal through the input node and outputs an enable signal. The detection unit sets the enable signal to a low level upon detecting that the input node remains at a high level for a predetermined period. A signal transmission unit includes a P-channel MOS transistor and transmits a signal input to the input node according to control by the enable signal.

Abstract: A circuit adapted to generate a high speed shaped pulse comprising an input adapted to receive a data signal and a control signal. A plurality of logic elements are configures to receive the data signal and the control signal and generate a plurality of output signals representative of the shaped pulse. A digital to analog converter is adapted to receive the plurality of output signals and generate a shaped pulse.

Abstract: Operating capacitive sensors in force feedback mode has many benefits, such as improved bandwidth, and lower sensitivity to process and temperature variation. To overcome, the non-linearity of the voltage-to-force relation in capacitive feedback, a two-level feedback signal is often used. Therefore, a single-bit ?-? modulator represents a practical way to implement capacitive sensors interface circuits. However, high-Q parasitic modes that exist in high-Q sensors (operating in vacuum) cause a stability problem for the ?-? loop, and hence, limit the applicability of ?-? technique to such sensors. A solution is provided that allows stabilizing the ?-? loop, in the presence of high-Q parasitic modes. The solution is applicable to low or high order ?-? based interfaces for capacitive sensors.

Abstract: An adaptive clock generating apparatus is provided. The apparatus includes a fixed frequency divider, a replica, a counter, a variable frequency divider. The adaptive clock generating apparatus generates a clock whose period varies along with changes in the critical path delay of a synchronous circuit.