Abstract: Briefly, in accordance with one embodiment of the invention, a device for use in a magnetic recording read channel adapted to be coupled to a magneto-resistive (MR) read head comprises: an integrated circuit adapted so as to introduce a controllable amount of second-order nonlinearity into the magnetic recording read channel signal path to at least partially offset nonlinearity associated with use of the MR read head. Briefly, in accordance with another embodiment of the invention, a method of reducing nonlinear signal effects in a magnetic recording read channel signal path associated with use of a magneto-resistive (MR) read head comprises the step of: introducing into the read channel signal path a scalable square of the read channel signal.

Abstract: An electrical circuit for generating a polynomial function in response to a linear input signal is disclosed. The circuit in one embodiment comprises a primary and a secondary current mirror, with the collector or source of the secondary current mirror connected in common with the input signal of the primary current mirror. The output signal of the electrical circuit is taken at the mirrored current source terminal of the first current mirror. The primary and secondary current mirrors are biased to at least initially respond exponentially to the linear input signal. Each then transitions into the more linear, resistor-dominated range. The primary current mirror is enabled at a predetermined cut-in level, such that an upward curving exponential response function is generated in response thereto.

Abstract: A programmable gain amplifier which can be realized using CMOS transistors. The amplifier provides a plurality of linear gain segments, with each of the gain segments having a different gain. A particular combination of the gain segments are selected using a digital control input to give an approximation of a linear dB output. By appropriately choosing the segments and how they combine, an approximation that is accurate to the least significant bit of a digital system can be provided.

Abstract: A circuit arrangement for forming the square root of an input signal in at least one quadrant. The input signal is fed to the input of a first differential amplifier, the current outputs of which work on two diodes. The two outputs of the first differential amplifier are also connected to the inputs of a second differential amplifier, from one output of which there is a feedback via a diode to one of the outputs of the first differential amplifier. The collectors of the second differential amplifier work on current sources.

Abstract: A gain control circuit provides linear-in-decibel gain control for an RF signal variable gain amplifier. The gain control circuit utilizes the transconductance characteristics of bipolar transistors to generate a logarithmic relationship between a gain control current and an amplifier bias current. The gain control circuit comprises essentially a current mirror having two transistors with a resistor coupled between the associated base terminals of the two transistors. A third transistor and a resistor are also provided to absorb the gain control current. The gain control current is applied to the base of a first one of the two transistors and a voltage is thereby established across the resistor. This voltage subtracts from the base-to-emitter voltage of the second transistor thereby producing a corresponding exponential reduction in the current through the second transistor. This current is provided to a gm stage, whose gain is linearly proportional to this current.

Abstract: Exponential and pseudo-exponential decay function values are generated by scaling a fractional decrease per sampling period by a previous decay function value and then subtracting the scaled fractional decrease from the previous decay function value. In one embodiment, a multiplier multiplies the fractional decrease by the previous decay function value and provides a product signal representing the scaled fractional decrease. An adder subtracts the scaled fractional decrease from the previous decay function value. In another embodiment, a shift block replaces the multiplier and approximates multiplication by a binary shift of the fractional decrease. The size of the shift is determined by the previous magnitude of the decay function as indicated by a priority encoder. Shifting generates a pseudo-exponential decay function which is suitable for music synthesis and can be generated quickly using less expensive hardware.

Abstract: A non-linear circuit having a transfer characteristic which is adjustable per amplitude segment of an input signal (Yi) includes a segmenting circuit (11 . . . 15, 21 . . . 25) for obtaining a plurality of amplitude segment signals (Y1 . . . Y5) from the input signal (Yi), and a non-linear segment amplifier circuit (31 . . . 35) coupled to the segmenting circuit (11 . . . 15, 21 . . . 25) for separately multiplying segments (Y1 . . . Y5) of the input signal (Yi) by respective segment gain factors (HM1 . . . HM5) in dependence upon a common gain factor (HMa) derived from the segment gain factors (HM1 . . . HM5) and on the basis of the amplitude segment signals (Y1 . . . Y5) for supplying a signal (Y"s) which is adjustable per amplitude segment of the input signal (Yi). The non-linear circuit may also include an output circuit (37, 39) coupled to the non-linear segment amplifier circuit (31 . . .

Abstract: An anti-logarithmic type converter circuit, with temperature compensation, includes a diode connected between a unity gain, non-inverting interface circuit and a low-impedance reference voltage circuit. A thermal compensation circuit is connected between the converter input and the interface circuit. The thermal compensation circuit includes current mirror circuits having a gain higher than one and their output currents linearly dependent on temperature.

Abstract: A differential amplifier provides a predetermined gain characteristic over a large range differential input voltage signals and operating temperatures. The differential amplifier receives a first differential input voltage signal at a pair of amplifier input terminals and outputs a differential output current signal at a pair of amplifier output terminals. First and second emitter-coupled transistors are connected to receive at their bases an amplifier core differential voltage signal, have their emitters coupled to receive first and second constant currents and coupled together by a load element. The first and second emitter follower transistors have their bases coupled to the amplifier input terminals to receive the first differential input voltage signal from the pair of amplifier input terminals.

Abstract: A voltage to current converter which exhibits a well-defined substantially exponential voltage-current characteristic. First and second input bipolar transistors of the voltage to current converter each have an emitter, a base, and a collector. The first and second input bipolar transistors are coupled at their emitters, and may be biased with a pre-determined constant current source, and they accept a selectable differential input voltage at their bases. A reference current source is connected to the collector of the first input bipolar transistor, and all output current source is connected to the collector of the second input bipolar transistor. A feedback element, having a gain, is connected between the coupled emitters and the collector of the first input bipolar transistor. The feedback element senses a voltage at the collector of the first input bipolar transistor and regulates a voltage at the coupled emitters to maintain a constant current through said first input bipolar transistor.

Abstract: A source of equally spaced timing signals which includes a first signal source providing a first signal tracing an essentially exponential voltage curve, a second signal source including a transistor having a control electrode and an electron flow path therethrough having a voltage drop V.sub.BE thereacross, a voltage source providing a voltage V.sub.CC coupled to one end of the electron flow path, a resistance R.sub.L coupled between the control electrode and the voltage source, the other end of the flow path providing a second voltage signal in accordance with the equation V.sub.i =V.sub.H -I.sub.i R.sub.L for i=1 to n where I.sub.i =(V.sub.H /R.sub.L)(1-e.sup.-i.alpha.) and V.sub.H =V.sub.CC -V.sub.BE and a comparator providing a timing signal whenever the second voltage signal is greater than the first signal.

Abstract: A circuit (12) for controlling the gain of a gain cell (14) is provided. Circuit (12) comprises a circuit (16) for generating a control current. A circuit (22) generates a reference voltage. A circuit (18) uses the reference voltage to generate a first control voltage. A circuit (20) uses the control current to generate a second control voltage. The first and second control voltages comprise a differential control output of circuit (12). The gain of the gain cell is exponentially related to the control current.

Abstract: A charge pump circuit comprises a plurality of voltage doubler circuits connected together such that a first voltage output generated by a first portion of a kth one of the voltage doubler circuits is substantially equal to Vdd*2.sup.k and Vdd*2.sup.k-1) on odd and even phases, respectively, of a first clock signal, and a second voltage output generated by a second portion of the kth one of the voltage doubler circuits is substantially equal to Vdd*2.sup.k-1) and Vdd*2.sup.k on the odd and even phases, respectively, of the first clock signal. Each of the voltage doubler circuits is constructed such that when its first portion is providing a voltage of Vdd*2.sup.k and a current to a next stage, its second portion is recharging a capacitor in that portion to Vdd*2.sup.k-1), and when its second portion is providing a voltage of Vdd*2.sup.2 and a current to the next stage, its first portion is recharging a capacitor in that portion to Vdd*2.sup.k-1).

Abstract: The circuit is adapted for integration of pulse signals of the shape U(t)=U.sub.0 exp(-t/.tau.), wherein the time constant .tau. can be determined in advance by a calibration measurement, in particular signals from a scintillation detector. The purpose is to treat pile-up phenomena, without measuring the integration time, wherein the measured integral is corrupted because the time distance between two pulses becomes smaller than the integration time for the first pulse. The circuit comprises an integrator (4, 5, 6, R, C) for the pulse signal and a summator (3, R.sub.1 -R.sub.3) for forming a weighted sum of the pulse signal (on 1, 2) and the integrated signal (from 4, 5), the weight of the pulse signal and the weight of the integrated signal having such a relation to each other that the result signal (on 8) is proportional to the sum of the time integral of the pulse signal and .tau. times the pulse signal.

Abstract: Gamma correction is performed by dividing the total gamma transfer function input value range into a plurality of segments. The source RGB data is then mapped into an associated x-position in a "standard" segment, and gamma correction is performed on the mapped value as if it was initially in that standard segment. The resulting corrected value is then de-mapped back into the original input value segment. Only the portion of the gamma correction curve which is within the "standard" segment is processable by the circuitry. The segments into which the input value range is divided may occupy ratiometrically increasing portions of the input value range, with the high-order half of the range designated as the standard segment. The lowest-order portion may be approximated linearly. Mapping into the standard segment then involves shifting the input value to the left until the highest order logic 1 is in the highest order bit position.

Abstract: An exponential circuit according to the present invention converts voltage level to time by using a charged voltage of RC circuit RC.sub.1, registers time as a clock number at a digital counter and performs bit shift for the registered data.

Abstract: A circuit for providing an output current proportional to a first voltage raised to a fractional exponential power divided by a second voltage raised to a fractional exponential power, is supplied. The circuit has four strings of series connected pn junctions. The first and second voltages are connected to the first and fourth string, respectively. A reference current is provided to the second string, while the third string provides the output current. The number of pn junctions are chosen to give the desired fractional exponents of the two voltages while the number of pn junctions in the third string is selected to adjust for the number of pn junctions in the other strings.