Abstract: A delay line and clock multiplying circuit are disclosed. A plurality of phase shifters impart on a reference clock successively increasing phase shifters, wherein the phase shifters have a plurality of outputs for the successively phase shifted signals. A plurality of first AND gates combine the phase shifted signals in groups to obtain a number of pulses. The pulses are then combined in a plurality of OR gates to obtain a number of pulse signals. A clock signal generator generates, from the pulse signals, mutually time delayed clock signals. A controller is arranged to control the time delay of a delay line circuit. The controller receives at least two mutually phase shifted signals from the outputs of the phase shifters and determines a delay error. The controller then generates a control signal for the delay line circuit, the magnitude of which depends upon the delay error.

Abstract: A computational circuit which has a capacitive coupling for weighted addition. Addition is performed by the capacitive coupling. By connecting and disconnecting capacitances of the capacitive coupling, multiplication can be executed by changing the weights of the capacitors. An inverter with a feed back capacitance is connected to a computational circuit to improve the accuracy of the computation.Capacitances consist of unit capacitances of scattered distribution, so that the deviation of the capacities is minimized.

Abstract: A programmable analog array (10) comprises an array (11) of cells, each cell including analog circuitry (12), a switch control circuit (18), and a digital storage element (16). The switch control circuit (18) receives a clock signal and sequentially configures the circuits within the analog circuitry (12) to realize different circuit functions in accordance with configuration data stored in different digital memory units (17A-17D) within digital storage element (16). During a time interval, the analog signals generated by the analog circuitry (12) before that time interval are stored in an analog storage element (14), which is constructed from a portion of a capacitor network (54) in the analog circuitry (12) and is partitioned into a set of analog memory units (56A-56D). Each analog memory unit (56A-56D) stores the analog signal for a corresponding phase of the clock signal.

Abstract: An impedance multiplier circuit comprises an input impedance having a certain value of impedance and a circuit coupled to this input impedance for multiplying its value by a multiplication factor. This multiplying circuit comprises a first and a second voltage follower amplifier and a first and a second scaling impedance. The input impedance is coupled between the input of the first voltage follower amplifier and the output of the second voltage follower amplifier with the first and second scaling impedances establishing a voltage division between the output of the first voltage follower amplifier and the input of the second voltage follower amplifier. In this way, the second voltage follower amplifier provides active negative feedback, and effectively multiplies the input impedances's impedance by a factor of one plus the quotient of the second scaling impedance to the first scaling impedance.

Abstract: Current mirror circuits and methods, and an amplifier using same, are provided in which the output of the current mirror is reduced to zero when the input current falls below a predetermined threshold. An offset current is subtracted from the input (or reference) current at input currents below the threshold. Otherwise, the offset current source is turned off. Thus, the output current can be reduced to zero, even if there is a small input current, without distorting the input-output relationship over the majority of the range of operation of the current mirror. An amplifier with two current-feedback complementary input stages (or fader circuit) is also provided which includes a gain control circuit that uses the current mirror circuits of the present invention to ensure that each input can be fully attenuated.

Abstract: A frequency conversion circuit having at least one transistor with an input terminal and an output terminal. A frequency signal to be converted or a local oscillator (LO) signal is input to the input terminal, and a converted frequency signal is output from the output terminal. A linear feedback circuit allowing at least a radio frequency (RF) signal and the LO signal to feed back is directly connected across the input and output terminals.

Abstract: An analog circuit for multiplying a first input signal with a second input signal. The inventive analog circuit is capable of linear operation with a low voltage power source. A first pair of transistors is coupled as a first differential pair, and a second pair of transistors is coupled as a second differential pair. The first differential pair is coupled to the second differential pair in a manner that is similar to the corrections made between a first and second differential pair of a conventional Gilbert mixer. However, the emitter degeneration resistors of the present invention are not coupled to the collectors of a third differential pair, as is the case in conventional Gilbert mixers. Rather, the degeneration resistors of the present invention are coupled directly to the negative power supply terminal.

Abstract: A computational circuit that includes a selector for providing an input to one of a plurality of sample/hold circuits. The outputs of the sample/hold circuits are provided to a multiplexer. The output of the multiplexer is provided to a computational portion, such as a multiplier.

Abstract: A computational circuit that includes a pair of operational amplifiers, wherein one of the amplifiers receives an analog input voltage. Switching circuits are provided to selectively connect the outputs of the operational amplifiers to a common node and to respective inputs thereof via feedback lines. Capacitors are provided at the common node. A digital signal actuates the switching circuits so that one switching circuit is opened when the other is closed.

Abstract: An estimating circuit for application in estimating or deriving the value V.sub.rms.sup.2 or V.sub.peak.sup.2, of a line voltage V.sub.AC provides fast response time and a substantially ripple free value for these signals by the utilization of a controlled harmonic oscillator whose output precisely tracks the input voltage waveform. Two out of phase (by .pi./2) sine wave signals are derived from the input sine wave and these two out of phase signals are squared and summed to derive or estimate the desired square of the sine waveform signal at a fast response time while substantially excluding ripple of the estimated out of phase sine waves. An estimating circuit, described herein, comprises two integrator circuits series connected into a substantially closed loop. The output of the second integrator circuit is fed back to the input of the first integrator circuit. The output of each individual integrator circuit is a voltage sine wave separated in phase from the output of the other integrator by .pi.