Abstract: A circuit configuration for triggering a field effect transistor with a source-side load has a capacitor which is connected on one hand through a load path of the field effect transistor to a supply voltage and on the other hand both to a first charging device and to a first controllable switching device. The first switching device is connected between the capacitor and a gate terminal of the field effect transistor. A second charging device acts through a second controllable switching device to charge a gate-to-source capacitor of the field effect transistor. A comparator monitors a voltage at the gate terminal of the field effect transistor and makes the first switching device conducting when a predetermined value is reached.

Abstract: A driver circuit for driving multiple lines with unknown loads uses a high slew rate driver to drive the output during input signal transitions, and uses a termination driver to drive the output during input signal steady state conditions. The high slew rate driver provides rapid transitions, and the terminating driver provides ideal output impedance to maintain the fidelity of the output signal.

Abstract: A driver circuit for regulating the current flowing through the coils of a rotary field microwave phase shifter. The circuit includes logic circuitry functions which implements an algorithm to provide decision making capability to avoid failure-inducing conditions, reducing power consumption, and enhancing testability of the circuit. The circuit includes two switches that respectively drive either a positive or a negative voltage to the load, to begin steering the load current to the appropriate direction. The logic circuitry includes a current mode mapping function to determine whether a commanded current value requires positive, negative or no voltage applied to the load. The logic circuitry further includes a finite state machine to control the two switches, to ensure that both switches are never commanded to be conductive at the same time, and to permit toggling of only one of the switches to regulate the current to a target value in a feedback loop.

Abstract: An N-channel power MOSFET includes a storage capacitor and a pair of diodes connected between the gate and drain terminals, respectively, and the capacitor. Since at any given time the voltage at either the drain or the gate of the MOSFET is high, a charge is maintained on the storage capacitor as the MOSFET is switched on and off. The charge stored on the capacitor yields an output voltage which may be used to power a gate drive circuit or other components within or outside the MOSFET.

Abstract: In a method and apparatus for shifting the level of a signal a shifter receives a multi-logic state input signal and generates a multi-logic state output signal responsive to changes in logic state of input signal and whose voltage level is shifted with respect to the input signal. The logic low state of the output signal is shifted to a certain voltage level above ground. A first switching device sets the voltage level of the logic low state. A feedback circuit feeds a signal derived from the output signal back to the switching device to precondition the shifter so that the speed of the output signal transition from one state to another is accelerated.

Abstract: A low power, low voltage level shifter is provided. The voltage level shifter includes a first switching circuit, and a second switching circuit. The first switching circuit has a first input terminal for receiving a first oscillating signal, and based on the first oscillating signal, switches the output of the first switching circuit between a first voltage level and a second voltage level. The second switching circuit has a second input terminal connected to the output terminal of the first switching circuit. The second switching circuit also has a third input terminal for receiving a second oscillating signal which is out of phase with the first oscillating signal. Based on the input signals received, the second switching circuit generates an output signal that switches between a third voltage level and a fourth voltage level at a selected rate and frequency.

Abstract: A variable delay circuit capable of changing delay time includes a latch circuit constituted of a pair of inverters cross-coupled to each other and a transistor serving for reducing voltage difference between two inputs of the latch circuit based on a control signal given thereto. The control signal is also supplied to a pair of transfer gates to control the delay time of the variable delay circuit. The latch circuit has two inputs, between which the transistor is coupled, coupled to the respective transfer gates' ends, at which buffers are respectively coupled to feed output signals. When the control signal reaches a high level, the state of the transistor becomes one of low impedance, so that the voltage difference between the two inputs of the latch circuit is reduced, and so that the state of the latch circuit can be quickly and easily changed with little energy.

Abstract: The present invention provides a driver circuitry having a single input terminal for receiving an input signal of binary digits consisting of high and low levels, and at least first and second output terminals, wherein the input signal is varied almost linearly in a first time period so as to be shifted between high and low levels, the driver circuitry comprises first and second control circuits. The first control circuit is coupled to the input terminal for receiving the input signal. The first control circuit is also coupled to the first output terminal for outputting a first output signal of binary digits via the first output terminal. The first control circuit is biased between a high voltage line which supplies a high level of voltage and a low voltage line which supplies a low level of voltage.

Abstract: A driver circuit for high frequency transistor type switches, comprising two sections; a positive (+) drive and a negative (-) drive, both sections being supplied with a high frequency signal by a square wave oscillator source. The sections are connected in parallel to a control generated input drive signal. In the negative drive section, the input drive signal is first inverted before being processed. Each section contains precise circuits for routing a high frequency carrier signal, for increasing input drive signal power gain, for providing independent positive and negative slope control, for providing exceptionally high voltage and noise isolation to avoid transmission of harmful voltages or noise, and for delivering a positive or negative drive signal to the gate/emitter of an external transistor under drive. The invention is characterized by its high voltage and noise isolation, using few components and being small in size.

Abstract: A drive circuit for a high-speed integrated circuit, bipolar switching regulator is disclosed. The circuit runs at megahertz frequencies, yet is efficient as previously available bipolar integrated circuit switching regulators operating at much lower frequencies. The circuitry provides three switch drive currents: a first (nominal) current that is provided while the switch is off in order to conserve power; a second (boosted) current, provided while the switch is transitioning from off to on in order to increase the speed at which the switching element switches on; and a third (drive) current, provided after the switch has turned on for maintaining the switch at a desired point in saturation. The drive current, additionally, varies as a function of the load on the switch in order, again, to conserve power. Additional circuitry increases the speed at which the switch turns off, by momentarily boosting base discharge current during the on-to-off transition period of the switch.

Abstract: A gate drive circuit for a power transistor provides improved dielectric isolation and protection against inadvertent turn ON of the power transistor. The gate drive circuit includes a first circuit means for providing a bias power signal and a trigger pulse signal to a second circuit means in response to a control signal from an external control circuit connected to said first circuit means. The bias power signal and the trigger pulse signal are coupled from the first circuit means to the second circuit means by magnetic induction through a first and a second coupling transformer, respectively, with the first and second coupling transformers thereby providing separate pathways for coupling of the bias power signal and the trigger pulse signal between the first and second circuit means. The first and second coupling transformers further provide dielectric isolation between the first and second circuit means along each of the separate pathways.

Abstract: A substrate voltage control circuit is used to apply bias voltage to a substrate or a well of a semiconductor memory such as a flash memory. The substrate voltage control circuits do not use any depletion type transistors. Therefore, the area occupied by the transistors for the circuit is small.

Abstract: A high performance isolated gate drive circuit for driving MOSFET is disclosed which uses a MOSFET pull-down device, provides unusually low gate discharge impedance, exceptionally fast turn-off of the controlled switch and reduced power dissipation in the overall gate drive circuit. It also provides superior off-time noise immunity.

Abstract: Driving circuits (6) output driving signals to drive switching transistors (Q 15, Q16). A potential as the high level of the driving signal can be set lower than a power supply voltage (V.sub.DD) by connecting the sources of transistors (Q18, Q20) to a node (X). This configuration prevents an overshoot at a switching time and allows an improvement in a settling time. Therefore, a complementary current source circuit for a high-speed D/A converter can be provided.

Abstract: A transition control circuit (2) for controlling the transitions of an output signal, at an output node (8) of a driver circuit, in dependence on the logic state of an input signal at an input node (10). The output signal being switchable between a first logic state and a second logic state. The transition control circuit (2) comprises first means (16) and second means (14). The first means (16) is enabled when the output signal has the first logic state and the input signal has the second logic state, and is disabled when the output signal has the second logic state or the input signal has the first logic state. Once enabled, the first means (16) couples the output node (8) to a first supply line (GNDA) whereby the output signal switches to the second logic state. The second means (14) is enabled when the output signal has the second logic state and the input signal has the second logic state, and is disabled when the output signal has the first logic state or the input signal has the first logic state.

Abstract: A differential comparator that amplifies small swing signals to full swing signals. The differential comparator comprises a current switch having a pair of inputs coupled to receive a pair of small swing complementary input signals and a pair of complementary outputs that output complementary signals. The complementary signals output by the current switch have a voltage swing that centers about a predetermined voltage in response to the complementary input signals. The differential comparator further comprises first and second inverters coupled to receive the output complementary signals, wherein each inverter has a trip point voltage equal to the predetermined voltage. The first and second inverters output full swing complementary output signals in response to the complementary signals output by the current switch.

Abstract: A pullup circuit having a limited voltage swing and fast pullup and pulldown times comprises a pullup structure, a pulldown structure and an internal node. The pullup circuit operates to limit the current of the pullup structure before the N-tree discharges the internal node, thereby reducing the pullup effect of the pullup structure to reduce fall time and power consumption. Then the pullup circuit maximizes the current of the pullup structure after the N-tree has pulled down the internal node to increase the pullup effect of the pullup structure to reduce rise time. As a result, the voltage of the internal node both charges more quickly when the N-tree becomes inactive and discharges more quickly when the N-tree becomes active.

Abstract: There is disclosed an input circuit for a semiconductor integrated circuit device wherein a level shift circuit (LS1) adds a constant voltage to an input signal from an input signal terminal (3) and a reference voltage from a reference voltage terminal (4) to output signals, which are in turn amplified by means of a plurality of cascaded, first and second differential amplifier circuits (Dif1, Dif2), and then a difference between the amplified input signal and the amplified reference voltage is applied to a CMOS inverter circuit (In1), which in turn outputs a power supply potential (V.sub.DD) or a ground potential (V.sub.SS) in accordance with the difference, thereby achieving a high-speed operation in response to the binary input signal slightly varying in signal voltage and a normal operation independent of variation of the reference voltage. (FIG.

Abstract: A system and method for increasing clock edge transition speed and edge phase accuracy. A split clock buffer provides separate controls of a pull-up transistor and a pull-down transistor. The buffer is off (high impedance) between clock edge transitions. Clock edge transition speed is improved by avoiding the transient condition of a conventional clock buffer where both of the pull-up and pull-down transistors are both on during clock edge transition.

Abstract: In an output circuit, a signal /.phi. opposite in phase to a signal /EN inputted through an input terminal 3 is generated by an inverter 1, and a signal .phi. in phase with the signal /EN is generated by two inverters 8 and 2. When the input signal /EN changes from a high level to a low level, a bipolar NPN transistor 35 is turned on instantaneously to decide an output terminal 5 at the low level forcedly. On the other hand, when the signal /EN changes from the low level to the high level, an NPN transistor 10 is turned on in advance of the other circuits to decide the output terminal 5 at the high level forcedly. Accordingly, it is possible to roughly equalize a delay time (from when the level of the input signal /EN changes at the input terminal 3 to when the level of the signal /.phi. changes at an output terminal 4) to another delay time (to when the level of the signal .phi. changes at the output terminal 5), thus realizing an ideal phase relationship between the two signals/.phi. and .phi.

Abstract: A high side switch having a MOSgated power device has a control circuit which contains a control MOSFET which is connected between the gate and source of the MOSgated power device. The input signal to turn the power device on and off is connected to a level translator circuit which is, in turn, connected to an inverter circuit which drives the gate of the control MOSFET. The control MOSFET then prevents the turn on of the power MOSFET during the turn-off process. A high negative clamp voltage causes a higher di/dt reduction of current during turn off to shorten the turn-off time. The power MOS device cannot be turned on whenever V.sub.CC is low and the output voltage is negative.

Abstract: A pulse generator using a buffer for receiving a differential signal and for generating an output signal in response thereto; a first differential amplifier for receiving the output signal from the buffer; and a pair of capacitors connected to the first differential amplifier and being caused to be charged by the buffer for selectively controlling the first differential amplifier; and means for receiving another differential signal from the first differential amplifier to produce a pulse, whereby a slew rate controller is used without requirement of complementary transistors to produce the pulse.

Abstract: A BIMOS driver circuit and method in which a push-pull pair of PNP-NPN bipolar transistors replaces the middle CMOS inverter stages in a circuit for driving a capacitive load. The rise and fall times of the circuit are made symmetrical by feeding back driver circuit output to operate a feedback transistor which removes the base charge stored in a PNP transistor of the bipolar push-pull pair, and maintains low propagation delay.

Abstract: The positive input terminal (1), the negative input terminal (2) and the differential amplifier (10) are connected to the voltage converting circuit (9a). The differential amplifier (10) is composed of the operational amplifier (6) and the resistors (5a, 5b, 5c and 5d). The voltage converting circuit (9a) includes NPN transistors (91, 92 and 93). The base of the transistor (91) is connected to the positive input terminal (1) and the base of the transistor (92) is connected to the reference potential input end (3) to which the reference potential (V.sub.x) is applied, respectively. The collectors of the transistors (91 and 92) are connected to the potential point (81) in common and the emitters are connected to the other end of the resistor (5a). The base of the transistor (93) is connected to the negative input terminal (2), the collector is connected to the potential point (81) and the emitter is connected to the other end of the resistor (5c).

Abstract: A variable slew control for output circuits is disclosed. The slew control circuit automatically adjusts the rate in which voltage on a slew node is driven to a reference voltage, minimizing noise at the output device driver. The variable slew control decreases the slew rate of the slew node during periods when di/dt is at a high level, but allows the voltage on the slew node to drop at faster rates during times when di/dt at the output driver is low.

Abstract: An output buffer circuit includes a pull-down side transistor connected between an output terminal and a low-potential power source. The pull-down side transistor is driven by an input signal, such that when the pull-down side transistor is turned on by the input signal, a low level output signal is output from the output terminal. A pull-up circuit is connected between the output terminal and a high-potential power source, for changing the output signal to a high level in accordance with the input signal when the transistor is turned off in response to the input signal. The pull-up circuit ceases to function when the output signal goes high thereby creating a high impedance condition. The pull-up circuit includes an OR gate which receives the input signal and the output signal, and an inverter which receives an output signal of the OR gate. A differentiating circuit is provided, through which an output signal of the inverter circuit is output to the output terminal.

Abstract: A BiCMOS digital delay chain includes two signal paths coupled between an input terminal and an output terminal. The first signal path has two CMOS inverters coupled in series, while the second path has one CMOS inverter coupled to an BiNMOS inverter, with the latter being coupled to a BiCMOS pull-down circuit. By providing two signal paths between the input and output terminals of the delayed chain, a zero-static-power low-voltage circuit is obtained in which power-supply sensitivity is higher in one switching direction than in the other. This feature permits operation over a wide range of power supply potentials while minimizing changes in integrated circuit performance.

Abstract: An output preconditioning circuit with an output level latch is provided to precondition the output to an intermediate level and to clamp the output to that level before the actual data from a memory cell arrives at the output. Since the actual data has to charge or discharge the output from some intermediate level rather than the maximum output swing level or the minimum output swing level, as in the normal case, this results in a reduced delay in charging or discharging the output. The output preconditioning circuit which may be coupled to a heavy load or a light load can eliminate oscillation of the output because of the output level latch.

Abstract: An output device and method of operating it are disclosed. The output device includes a output control unit and an output buffer unit. The output control unit produces a data release (INR) signal after producing an output release (OR) signal, for example, by delaying the OR signal. The INR signal causes release of an output signal from a sense amplifier, resulting in a data signal. The output buffer includes n- and p-channel switching transistors and control units controlling their gates. In response to activation of the OR signal, the control units bring the voltage of the gates of the switching transistors to respectively slightly above and slightly below the threshold levels of their gates. In response to the data signal, the control units fully activate one of the switching transistors and deactivate the other of the switching transistors depending on the voltage level of the data signal. The speed with which the control units respond to the data signal is controlled.

Abstract: A current buffer circuit comprises an input terminal, an output terminal, a first transistor of a first conductivity type having a base connected to the input terminal and an emitter, and a second transistor of a second conductivity type having a base connected to the input terminal and an emitter. The buffer circuit further includes a third transistor of the second conductivity type having a base connected to the emitter of the first transistor, a collector connected to a first power supply terminal, and an emitter connected to the output terminal, a fourth transistor of the first conductivity type having a base connected to the emitter of the second transistor, a collector connected to a second power supply terminal, and an emitter connected to the output terminal, and a fifth transistor of the second conductivity type having a base connected to the collector of said fourth transistor, a collector connected to said output terminal, and an emitter connected to the second power supply terminal.

Abstract: This application discloses circuit and method for reducing the turn-off time of a power transistor driving an inductive load. The circuit clamps the gate to source of a power transistor by using two field effect transistors as the current path across the gate and source of the power transistor. A zener diode connected from the source to gate of the two field effect transistors is used to provide high voltage protection.

Abstract: A high speed CMOS current switching circuit suitable for use in digital to analog converters for graphic interfaces having high pixel clock rates, and such interfaces as may be used in portable and other battery operated or low power consumption applications. In operation, the current switching circuit normally steers an idle current to ground. If the bit of the digital to analog converter input digital signal represented by the respective source is a 1, the input signal representing the bit is delayed slightly while the current steered to ground is increased from the idle value to the full desired output current, whereupon at the end of the delay, the device coupling the output current to ground is turned off, thereby forcing the output current through an output device. A low power current steering circuit which can perform dynamic current steering without affecting switching speed performance is also disclosed.

Abstract: A circuit arrangement for gate-controlling a MOS field-effect transistor (T.sub.o) comprises a discharge circuit (12) via which the charge stored in the gate-source capacitance (C.sub.GS) can be discharged according to a time constant, the value of which depends on the internal impedance of said discharge circuit (12). This discharge circuit (12) can be switched between two conditions determined by a relatively large and a relatively small internal impedance respectively and assumes the condition dictated by the relatively small internal impedance as soon as the gate-source voltage (U.sub.GS) has dropped below a predetermined limit.

Abstract: An output driver circuit for preventing the emission of high-frequency signals, including two MOS output transistors (M2, M1) which are connected in series between the supply voltage (Vcc) and ground, and two capacitors (C1, C2) which are arranged between the output node (N1) and the gate of a respective output transistor. The voltages on the gates of the output transistors are quickly increased to the conductivity threshold before a transition occurs on the output, whereby acceleration circuits supply the gates of the output transistors with high currents. During the transition of the output signal, the acceleration circuits are switched off and smaller currents are applied to the gates of the output transistors; the capacitances (C1, C2), being connected in phase opposition, prevent excessively fast variation of the voltage on the output node.

Abstract: The turn-off delay time of a low-side driver (output power transistor), may be independently reduced and eventually made identical to the turn-on delay time by employing an auxiliary current generator that may be controlled by the same switching signal that controls a current generator employed for discharging the control node of the low-side driver, in order to provide an augmented discharging current during a first phase (only) of a turn-off process. The contribution to the capacitance discharge current provided by said third current generator is automatically interrupted by means responsive to the voltage present on the driving node of the low-side driver, when it approaches saturation.

Abstract: The multiple-input OR-gate includes a set of pull down transistors connected in parallel to a common signal line. A pair of first and second inverters are connected along the common signal line between the input pull down transistors and an output. A feedback element connects an output of the second inverter to an input of the first inverter. The inverters are configured to maintain the input of the first inverter at a first intermediate voltage level of V.sub.cc -2 Vt. Input signals received by the input transistors cause the voltage on the signal line to be pulled from the first intermediate level toward Vss. The first inverter responds by generating an output signal which swings from a low voltage of V.sub.ss towards a second intermediate level of V.sub.cc -0.7 Vt. The second inverter responds by generating an output signal which swings between the high level of V.sub.cc and a low level of V.sub.ss.

Abstract: An output driver for use with low voltage level, high speed data transmission busses. An open drain output transistor has a controlled slew rate for a high to low output transition. The slew rate control is provided by controlling the slew rate of the gate voltage of the output transistor in response to an input transition. A slew rate control circuit coupled to the output transistor includes a current source powered by a high stability bias generator, a diode and a capacitance. The current source controls the amount of current available at the gate of the output transistor. The diode and the capacitance combined are used to control the initial voltage at the gate of the output transistor, and the slew rate for the rising voltage waveform at the gate of the output transistor. The resulting circuit has a fast transition time in response to an input transition combined with a tightly controlled slew rate.

Abstract: A switch circuit for a charge pump circuit is disclosed. The switch circuit has a first transistor for conducting current and is controlled by a second, third, and fourth transistor. The second transistor protects the first transistor for excessive gate-to-drain voltage. The third transistor receives the signal for switching the switch circuit and also serves as a cascoding transistor for protecting the fourth transistor from excessive gate-to-drain voltage. Consequently, the switch circuit can withstand high gate-to-drain voltages and has increased reliability. The switch also has a turn-off circuit to facilitate the depletion of charge on the control element of the first transistor. The switch circuit also has a zener diode to insure that excessive voltage is not applied across the gate-to drain of the first transistor.

Abstract: A track and hold circuit including an input terminal V.sub.IN, a first node, a second node and a capacitor C.sub.H. A diode D connects between the first node and the input terminal V.sub.H. Circuitry coupled to the first node makes the diode conductive during track mode of operation, indicated by a clock CK being at a first state, and non-conductive during hold mode of operation, indicated by a clock CK being at a second state. A transistor Q3 is coupled between said first node and said second node. The capacitor C.sub.H is connected to said second node. The transistor Q3 is operative to charge the capacitor C.sub.H during track mode and to isolate the capacitor C.sub.H from the input terminal V.sub.IN during hold mode. Additional circuitry coupled to said transistor Q3 senses the clock shifting from said first to said second state to rapidly discharge the inherent base/emitter capacitor of the transistor Q3 to thereby cause rapid turn off of the transistor Q3.

Abstract: A bi-mode circuit for driving an output load selectively couples the output load to a supply voltage source or to a low discharge voltage source such as ground using switches which are controlled by an input buffer in response to an input signal. A high input signal closes a first switch to provide a biasing current to first and second current amplifiers to turn on a first output transistor which couples the output load to the low reference voltage to discharge the output load. Conversely, a low input signal closes a second switch to provide the biasing current to a third current amplifier to turn on a second output transistor which couples the output load to the supply voltage source. When the input signal becomes high, rapid pulldown of a capacitive output load is achieved using a high internal pre-drive current provided by the first and second current amplifiers, in a first mode of operation.

Abstract: A data output buffer for a semiconductor memory device having a plurality of memory cells, each of the memory cells storing a data signal. The data output buffer comprises: an input line for inputting the data signal from each of the memory cells; a pull-up driver connected between a supply voltage source and an output line, the pull-up driver being driven in response to a first logic of the data signal from the input line; a pull-down driver connected between a ground voltage source and the output line, the pull-down driver being driven complementarily to the pull-up driver in response to a second logic of the data signal from the input line; at least one auxiliary pull-up driver connected in parallel to the pull-up driver; and a controller for driving the at least one auxiliary pull-up driver for a predetermined time period from a start portion of the first logic of the data signal from the input line.

Abstract: A CMOS pass gate receiver improves chip-to-chip communication speed for high speed chips. The high speed CMOS pass gate receiver is immune to overshoot or undershoot and can operate in a frequency greater than or equal to 400 Mhz.

Abstract: A semiconductor memory device which is capable of reducing a delay in the conversion of an input chip enable signal having a TTL level, providing a quick chip enable access and avoiding an increase in current consumption despite the quick chip enable access. The semiconductor memory device in one embodiment includes an input buffer outputting a signal having a CMOS level in response to a chip enable signal having a TTL level, and having a plurality of transistors whose gate lengths are set to first dimensions, and a second input buffer activated in response to both another input signal having a TTL level and the signal having the CMOS level, and having a plurality of transistors whose gate lengths are set to second dimensions greater than the first dimensions.

Abstract: A PNP bipolar transistor is connected to both ends of a resistive element of a Super Push-Pull Logic (SPL) circuit so as to place an emitter thereof at the side of a power supply source. Resistive elements and an NPN bipolar transistor forms a bias circuit for biasing a low voltage to a base of the PNP bipolar transistor. The base of the PNP bipolar transistor is connected to an emitter node of a NPN bipolar transistor through a capacitative load element. By this construction, the present invention can provide signal without any delay to turn on the PNP bipolar transistor. Therefore, the collector response speed of the SPL circuit can be increased.

Abstract: A bus line is divided into at least first and second bus segments that are coupled together via a precharge buffer, each segment seeing less effective RC than if segmentation were not present. The precharge buffer provides first and second output buffer lines (or segments) that are monitored and cross-coupled through the buffer such that each line is pulled-up or pulled-down substantially simultaneously to keep equivalent states in each. Feedback provided by the cross-coupling further hastens the process of bus pull down. Still further acceleration of the pulldown process can result by sensing bus pulldown at trip point that is higher than a conventional logic level trip point. Segmenting the bus and coupling the segments with a precharge buffer results in less equivalent RC being presented to each bus segment. Thus, effective shunt capacitance is reduced, allowing use of downsized transistors coupled to the output buffer lines to pull down the bus segments.

Abstract: A push-pull output driver includes a pair of auxiliary, low current capacity output circuits connected in parallel with a pair of high current capacity, series connected devices. In response to a pulse transition at the input of the driver circuit, one of the high current capacity devices is turned on to provide the current necessary for a change in state of the output signal. After the output signal has reached a steady state level, the associated auxiliary low current capacity device is turned on and the high current capacity device is turned off. For the remainder of the duration of the pulse, the relatively low current required to maintain the output signal is provided by the auxiliary gate. At the next pulse transition, the other of the high current capacity gates is turned on. Since the first high current capacity gate was turned off prior to the pulse transition, only one of the high current capacity devices is drawing current from the supply and the need for a large current supply is eliminated.

Abstract: A fast turn-on electrical switch circuit includes a silicon controlled rectifier ("SCR") connected substantially in parallel with a MOS controlled thyristor ("MCT"). When the switch is turned on, the MCT turns on almost immediately and carries the circuit load during the spreading time of the SCR. The SCR subsequently carries the circuit load when it is turned fully on because it has a smaller forward drop, due in part to its larger area and/or higher carrier lifetime. The MCT and SCR may be gated simultaneously from the same or separate sources or the SCR may be gated with a portion of the current from the MCT. The switch may be integrated into a single semiconductor device with alternating MCT regions and SCR regions.

Abstract: The circuit for converting unipolar input to bipolar output includes a differential amplifier, first and second feedback resistors; and a peak detector. The negative output of the differential amplifier is fed back to the positive input of the differential amplifier through the first feedback resistor, and the positive output of the differential amplifier is fed back to the negative input of the differential amplifier through the peak detector and the second feedback resistor. A pole of lowest frequency among feedback amplifier circuits forming the circuit for converting unipolar input to bipolar output is to be determined with cut-off frequency of an amplification stage of the differential amplifier.

Abstract: A track and hold circuit is disclosed which may be used in high speed analog to digital conversions. The circuit includes a control transistor which keeps the circuit's input transistor in a conductive state even when the circuit is in hold mode. As a result, the track and hold circuit achieves a high switching speed while minimizing input voltage spikes.

Abstract: A low-power inverter (53) reduces power consumption over known inverter designs and is especially well-adapted for serving as a buffer in a Pierce crystal oscillator with a large load capacitance. The inverter (53) includes P- and N-side source-follower stages (310, 320) driving CMOS output transistor pairs (350, 360). The source followers are current-limited through current sources (311, 313, 321, 323) which are biased by a stable reference voltage such as a bandgap reference voltage. Clamping devices (331, 332) are provided to limit the voltages on the gates of the output transistors (350, 360), thereby limiting maximum currents thereof. In addition, a helper device (332) is connected to the gate of a P-channel output transistor (350). The P-channel output transistor (350) typically has a large gate area and thus a large capacitance, and the helper device (332) quickly increases the voltage at the gate when an input signal changes to a high voltage.