Abstract: A decoded source sense amplifier in which the column select signal is shaped so that it turns on bit select transistors at a predetermined time after the source electrodes of the sense amplifier are connected to ground, so as to give the sense amplifier time to latch before it is coupled to external bit lines.

Abstract: A semiconductor integrated circuit device has a first wire for transmitting a first signal and a second wire adjacent to the first wire, for transmitting a second signal having the stronger probability of having an opposite phase to that of the first signal. A space between the first and second wires is wider than a standard wiring space, to reduce a delay in the operation speed of the device due to wiring capacitance produced between the first and second wires.

Abstract: A single ended sense amplifier that not only preserves the high speed feature of the ordinary .vertline.V.sub.TP .vertline., the threshold voltage of a PMOS transistor, but also eliminates the current leakage problem of conventional designs. The single-ended sense amplifier uses seven transistors and one phase clock instead of eleven transistors and two phase clocks as used in the prior art.

Abstract: A sense amplifier is provided that has improved speed from input to output, particularly during low-to-high transitions on the output and minimizes power consumption. By removing the product term window circuit from the critical node, the overall speed of the amplifier is maximized. In addition, circuitry is included to speed up low-to-high transitions, high-to-low transitions and provide increased noise immunity over temperature variations.

Abstract: An integrated circuit output buffer that operates at a low power supply voltage (e.g., 3.3 volts) shares an I/O bondpad with input circuitry that operates at a higher voltage (e.g., 5 volt) signal level. The higher voltage signal level is typically obtained by connection of the bondpad to a bus that is connected to one or more output buffers on other IC's that operate at the higher power supply voltage level. The inventive output buffer obtains a decreased propagation delay by the use of an additional pull-up transistor in a configuration that protects the low voltage output transistors, including the additional transistor, from the higher voltage signal levels present on the bondpad. In this manner, the output buffer may be used in applications that require the relatively low propagation delay specified for the PCI bus, for example.

Abstract: A CMOS buffer includes an input inverter, and a pull-up circuit coupled to the input inverter. The pull-up circuit provides an additional, temporary, signal pull-up on the output terminal of the input inverter during a high to low signal transition on its input terminal. The pull-up circuit includes a means for creating a signal delay. In one embodiment, the means for creating a signal delay includes a second and third inverter in series, the second inverter receiving an output signal from the input inverter. The pull-up circuit further includes two transistors for transferring a high signal to an output line of the input inverter. One transistor is controlled by a signal transferred by the means for creating a delay. The other transistor is controlled by an input signal to the input inverter. This pull-up circuit configuration ensures that the signal transition from low to high is substantially equal to the signal transition from high to low on the output line of the input inverter.

Abstract: A high speed CMOS current switching circuit suitable for use in digital to analog converters for graphic interfaces having high pixel clock rates (high display resolutions), and such interfaces as may be used in portable and other battery operated or low power consumption applications. In operation, the current switching circuit normally steers an idle current to ground. If the bit of the digital to analog converter input digital signal represented by the respective source is a 1, the input signal representing the bit is delayed slightly while the current steered to ground is increased from the idle value to the full desired output current, whereupon at the end of the delay, the device coupling the output current to ground is turned off, thereby forcing the output current through an output device.

Abstract: A power transistor switching circuit includes a switching transistor. A switching signal triggers a control device which, via a delay device and a control amplifier applies a first control signal to a control electrode of the switching transistor. A thyristor is coupled to the control electrode of the switching transistor. The thyristor has a first trigger gate and a second trigger gate. A measuring circuit generates a measuring signal proportional to the current in the switching transistor. A comparison device compares the measuring signal with a reference signal for applying a second trigger signal to the thyristor second trigger gate. The control device includes a further control amplifier having an input coupled to the switching signal and an output which applies a further control signal to the first trigger gate. The delay device delays the first control signal with respect to the further control signal.

Abstract: Switchable diffused junction capacitors providing selectable data signal paths in a logic gate. A control circuit, such as a current switch, renders one of the junction capacitors conductive to present a large diffusion capacitance which acts as a fast signal pathway to the respectively applied data signal. Non-conducting junction capacitor presents a negligible diffusion capacitance which essentially acts as an open circuit to the respectively applied data signal. The control circuit response is slow and non-critical. The combination of a slow response control to configure selectable fast response data signal pathways is useful in "half good" or "partial good" semiconductor chip technologies, data buffers with fast flush, and self-test, self-repair chip designs, among others.