Abstract: Methods and devices to address body leakage current generation and bias voltage distribution associated with body leakage current in an OFF state of a FET switch stack are disclosed. The devices include charge redistribution arrangements and bridge networks to perform coupling/decoupling to/from the FET switch stack. Detailed structures of such bridge networks are also described.

Abstract: Methods and devices to address the undesired DC voltage distribution across switch stacks in OFF state are disclosed. The disclosed devices include charge control elements that sample the RF signal to generate superimposed voltages at specific points of the switch stack biasing circuit. The provided voltages help reducing the drooping voltages on drain/source/body terminals of the transistors within the stack by supplying the current drawn by drain/source terminals of the stacked transistors and/or by sinking the body leakage current exiting the body terminals of such transistors. Methods and techniques teaching how to provide proper tapping points in the biasing circuit to sample the RF signal are also disclosed.

Abstract: A first power supply rail is provided as a power supply tree configured with couplings to distribute a supply voltage to active elements of the circuit. A second power supply rail is provided as an electrostatic discharge channel and is not configured with distribution tree couplings to active elements of the circuit. A first electrostatic discharge circuit is directly electrically connected between one end of the second power supply rail and a ground rail. A second electrostatic discharge circuit is directly electrically connected between an interconnect node and the ground rail. The interconnect node electrically interconnects another end of the second power supply rail to the first power supply rail at the second electrostatic discharge circuit.

Abstract: A gate driver for driving a gate of a switching element in accordance with an input signal is provided. The gate driver is configured to change a gate driving condition in accordance with a detected value of power supply voltage. Each time when the switching element is turned off, the gate driver stores a time width from a time when the input signal is switched to an off command to a time when switch-off surge occurs in the switching device. If it is determined that the gate driving condition should be changed during turn-off operation of the switching element, the gate driver switches the gate driving condition when a time corresponding to the time width stored at a previous turn-off is elapsed after a current turn-off of the switching element is started.

Abstract: A switched-capacitor integrator is described having the contribution to offset from the charge injection mismatch of switches connected to the summing nodes mitigated by using a switching scheme that conveys basically all the charge injection to the output, thus preventing net offset from being integrated.

Abstract: A direction setting pin DIR receives a direction signal ROT that indicates the rotational direction of the stepping motor. A clock pin CLK receives a clock signal CLK that indicates the rotational direction of the stepping motor. A logic circuit generates a first internal signal and a second internal signal that respectively indicate the states of the first H-bridge circuit and the second H-bridge circuit according to the direction signal ROT and the clock signal CLK. When the clock signal CLK remains in a predetermined state for a predetermined judgment time, the logic circuit transits to a predetermined mode.

Abstract: A digital-to-analog converter (“DAC”) system for converting a digital input code to an analog signal, comprises: an N-bit DAC and a back-gate bias generator (“BBGEN”). The N-bit DAC has a reference cell and a current source array of unit cells for generating a DAC output. The (“BBGEN”) generates a first back-gate bias voltage PB_CSM and a second back-gate bias voltage PB_CSA. A back gate of the reference cell is configured to receive the first back-gate bias voltage PB_CSM. A back gate of each of the unit cells is configured to receive the second back-gate bias voltage PB_CSA. The reference cell is configured to generate a main current, and the unit cells are configured to mirror the main current.

Abstract: Described is an apparatus which comprises: a first power supply node to supply input power supply; a power transistor coupled to the first power supply node; a multiplexer to selectively control gate terminal of the power transistor according to whether the power transistor is to operate as part of a low dropout voltage regulator (LDO-VR) or is to operate as a digital switch; and a second power supply node coupled to the power transistor, the second power supply node to provide power supply to a load from the power transistor.

Abstract: In general, in one aspect, a direct-current to direct-current (DC-DC) converter that receive one or more of input voltages and generates one or more of output voltages. The DC-DC converter is capable of operating at one of a plurality of voltage conversion ratios and selection of the one of a plurality of voltage conversion ratios is based on an input voltage received, the DC-DC converter may include a plurality of capacitors, a plurality of inductors, and a plurality of switches which create a plurality of switched cells connected in cascade, in a stack, or in cascade and in a stack, wherein each switched cell is capable of operating in one of a plurality of modes.

Abstract: A Radio Frequency (RF) switch having two or more stages coupled in series is disclosed. A first Field-Effect Transistor (FET) with a first control terminal is coupled across a gate resistor to shunt the gate resistor when the first FET is on. An RF switching device is configured to pass an RF signal between a signal input and a signal output when the RF switching device is on. A second FET having a second control terminal coupled to an acceleration output is configured to shunt the RF switching device when the second FET is on. A third FET is coupled between the first control terminal and the signal input for controlling charge on a gate of the first FET. A third control terminal of the third FET is coupled to an acceleration input for controlling an on/off state of the third FET.

Abstract: Radio-frequency (RF) switch circuits having switchable transistor coupling for improved switching performance. An RF switch system includes at least one field-effect transistor (FET) disposed between first and second nodes, each FET having a gate and body. A switchable resistive coupling circuit is connected to each of the respective gates. A switchable resistive grounding circuit is connected to each of the respective bodies. The RF switch system also includes a compensation circuit to compensate a non-linearity effect generated by at least one of the field-effect transistors.

Abstract: Operational mode changes in a system-on-a-chip (SoC) integrated circuit in a complex device such as a mobile phone cause spikes in current demand which can cause voltage droops that disrupt operation of the SoC. A hybrid parallel power supply connects a switching-mode power supply and a low-dropout voltage regulator in parallel to provide high efficiency and fast response times. Integration of the voltage regulator on the SoC reduces parasitic impedance be between the voltage regulator and the load to aid in reducing voltage droops. The switching-mode power supply and the low-dropout voltage regulator can regulate their outputs to slightly difference voltage levels. This can allow the switching-mode power supply to supply most of the SoC's current demands.

Abstract: A high-voltage electronic switch includes first and second transistors defining a current flow path between an input and output of the switch. The transistors have a common point of the current flow path and a common control terminal. A control circuit includes a voltage line receiving a limit operating voltage and first and second branches coupled between the voltage line and the common point and common control terminal, respectively. Further transistors are activated, upon turning-off of the first and second transistors, for coupling the branches to the voltage line. The branches include a parallel connected resistor, diode, and string of diodes with opposite polarities. The diode of the first branch plus string of diodes of the second branch and diode of the second branch plus string of diodes of the first branch provide coupling paths between the voltage line and, respectively, the common point and common control terminal.

Abstract: The analog switch includes a first DMOS transistor of a second conductivity type that is connected to an input terminal at a first end of a current path thereof and to the gate of the first MOS transistor at a second end of the current path, and is controlled in accordance with the second current. The analog switch includes a second DMOS transistor of the second conductivity type that is connected to the second end of the current path of the first DMOS transistor at a first end of a current path thereof and to an output terminal at a second end of the current path and is controlled in accordance with the second current. The analog switch includes a first switch element that is connected between a gate and the second end of the current path of the first DMOS transistor.

Abstract: According to one embodiment, a semiconductor switch circuit includes a semiconductor substrate, an insulating film, a semiconductor layer, a first wiring line, a semiconductor switch unit, and a first conductor. The insulating film is provided on the semiconductor substrate. The semiconductor layer is provided on the insulating film. The first wiring line is provided above the insulating film. The semiconductor switch unit is provided on the semiconductor layer and is electrically connected to the first wiring line. The first conductor is provided between the first wiring line and the semiconductor substrate.

Abstract: A method for controlling a first switch and a second switch is suggested, wherein each switch is an RC-IGBT and wherein both switches are arranged as a half-bridge circuit. The method includes: controlling the first switch in an IGBT-mode; controlling the second switch such that it becomes desaturated when being in a DIODE-mode; wherein controlling the second switch starts before and lasts at least as long as the first switch changes its IGBT-mode from blocking state to conducting state.

Abstract: Radio-frequency (RF) switch circuits are disclosed including at least one first field-effect transistor (FET) disposed between first and second nodes, each of the at least one first FET having a respective body and gate. The RF switch circuit may include a coupling circuit that couples the respective body and gate of the at least one first FET, the coupling circuit configured to be switchable between a resistive-coupling mode and a body-floating mode, as well as an adjustable-resistance circuit connected to either or both of the respective gate and body of the at least one FET, the adjustable-resistance circuit including a resistor in parallel with a bypass switch.

Abstract: A Radio Frequency (RF) switch element is described. The RF switch element comprises a primary transistor element for facilitating switching an RF signal between circuit nodes. A pair of secondary transistor elements are also provided. The pair of secondary transistor elements are co-operable with the primary transistor element and provide respective signal paths which have a lower impedance level than an intrinsic element associated with the primary transistor element.

Abstract: In a signal generating circuit, a power supply terminal is connected with first terminals of a first switching element, a second switching element, and a third switching element; second terminals of the second switching element and the third switching element are connected to each other at a first node; the first node is connected with a ground and a first input terminal; a conduction control terminal of the third switching element is connected with the power supply terminal and the first terminal of the first switching element; a second terminal of the first switching element is connected with the first node; the second input terminal is connected with conduction control terminals of the first switching element and the second switching element; a first output terminal is connected with a second node; a second output terminal is connected with a third node; a first high-frequency cutoff element is connected with the power supply terminal and the second node; and a second high-frequency cutoff element is conne

Abstract: The present invention relates to an electronic device, the electronic device comprising at least one LED, a driving unit for applying a driving algorithm for driving the LED during normal operation, and a measurement unit for determining a forward voltage of the LED by imposing a test current to the LED, the measurement unit being programmed for determining test current characteristics taking into account said driving algorithm.

Abstract: A charge pump at least includes a current source, a first switch, a second switch, a level-shift circuit, and a capacitor. The first switch is coupled between the current source and an internal node. The capacitor is coupled between the internal node and the level-shift circuit. The second switch is coupled between the internal node and an output node. The first switch performs a closing-and-opening operation and the level-shift circuit performs a level-shift operation while the second switch is kept open and the internal node is isolated from the output node. The operating range of the charge pump is effectively widened by using the proposed design.

Abstract: A gate driver driving a switching device is disclosed. The gate driver includes a capacitor which is coupled to the input of the switching device. The gate drive power consumption is reduced by this additional capacitor.

Abstract: Disclosed are devices and methods related to a CMOS switch for radio-frequency (RF) applications. In some embodiments, the switch can be configured to include a resistive body-floating circuit to provide improved power handling capability. The switch can further include an electrostatic discharge (ESD) protection circuit disposed relative to the switch to provide ESD protection for the switch. Such a switch can be implemented for different switching applications in wireless devices such as cell phones, including band-selection switching and transmit/receive switching.

Abstract: Provided is a switching circuit capable of transmitting a signal with large amplitude and large current while suppressing deterioration when a small-amplitude signal is transmitted. The switching circuit 100 includes a first terminal a, a second terminal b, a first switch 1, a second switch 2, a first separation switch 3a, and a second separation switch 3b. The first switch 1 connects the first terminal a and the second terminal b according to a control signal. The second switch 2 has a first node n1 and a second node n2, and connects between the nodes in synchronization with the first switch 1. The first separation switch 3a transmits a signal of the first node n1 to the second node n2 when an electric potential of the first node n1 is higher than that of the second node n2 by more than a predetermined electric potential.

Abstract: A switching circuit includes first and second MOS transistors of the same conductive type. The second MOS transistor has a drain connected to a first terminal, a source connected to a load connecting terminal, a gate connected to a gate of the first MOS transistor, and a back gate connected to a source of the first MOS transistor. The switching circuit includes a circuit that controls a current flowing between the source of the first MOS transistor and a resistor connecting terminal so that the potential of the source of the first MOS transistor and the potential of the source of the second MOS transistor are equal. This switching circuit further includes a circuit that outputs a control signal to the gate of the first MOS transistor and the gate of the second MOS transistor and controls the operations of the first MOS transistor and the second MOS transistor.

Abstract: According to one embodiment, a switch circuit includes a transmission unit configured to transmit a signal through a transistor, in which a back gate and a source are connected by way of a resistor; and a back gate control unit configured to connect the back gate of the transistor to a fixed potential when the transistor is turned OFF, and to separate the back gate of the transistor from the fixed potential when the transistor is turned ON.

Abstract: Radio-frequency (RF) switch circuits are disclosed providing improved switching performance. An RF switch system includes at least one field-effect transistor (FET) disposed between a first node and a second node, each having a respective source, drain, gate, and body. The system includes a coupling circuit including a first path and a second path, the first path being between the respective source or the respective drain and the respective gate of the at least one FET, the second path being between the respective source or the respective drain and the respective body of the at least one FET. The coupling circuit may be configured to allow discharge of interface charge from either or both of the coupled gate and body.

Abstract: A path switching FET and a shunt FET are separated from each other by a capacitor. The gates of the path switching FET and the shunt FET are controlled using an inverter circuit having a first internal power supply voltage (e.g., 2.5 V) as a power supply. The sources and drains of the path switching FET and the shunt FET are controlled using an inverter circuit having a second internal power supply voltage (e.g., 1.25 V) which is smaller than the first internal power supply voltage, as a power supply.

Abstract: A circuit arrangement is disclosed for controlling the switching of a field effect transistor (FET). A current controlled amplifier may be configured to amplify a current in a current sense device to generate an amplified current, wherein the current in the current sense device indicates a current through the FET. A comparator may be coupled to the current sense amplifier to compare a voltage corresponding to the amplified current with a voltage reference and to generate a comparator output based on the comparison, wherein the comparator output controls whether the FET is on or off.

Abstract: One or more circuits are provided wherein leakage current is mitigated. A circuit comprises a pad, a first transistor, a second transistor, a power leakage component and a data leakage component. The first transistor and the second transistor are respectively configured to control a voltage level at the pad. The first transistor is connected to the pad and to a first voltage source. The second transistor is connected to the pad and to a third voltage source. The power leakage component is connected between the first transistor and the pad. The data leakage component is connected between the second transistor and the pad. The power leakage component is configured to mitigate leakage current from the first transistor to the pad. The data leakage component is configured to mitigate leakage current from the pad to the second transistor.

Abstract: A field device and method of operating high voltage semiconductor device applied with the same are provided. The field device includes a first well having a second conductive type and second well having a first conductive type both formed in the substrate (having the first conductive type) and extending down from a surface of the substrate, the second well adjacent to one side of the first well and the substrate is at the other side of the first well; a first doping region having the first conductive type and formed in the second well, the first doping region spaced apart from the first well; a conductive line electrically connected to the first doping region and across the first well region; and a conductive body insulatively positioned between the conductive line and the first well, and the conductive body correspondingly across the first well region.

Abstract: One gate driver includes an output node configured to be coupled to a gate line and to provide power to the gate line for driving thin-film transistor (TFT) gates of a display. An input node of the gate driver is configured to receive an input signal. The gate driver includes a first field-effect transistor (FET) having a gate, a drain, and a source. The drain may be coupled to the input node and the source may be coupled to the output node. The gate driver also includes a second FET having a gate, a drain, and a source. The drain may be coupled to the input node. The gate driver includes a capacitor having a first end coupled to the gates of the FETs and a second end coupled to the source of the second FET. Using the gate driver power consumption of the display may be reduced.

Abstract: A decoupling circuit includes an inverter. The inverter includes i (i is an integer of 1 or more) PMOS transistors each having a first gate electrode, and j (j is an integer of 0 or more) PMOS transistors each having a second gate electrode. The inverter includes m (m is an integer of 1 or more) NMOS transistors each having a third gate electrode, and n (n is an integer of 0 or more) NMOS transistors each having a fourth gate electrode. The first to fourth gate electrodes are coupled to an input end of the inverter. A total area of the first and second gate electrodes is different from a total area of the third and fourth gate electrodes.

Abstract: A circuit is described that includes a switch, a switchable clamping element coupled to the switch, and a driver configured to control the switch based at least in part on a driver control signal. The driver is further configured to enable or disable the switchable clamping element. The switchable clamping element is configured to clamp a voltage across the switch when the switchable clamping element is enabled by the driver and when the voltage across the switch or a current at the switch satisfies a threshold for activating the switchable clamping element.

Abstract: A gate drive circuit is disclosed that charges the gate of a switching transistor to a voltage that is high enough to turn the switching transistor fully on and then prevent the charge from flowing back into the gate drive circuit. The gate drive circuit works with a ground rectifier switch by providing a fully differential connection of the switching transistor and its capacitor and resistor in parallel with the antenna.

Abstract: A cascode transistor includes: a first switch; a second switch that has a withstand voltage higher than that of the first switch and is cascade coupled to a drain of the first switch; and a circuit in which a third switch and a capacitor are coupled in series with each other and that is provided between a connection node and a source of the first switch, the connection node being a node at which the first switch and the second switch are coupled to each other.

Abstract: Switching circuitry for use in a digital-to-analogue converter, the circuitry comprising: a common node; first and second output nodes; and a plurality of switches connected between the common node and the first and second output nodes and operable in each clock cycle of a series of clock cycles, based on input data, to conductively connect the common node to either the first or second output node along a given one of a plurality of paths, wherein the circuitry is arranged such that a data-controlled switch and a clock-controlled switch are provided in series along each said path from the common node to the first or second output node.

Abstract: A switching circuit includes a plurality of switching elements connected between an input node and an output node and each comprising a first and second electrode connected to the input node and output node, respectively. The switching elements include a control electrode for controlling electrical conductance between the first and second electrodes such the switching element can be switched between an ON conductance state and an OFF conductance state. A detection circuit in the switching circuit outputs a detection value corresponding to an output current at the output node. A control circuit changes the conductance state of at least one switching element such that the summed total of the parasitic capacitances of all switching elements in the ON state decreases as the output current decreases as indicated by the detection value.

Abstract: A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level connects a second subset of the PMOS drains together. The second subset of the PMOS drains is different than the first subset of the PMOS drains. The first interconnect and the second interconnect are disconnected on the interconnect level. A third interconnect on the interconnect level connects a first subset of NMOS drains together of the CMOS device. A fourth interconnect on the interconnect level connects a second subset of the NMOS drains together. The second subset of the NMOS drains is different than the first subset of the NMOS drains. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, and fourth interconnects are coupled together though at least one other interconnect level.

Abstract: A CMOS device with a plurality of PMOS transistors each having a PMOS drain and a plurality of NMOS transistors each having an NMOS drain includes a first interconnect on an interconnect level extending in a length direction to connect the PMOS drains together. A second interconnect on the interconnect level extends in the length direction to connect the NMOS drains together. A set of interconnects on at least one additional interconnect level couple the first interconnect and the second interconnect together. A third interconnect on the interconnect level extends perpendicular to the length direction and is offset from the set of interconnects to connect the first interconnect and the second interconnect together.

Abstract: According to one embodiment, a switch circuit includes a transmission unit configured to transmit a signal through a transistor, in which a back gate and a source are connected by way of a resistor; and a back gate control unit configured to connect the back gate of the transistor to a fixed potential when the transistor is turned OFF, and to separate the back gate of the transistor from the fixed potential when the transistor is turned ON.

Abstract: An ultrasound image system has a plurality of channels. At least one of the plurality of channels has a capacitive T/R switch.

Abstract: In various embodiment, a switch circuit arrangement is provided. The switch circuit arrangement may include a switch circuit, a driver circuit and a supply circuit. The driver circuit may be configured to control the switch circuit. The supply circuit may be configured to power the driver circuit. The supply circuit may include a first circuit configured to modify an output impedance of the supply circuit to have a first impedance when the driver circuit controls the switch circuit to be in a conducting state and to have a second impedance when the driver circuit controls the switch circuit to change from a non-conducting state to the conducting state.

Abstract: A field device and method of operating high voltage semiconductor device applied with the same are provided. The field device includes a first well having a second conductive type and second well having a first conductive type both formed in the substrate (having the first conductive type) and extending down from a surface of the substrate, the second well adjacent to one side of the first well and the substrate is at the other side of the first well; a first doping region having the first conductive type and formed in the second well, the first doping region spaced apart from the first well; a conductive line electrically connected to the first doping region and across the first well region; and a conductive body insulatively positioned between the conductive line and the first well, and the conductive body correspondingly across the first well region.

Abstract: Embodiments of radio frequency (RF) switching circuitry are disclosed that include (at least) a first switch and a body switching network operably associated with the first switch. The first switch has a first control contact, a first switch contact and a first body contact. The body switching network includes a first switchable path and a second switchable path. The first switchable path is connected between the first body contact and the first control contact of the first switch. Additionally, the second switchable path is connected between the first body contact and the first switch contact. Accordingly, the first body contact is can be appropriately biased by the switchable paths without requiring a resistor network and thus there is less loading. This maintains the Q factor of the RF switching circuitry.

Abstract: A gate driving circuit for a display is disclosed. The gate driving circuit utilizes at least one transistor connected in series between an input end of a reference voltage signal and a transistor connected to a node providing a high voltage level for making the at least one transistor share the voltage difference between the source electrode and the drain electrode of the transistor connected to the node. In such a manner, the gate driving circuit can reduce the occurrence of current leakage in the transistor, thereby improving the stability of driving voltage of the gate driving circuit and the reliability of the gate driving circuit.

Abstract: A switching device includes: a switch that selects and connects one of at least three terminals including a first terminal, a second terminal, and a third terminal to a common terminal; and a compensating circuit that shifts a phase of at least one of a first signal transmitted through the second terminal and a second signal transmitted through the third terminal so that the first signal and the second signal compensate each other and unifies and outputs the first signal and the second signal to a fourth terminal as a third signal, or that branches a third signal input to the fourth terminal into the first signal and the second signal.

Abstract: A multi-path transistor includes an active region including a channel region and an impurity region. A gate is dielectrically separated from the channel region. A signal line is dielectrically separated from the impurity region. A conductive shield is disposed between, and dielectrically separated from, the signal line and the channel region. In some multi-path transistors, the channel region includes an extension-channel region under the conductive shield and the multi-path transistor includes different conduction paths, at least one of the different conduction paths being in the extension-channel region to conduct substantially independent of a voltage on the signal line. In other multi-path transistors, the conductive shield is operably coupled to the impurity region and the multi-path transistor includes different conduction paths, at least one of the different conduction paths being under the conductive shield to conduct substantially independent of a voltage on the signal line.

Abstract: An electronic device which includes a first stage having an input capacitance, a switch, a buffer and a second stage having an input sensitive to charge injection and/or voltage glitches. An input of the buffer and the input of the second stage are coupled together at a first node which is configured to be coupled to a voltage source for supplying a reference voltage to the input of the first stage having the input capacitance. In a first configuration of the switch, the switch is arranged to either connect the input of the first stage to the first node and to disconnect the input of the first stage from an output of the buffer. In a second configuration of the switch, to connect the input of the first stage to the output of the buffer and to disconnect the input of the first stage from the first node.

Abstract: In an embodiment, a gate driver circuit and/or method therefor may include configuring the gate driver circuit form a drive current to supply to a gate of an MOS transistor wherein the value of the drive current is a minimum value that can be supplied to the gate without increasing a charge stored on a gate-to-source capacitance of the MOS transistor; configuring the gate driver circuit to change the value of the drive current responsively to changes of a Vgs of the MOS transistor.