Abstract: A circuit may include a controller, at least one bridge circuit, and a plurality of switches. The plurality of switches may be connected parallel to each other, each may have a switch output connected to the bridge circuit. The bridge circuit, upon receiving a current from the plurality of switches, may generate an output based on a reference voltage. The controller may generate a plurality of control signals, based on a voltage transition range, to selectively turn on the plurality of the switches in more than one combination, to supply a current to the output.

Abstract: A signal processing device and a measuring method are provided. A ring oscillator includes (2n+1) signal transmission circuits (n is an integer greater than or equal to 1). One of the signal transmission circuits comprises an inverter, a first transistor, and a second transistor; one of an input terminal and an output terminal of the inverter is connected to one of a source and a drain of the first transistor; one of a source and a drain of the second transistor is connected to a gate of the first transistor; an output of a k-th (k is an integer greater than or equal to 1 and less than or equal to 2n) signal transmission circuit is connected to an input of a (k+1)-th signal transmission circuit; and an output of a (2n+1)-th signal transmission circuit is connected to an input of a first signal transmission circuit.

Abstract: At a contact input circuit, a voltage at a switching device is sensed and the voltage is associated with a status of a switching device. The contact input circuit is operated according to the sensed voltage regardless of the value of the sensed voltage. The power usage of the contact input circuit is maintained to be within a predetermined range of power consumption values regardless of the value of the sensed voltage. Wetting voltages can be continuously monitored and the approaches described herein can monitor open contact, closed contact, and open field wire conditions.

Abstract: A control device for influencing a flow of energy in a load circuit between an electrical voltage source and an electrical load, having a semiconductor switch including a conductive section which is formed between an input connection and an output connection, can be looped into the load circuit, and has an electrical resistance adjustable by means of an electrical potential which can be applied to a control connection associated with the semiconductor switch, and having a control circuit which is coupled to the control connection and includes a freewheeling means connected in parallel to the load. The control circuit is designed to supply a control current at the control connection which is proportional to a voltage via the freewheeling means.

Abstract: A system for controlling gate power includes a metal oxide semiconductor field effect transistor (MOSFET) configured to supply power to a load according to a gate control voltage applied to a gate of the MOSFET. The system includes a gate control circuit configured to turn on and off the gate control voltage supplied to the gate of the MOSFET. The system also includes a ramping circuit configured to perform at least one of ramping up a voltage applied to the gate of the MOSFET based on the gate control circuit turning on power to the gate of the MOSFET and ramping down the voltage applied to the gate of the MOSFET based on the gate control circuit turning off power to the gate of the MOSFET.

Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.

Abstract: An integrated circuit 2 includes a transistor 26 Which has a normal switching speed arising during normal operations of that transistor that apply electrical signals within normal ranges. If it is desired to change the speed of operation of the transistor, then speed tuning circuitry 12 applies a tuning electrical signal with a tuning characteristic outside of the normal range of characteristics to the transistor concerned. The tuning electrical signal induces a change in at least one of the physical properties of that transistor such that when it resumes its modified normal operations the switching speed of that transistor will have changed. The tuning electrical signal may be a voltage (or current) outside of the normal range of voltages applied to the gate of a transistor so as to induce a permanent increase in the threshold of that transistor and so slow its speed of switching. Temperature of a transistor may also be controlled to induce a permanent change in performance/speed.

Abstract: The present invention generally relates to an architecture for isolating an RF MEMS device from a substrate and driving circuit, series and shunt DVC die architectures, and smaller MEMS arrays for high frequency communications. The semiconductor device has one or more cells with a plurality of MEMS devices therein. The MEMS device operates by applying an electrical bias to either a pull-up electrode or a pull-down electrode to move a switching element of the MEMS device between a first position spaced a first distance from an RF electrode and a second position spaced a second distance different than the first distance from the RF electrode. The pull-up and/or pull-off electrode may be coupled to a resistor to isolate the MEMS device from the substrate.

Abstract: A method for controlling two electrically series-connected reverse-conductive (RC) IGBTs (RC-IBGT) of a half bridge is disclosed, wherein an operating DC voltage is applied across the series connection and one of the two series-connected reverse-conductive IGBTs operates in IGBT mode and another of the two series-connected reverse-conductive IGBTs operates in diode mode, and wherein each of the two reverse-conductive IGBTs has three switching states “+15V”, “0V”, “?15V”. The RC-IGBT T1 operated in diode mode does not go into the switching state (?15V) of highly charged carrier concentration, but instead into a state of medium charge carrier concentration associated with the switching state “0V”, and not into the switching state “?15V”, as is known from conventional methods. This reduces the reverse-recovery without adversely affecting the forward voltage.

Abstract: A data link circuit switches high-speed signals through FET-based circuitry between channels. A FET responds to control signals at the gate terminal to operate in either a signal-passing mode or another (blocking) mode. In the passing mode, an AC (high-speed) signal is passed between the S-D terminals by coupling a first signal portion (of the AC signal) and with another signal portion diverted by the inherent capacitances associated with the FET. For offsetting the loading caused by the inherent capacitances associated with the FET-based switch, a biasing circuit is configured and arranged to bias the back-gate terminal of the FET transistor with a follower signal.

Abstract: A data link circuit switches high-speed signals through FET-based circuitry between channels. A FET responds to control signals at the gate terminal to operate in either a signal-passing mode or another (blocking) mode. In the passing mode, an AC (high-speed) signal is passed between the S-D terminals by coupling a first signal portion (of the AC signal) and with another signal portion diverted by the inherent capacitances associated with the FET. For offsetting the loading caused by the inherent capacitances associated with the FET-based switch, a biasing circuit is configured and arranged to bias the back-gate terminal of the FET transistor with a follower signal.

Abstract: In one implementation, a switching circuit includes a pass switch including group III-V, for example III-Nitride, transistors coupled between an input of the switching circuit and an output of the switching circuit. The switching circuit further includes a shunt switch configured to ground the input of the switching circuit while the pass switch is disabled. The switching circuit also includes a gate control transistor configured to reduce resistance between a control terminal of the pass switch and/or the shunt switch and gate of the group III-V transistor of the pass switch and/or the shunt switch so as to enable and disable the pass switch and/or shunt switch. The gate control transistor can be coupled across a gate resistor of the pass switch and/or the shunt switch. The gate control transistor can reduce the resistance in order to lower the OFF state impedance of the pass switch and/or the shunt switch.

Abstract: According to example embodiments, a method for controlling a gate voltage applied to a gate electrode of a high electron mobility transistor (HEMT) may include measuring a voltage between a drain electrode and a source electrode of the HEMT, and adjusting a level of the gate voltage applied to the gate electrode of the HEMT according to the measured voltage. The level of the gate electrode may be adjusted if the voltage between the drain electrode and the source electrode is different than a set value.

Abstract: An insulated gate turn-off (IGTO) device has a layered structure including a p+ layer (e.g., a substrate), an n-type layer, a p-type layer (which may be a p-well), n+ regions formed in the surface of the p-type layer, and insulated planar gates over the p-type layer between the n+ regions. The layered structure forms vertical NPN and PNP transistors. The p-type layer forms the base of the NPN transistor. When the gates are sufficiently positively biased, the underlying p-type layer inverts to reduce the width of the base to increase the beta of the NPN transistor. This causes the product of the betas of the NPN and PNP transistors to exceed one, and the device becomes fully conductive. When the gate voltage is removed, the base width increases such that the product of the betas is less than one, and the device shuts off. No latch-up occurs in normal operation.

Abstract: The invention stems from the realization that it is possible to control the electric field in the gate region of a field effect transistor (MOS, FET etc.) without changing the net charge of the gate electrode or without resorting to electrical conduction. According to an aspect of the invention, the electric field is changed by modifying the charge distribution within the gate electrode without materially adding or subtracting charge carriers to it or changing its net charge. This is achieved by displacing one or more sources of electric field, for example free charges, or conductive or non-conductive surface charges in the proximity of the gate electrode. By electric induction, the electric field produce a separation of charges in the gate electrode and an alteration in the conduction state of the FET transistor.

Abstract: An output thin film transistor threshold voltage offset compensation circuit, a GOA circuit, and a display. The circuit includes: a first capacitor, comprising a first electrode and a second electrode, the first electrode being connected to the gate of an output thin film transistor and receiving a charge signal, the second electrode being connected to the drain of the output thin film transistor, the first capacitor being used for, under the action of the charge signal, making the first electrode and the second electrode have a same voltage, so that a voltage difference between the drain and the source of the output thin film transistor is equal to a threshold voltage thereof; a first switch unit, connected to the drain and the source of the output thin film transistor, and opening under the action of a first clock signal, so that a voltage difference between the gate and the source of the output thin film transistor is equal to the threshold voltage thereof.

Abstract: A method for operating a field-effect transistor having a source terminal, a drain terminal, a gate terminal, a drift region and a dielectric region adjoining the drift region, is provided. The method includes: connecting at least one of the drain terminal and the source terminal to a load; applying a sequence of voltage pulses between the gate terminal and the source terminal to repetitively switch the field-effect transistor such that the field-effect transistor is driven in an avalanche mode between the voltage pulses, during the avalanche mode avalanche multiplication occurring in the drift region close to the dielectric region; and applying at least one relaxation pulse to the field-effect transistor to reduce an accumulation of charges in the dielectric region due to hot charge carriers generated in the avalanche mode. Further, a field-effect transistor and a circuit configuration including the field-effect transistor are provided.

Abstract: A switching circuit according to one embodiment includes first to fourth semiconductor switch elements. A pulse-like signal is applied to each input terminal of the switch elements such that when the first and fourth switch elements are in an ON (OFF) state, the remaining switch elements are in an OFF (ON) state. The switching circuit includes first and second capacitance elements. The first capacitance elements connected between an output terminal of the second semiconductor switch element and the second capacitance elements connected between an input terminal of the second semiconductor switch element and an output terminal of the fourth semiconductor switch element has a capacitance to reduce a parasitic capacitance between the input and output terminals of each of the fourth and second switch elements at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse-like signal.

Abstract: A gate driving apparatus according to the embodiment includes a first switching device, a second switching device that outputs a signal to charge a capacitance of the first switching device, a third switching device connected in parallel to the second switching device to prevent a drop of a voltage output from the second switching device, and a fourth switching device that outputs a signal to discharge the capacitance of the first switching device. An NMOS transistor is used as a main switching device and a PMOS transistor connected in parallel to the NMOS transistor is used as a sub-switching device, so that the chip size is reduced without dropping the output voltage of the gate driving apparatus. The loss of the switching device is prevented by preventing the output voltage of the gate driving apparatus from being dropped.

Abstract: A switching circuit according to one embodiment is a switching circuit including at least one semiconductor switch element having an input, output, and a common terminals, a pulse-like signal being applied between the input and common terminals to switch a current between the output and common terminals. The switching circuit further includes a capacitance suppression element section connected at least one of between the input and output terminals, between the input terminal common terminals, and between the output and common terminals. The capacitance suppression element section reduces a parasitic capacitance between the terminals of the semiconductor switch element where the capacitance suppression element section is connected to less than that obtained when the capacitance suppression element section is not connected at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse-like signal.

Abstract: A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET.

Abstract: An electronic component is described which includes a first transistor encased in a first package, the first transistor being mounted over a first conductive portion of the first package, and a second transistor encased in a second package, the second transistor being mounted over a second conductive portion of the second package. The component further includes a substrate comprising an insulating layer between a first metal layer and a second metal layer. The first package is on one side of the substrate with the first conductive portion being electrically connected to the first metal layer, and the second package is on another side of the substrate with the second conductive portion being electrically connected to the second metal layer. The first package is opposite the second package, with at least 50% of a first area of the first conductive portion being opposite a second area of the second conductive portion.

Abstract: Provided is a digital circuit (30) that comprises: a switching circuit (31) having first transistors (32, 33) supplied with power supply potentials (VDD, VSS); correcting circuits (34, 36) connected between an input terminal (IN) inputted with an input signal and control terminals (gates) of the first transistors; capacitors (C2, C3) connected between the control terminals and the input terminal; diode-connected second transistors (35, 37) that are provided between nodes (N5, N6) between the capacitors and the control terminals and the power supply potentials and have the substantially same threshold voltage as the first transistors; and switches (SW2, SW3) connected in series with the second transistors.

Abstract: The present invention copes with fluctuations in a power supply voltage when a capacitor for coping with fluctuations in the power supply voltage has been omitted and also cases in which the power supply voltage is constantly low, thereby ensuring driving of an active element. A gate driving device of an IGBT includes: a first switch portion which turns on the IGBT; a second switch portion which turns off the IGBT; a current control portion which controls the outflow of charge on the gate to a ground line such that current is constant; a first protection circuit which suppresses outflow of gate current to the power supply line; and a second protection circuit which detects a prescribed fluctuation in an internal power supply voltage Vdc, and interrupts the connection between the current control portion and the ground line.

Abstract: The present invention relates to a device for neutralization of a signal obtained by transposition to a high frequency of a useful signal supplied by a unit of equipment, the said equipment having a spurious capacitance Cparasite that varies over time. The device comprises a neutralization capacitance Cneut and means with adjustable gain G, together with means for feedback controlling the gain G in such a manner that, continuously, G×Cneut=Cparasite.

Abstract: The semiconductor device includes first and second output terminals each coupled to one end side and another end side of an inductive or capacitive load, a first MOS transistor coupled between a first voltage and the first output terminal, a second MOS transistor coupled between a second voltage and the first output terminal, a third MOS transistor coupled between the first voltage and the second output terminal, a fourth MOS transistor coupled between the second voltage and the second output terminal, and a drive circuit driving the first to fourth MOS transistors for controlling the inductive or capacitive load, and further includes first and second bypass transistors for bypassing a forward current of a parasitic diode of a PN-junction formed in the MOS transistor in the dead-off period.

Abstract: A low voltage isolation switch is coupled between an input terminal suitable for receiving a high voltage signal and an output terminal suitable for transmitting this high voltage signal to a load. The isolation switch includes a first driving transistor coupled between a first reference terminal and an intermediate node, a second driving transistor coupled between the intermediate node and the second reference terminal, a control transistor connected across a diode block coupled between the input and output terminals. The control transistor has a control terminal connected to the intermediate node through a low voltage decoupling block that includes first and second substrate terminals, first and second parasitic capacitive element connected to these first and second substrate terminals, and first and second decoupling transistors coupled in parallel to each other and having control terminals connected to the first and second parasitic capacitive elements, respectively.

Abstract: This disclosure relates to a compensating for nonlinearity resulting from a capacitance feedback in current cells of a single ended digital to analog circuit.

Abstract: In one general aspect, an apparatus can include a complementary switch circuit including a first portion and a second portion, and a first driver circuit coupled to the first portion of the complementary switch circuit. The apparatus can include a positive charge pump device coupled to the first driver, and a second driver circuit coupled to the second portion of the complementary switch circuit. The apparatus can also include a negative charge pump device coupled to the second driver circuit.

Abstract: An RF switch includes a transistor and a compensation capacitor circuit. The compensation capacitor circuit includes a first compensation capacitor and a second compensation capacitor of the same capacitance. The compensation capacitor circuit is used to improve voltage distribution between a control node and a first node of the transistor and between the control node and a second node of the transistor.

Abstract: A bootstrap circuit includes an input terminal, an inverting input terminal, an output terminal, an inverting output terminal, a first sub-bootstrap circuit, a second sub-bootstrap circuit, and a charging path providing circuit. The first sub-bootstrap circuit includes a first bootstrap capacitor, a first charging path, a first discharging path, and a first high voltage providing path. The charging path providing circuit includes a third charging path. In response to a high voltage level inputted into the input terminal, the first charging path and the third charging path are turned on, the first bootstrap capacitor is charged to a capacitor voltage, and the first discharging path is turned on to discharge the output terminal. In response to a low voltage level inputted into the input terminal, a first superimposed voltage including the high voltage level and the capacitor voltage is provided to the output terminal.

Abstract: A method for controlling two electrically series-connected reverse-conductive (RC) IGBTs (RC-IBGT) of a half bridge is disclosed, wherein an operating DC voltage is applied across the series connection and one of the two series-connected reverse-conductive IGBTs operates in IGBT mode and another of the two series-connected reverse-conductive IGBTs operates in diode mode, and wherein each of the two reverse-conductive IGBTs has three switching states “+15V”, “0V”, “?15V”. The RC-IGBT T1 operated in diode mode does not go into the switching state (?15V) of highly charged carrier concentration, but instead into a state of medium charge carrier concentration associated with the switching state “0V”, and not into the switching state “?15V”, as is known from conventional methods. This reduces the reverse-recovery without adversely affecting the forward voltage.

Abstract: An A/D conversion apparatus includes first to M-th ADC connected in parallel converting an analog input signal to digital signals in response to M-phase sampling signals, a reference A/D conversion circuit that converts the analog input signal to a digital signal in response to a divided-by-(n×M+1) sampling signal; and a control unit that compares, for each period of (n×M+1) clock cycles, one of the digital signals from a corresponding one of first to M-th ADC with the digital signal from the reference ADC in a predetermined order of the first to M-th ADC, and generates a compensation control signal based on the comparison result for supply to the corresponding ADC.

Abstract: A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

Abstract: A charging circuit includes a first current mirror for receiving an input voltage, a second current mirror including a first branch circuit and a second branch circuit for receiving the input voltage, a switch transistor coupled to the first current mirror and the first branch circuit for determining a conduction condition of the switch transistor according to a switch signal, a first resistor including a first resistance and one end coupled to the switch transistor, and a second resistor including a second resistance and one end coupled the second branch circuit of the second current mirror, wherein the first current mirror and the second current mirror perform a charging operation of a loading circuit according to the first resistance and the second resistance.

Abstract: A high-frequency switching circuit includes a high-frequency switching transistor, wherein a high-frequency signal-path extends via a channel-path of the high-frequency switching transistor. The high-frequency switching circuit includes a control circuit and the control circuit is configured to apply at least two different bias potentials to a substrate of the high-frequency switching transistor, depending on a control signal received by the control circuit.

Abstract: A gate driving apparatus according to the embodiment includes a first switching device, a second switching device that outputs a signal to charge a capacitance of the first switching device, a third switching device connected in parallel to the second switching device to prevent a drop of a voltage output from the second switching device, and a fourth switching device that outputs a signal to discharge the capacitance of the first switching device. An NMOS transistor is used as a main switching device and a PMOS transistor connected in parallel to the NMOS transistor is used as a sub-switching device, so that the chip size is reduced without dropping the output voltage of the gate driving apparatus. The loss of the switching device is prevented by preventing the output voltage of the gate driving apparatus from being dropped.

Abstract: A switched capacitor circuit includes an inverter, a first capacitor, and a first switch unit. The inverter is arranged to receive a control signal to generate an inverting control signal corresponding to the control signal. The first capacitor is coupled between a first output port and a first node. The first switch unit is arranged to receive a first input signal and a second input signal, and selectively couple the second input signal to the first node according to the first input signal. The first input signal is determined by one of the control signal and the inverting control signal, and the second input signal is determined by the other of the control signal and the inverting control signal.

Abstract: A precision charge dump circuit configured to transfer preset quanta of charge to or from a first capacitor (for example, an integration capacitor in an in-pixel ADC circuit). In one example, the charge dump circuit uses a second capacitor that is pre-charged with the preset quanta of charge to determine the preset value of the quanta of charge, and an amplifier in a voltage-follower mode to cause the charge subtraction or addition.

Abstract: A method for digitizing at least a portion of a selected analog input signal of a plurality of analog input signals by using a multiplexer having a plurality of channels is provided. Each channel for the multiplexer is associated with at least one of the analog input signals and is associated with a pair of select signals, and wherein each channel includes a cell having an input terminal, an output terminal, and a boosted NMOS switch. According to the method, a first select signal from each pair of select signals is asserted to decouple the input and output terminals for each cell. A boost capacitor is also charged during the non-sampling or conversion phase while the first select signal from each pair of select signals is asserted.

Abstract: Disclosed is a device for driving an inverter having a semiconductor switching element. A gate voltage calculating unit (20) calculates a surge voltage from the temperature, current, and DC-side voltage of each of IGBTs of the inverter and compares the surge voltage with the breakdown voltage of the element. The gate voltage calculating unit (20) commands a gate voltage control unit (22) to set a gate voltage higher than the normal value (reference value) in the case of judging that the difference between the element breakdown voltage and the surge voltage exceeds a predetermined threshold voltage and that a margin exists in the surge voltage. The voltage control unit (22) performs switching control of gates of the IGBTs according to the gate voltage command higher than the reference voltage to thereby reduce stationary losses of the IGBTs.

Abstract: Electronic modules, and methods of forming and operating modules, are described. The modules include a capacitor, a first switching device, and a second switching device. The electronic modules further include a substrate such as a DBC substrate, which includes an insulating layer between a first metal layer and a second metal layer, and may include multiple layers of DBC substrates stacked over one another. The first metal layer includes a first portion and a second portion isolated from one another by a trench formed through the first metal layer between the two portions. The first and second switching devices are over the first metal layer, a first terminal of the capacitor is electrically connected to the first portion of the first metal layer, and a second terminal of the capacitor is electrically connected to the second portion of the first metal layer, with the capacitor extending over the trench.

Abstract: A SAR ADC includes a DAC including a first set of capacitors each having a first end connected to a common node, and a second end, and a first set of switches each connecting the second end of a respective one of the capacitors to a first reference voltage. The SAR ADC further includes a second set of capacitors each having a first end connected to the common node and a second end that receives an input to be converted when the common node is connected to ground. The SAR ADC further includes a second set of switches that selectively connect the second end of a first capacitor of the second set of capacitors to ground when the input is disconnected from the second ends of the second set of capacitors and when the common node is disconnected from ground during a first of a plurality of successive approximations.

Abstract: A digital-to-analog converter converts a digital input signal into an analog output signal. The digital-to-analog converter includes an input selector configured to input the digital input signal and an output terminal configured to output the analog signal. An array of current source cells is provided. Each current source cell includes a current source transistor having a gate terminal and a source terminal, a current source switch for coupling the source terminal to the output terminal based on the digital input signal, and a compensation capacitor configured to compensate a capacitive feedback between the gate terminal and the source terminal when the source terminal is coupled to the output terminal. At least one of the current source cells further includes a calibration circuit configured to detect a voltage variation at the gate terminal and provide a compensation voltage for the compensation capacitor.

Abstract: A capacitance compensation circuit includes an input terminal, a plurality of switches coupled to the input terminal, a plurality of varactors coupled to the plurality of switches, and a plurality of blocking capacitors coupled between the plurality of switches and the plurality of varactors. The capacitance compensation circuit further includes a plurality of adjustable biasing circuits to precisely compensate for linear and parabolic voltage dependent components of an input or other capacitor. Two such circuits can be used with a single input terminal to compensate for both increasing and decreasing voltage dependent characteristics of a target capacitor.

Abstract: Provided is a digital circuit (30) that comprises: a switching circuit (31) having first transistors (32, 33) supplied with power supply potentials (VDD, VSS); correcting circuits (34, 36) connected between an input terminal (IN) inputted with an input signal and control terminals (gates) of the first transistors; capacitors (C2, C3) connected between the control terminals and the input terminal; diode-connected second transistors (35, 37) that are provided between nodes (N5, N6) between the capacitors and the control terminals and the power supply potentials and have the substantially same threshold voltage as the first transistors; and switches (SW2, SW3) connected in series with the second transistors.

Abstract: A multiport radio frequency (RF) switch circuit is disclosed. The switch circuit includes a first transistor that is connected to a first port, a common antenna port, and a first enable line. The first transistor is selectively activatable in response to a first enable signal applied to the first enable line. There is also a second transistor connected to a second port, the common antenna port, and a second enable line. The second transistor is selectively activatable in response to a second enable signal applied to the second enable line. A first inductor connected to the first port and the second port compensates for parasitic capacitance between the first port and the second port from an inactive one of the transistors.

Abstract: Reducing, suppressing or canceling series parasitic inductance and/or resistive effects that affect the frequency response of components, elements and/or circuits in an electronic circuit or system that exhibit capacitance is disclosed. Noise generated by series parasitic inductance and/or parasitic resistance of the components, the physical orientation of the components, and/or the layout of components, devices and/or conductive tracks (board traces) on printed circuit boards within an electronic circuit or system is reduced, suppressed or canceled. The reduction, suppression or cancellation is achieved by adding a voltage source in series with a part or component of the electronic circuit or system that exhibits capacitance, the current source being adapted to deliver a compensating voltage of roughly equal magnitude and roughly opposite phase to parasitic voltage associated with the part or component.

Abstract: A capacitance compensation circuit includes a plurality of switches having a first node coupled to an input terminal, a plurality of capacitors each coupled to a respective second node of the plurality of switches, and an adjustment circuit for providing a plurality of adjustable bias levels to a plurality of switch control nodes to precisely compensate for linear and parabolic voltage dependent components of an input or other capacitor. Two such circuits can be used with a single input terminal to compensate for both increasing and decreasing voltage dependent characteristics of a target capacitor.

Abstract: A capacitance compensation circuit includes a plurality of switches having a first node coupled to an input terminal, a plurality of capacitors each coupled to a respective second node of the plurality of switches, and an adjustment circuit for providing a plurality of adjustable bias levels to a plurality of switch control nodes to precisely compensate for linear and parabolic voltage dependent components of an input or other capacitor. Two such circuits can be used with a single input terminal to compensate for both increasing and decreasing voltage dependent characteristics of a target capacitor.