Abstract: A capacitance compensation circuit includes a plurality of switches having a first node coupled to an input terminal, a plurality of capacitors each coupled to a respective second node of the plurality of switches, and an adjustment circuit for providing a plurality of adjustable bias levels to a plurality of switch control nodes to precisely compensate for linear and parabolic voltage dependent components of an input or other capacitor. Two such circuits can be used with a single input terminal to compensate for both increasing and decreasing voltage dependent characteristics of a target capacitor.

Abstract: A capacitance compensation circuit includes an input terminal, a plurality of switches coupled to the input terminal, a plurality of varactors coupled to the plurality of switches, and a plurality of blocking capacitors coupled between the plurality of switches and the plurality of varactors. The capacitance compensation circuit further includes a plurality of adjustable biasing circuits to precisely compensate for linear and parabolic voltage dependent components of an input or other capacitor. Two such circuits can be used with a single input terminal to compensate for both increasing and decreasing voltage dependent characteristics of a target capacitor.

Abstract: A power module comprises: first and second terminals; first and second switching elements having a first electrode and a second electrode which is connected to the second terminal; first and second wirings respectively connecting the first electrodes of the first and second switching elements to the first terminal; and a third wiring directly connecting the first electrode of the first switching element to the first electrode of the second switching element, wherein parasitic inductances of the first and second wiring are different or switching characteristics of the first and second switching elements are different.

Abstract: In a D/A converter that has a plurality of current sources (IS1, IS2 and IS3-1 to IS3-63) each including a transistor, and is for converting an input digital signal into an analog signal by selecting paths of currents output from the current sources (IS1, IS2 and IS3-1 to IS3-63), depending on the digital signal, a forward body bias voltage is applied to a back-gate terminal of the transistor included in each current source (IS1, IS2 and IS3-1 to IS3-63).

Abstract: Switches with improved biasing and having better isolation and reliability are described. In an exemplary design, a switch is implemented with a set of transistors, a set of resistors, and an additional resistor. The set of transistors is coupled in a stacked configuration, receives an input signal, and provides an output signal. The set of resistors is coupled to the gates of the set of transistors. The additional resistor is coupled to the set of resistors and receives a control signal for the set of transistors. The resistors reduce signal loss through parasitic capacitances of the transistors when they are turned on. The resistors also help split the signal swing of the input signal approximately evenly across the transistors when they are turned off, which may improve reliability of the transistors. The switch may be used in a switchplexer, a power amplifier (PA) module, etc.

Abstract: A high-frequency switch circuit according to the present invention includes at least a first switch connected between a common terminal and a first terminal, and a second switch connected between the common terminal and a second terminal. Each of the first and second switches includes a plurality of field-effect transistors connected in series and each having a body, a source, a drain, and a gate. A compensation capacitance that compensates a parasitic capacitance generated when the first switch is in an off-state is formed between the drain and the body or between the source and the body in the FET of the first switch. A compensation capacitance that compensates a parasitic capacitance generated when the second switch is in an off-state is formed between the drain and the body or between the source and the body in the FET of the second switch.

Abstract: A switching circuit. The novel switching circuit includes an active device and a first circuit for providing a reactive inductive load in shunt with the active device. In an illustrative embodiment, the first circuit is implemented using a transmission line coupled between an output of the active device and ground, in parallel with the device, to minimize the parasitic effects of the device drain to source capacitance. In a preferred embodiment, the active device includes a silicon-germanium NFET optimized for operation at high frequencies (e.g. up to 20 GHz). The optimization process includes coupling a compact, low-parasitic polysilicon resistor to a gate of the NFET to provide gate RF isolation, and designing the gate manifold, drain manifold, and drain to source spacing of the NFET for optimal high frequency operation.

Abstract: This disclosure relates to a compensating for nonlinearity resulting from a capacitance feedback in current cells of a single ended digital to analog circuit.

Abstract: A driving circuit of a switch includes first and second transistors connected in series to each other and to relative intrinsic diodes in antiseries and driven by a driving device that includes at least one first and one second output terminal connected to the switch to supply it with a first control signal for driving the switch in a first working state and a second control signal for driving the switch in a second working state. At least one latch circuit coupled between respective common gate and source terminals of the first and second transistors supplies the common gate terminal with the first and second control signals, respectively, according to the working state to turn off and turn on the first and second transistors.

Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.

Abstract: A method for reducing a parasitic capacitance of an electrostatic discharge (ESD) protection circuit for an integrated circuit (IC) includes providing an ESD protection circuit including a plurality of transistors; coupling one end of a resistor to a shared drain of the plurality of transistors; and coupling an opposite end of the resistor to at least one of an input pad of the IC, a blocking capacitor of the IC and a transistor in the IC.

Abstract: Power savings are achieved for digital data transport over short distances by using the characteristics of resonant LC circuits. Economy of circuit elements is achieved by enabling a single pair of resonant circuits to drive large numbers of digital data lines or nodes in parallel. This maximizes power efficiency and minimizes area and cost. Resistance is minimized by insuring that all switches in the current path are fully “ON” whenever significant current is flowing through them. All other parasitic resistances in the circuits, consisting primarily of parasitic interconnect resistances, are minimized. This enables the data transmission circuits to achieve maximum Q or quality factor, which minimizes power dissipation.

Abstract: In a semiconductor device, a method for reducing the effect of crosstalk from an aggressor line to a victim line begins with sensing the occurrence of a voltage change on the aggressor line that can induce a voltage pulse having a pulse magnitude that exceeds a pulse threshold on the victim line. The induced voltage pulse is counteracted by coupling the victim line to a counteracting voltage source. After a predetermined delay period, the coupling of the counteracting voltage source is removed from the victim line. The voltage change on the aggressor line my be sensed from a node connected to either the aggressor line or the victim line. A rising induced pulse is counteracted by coupling the victim line to a more negative voltage source, and a falling induced pulse is counteracted by coupling the victim line to a more positive voltage source.

Abstract: An active-load dominant circuit for common-mode glitch interference cancellation, biased between a first voltage potential and a second voltage potential with an accompanying common-mode glitch interferer. The active-load dominant circuit includes a pair of pull-up networks and a pair of active-load networks. The common-mode glitch interferer is cancelled out due to a symmetric structure of the pair of pull-up networks. At least one set signal and at least one reset signal are provided to a latch in response to a clock signal or a complemented clock signal. At least one of the set signal and the reset signal can be pulled up to the first voltage potential or pulled down to the second voltage potential. The voltage difference of the set signal and the reset signal is large enough for a latch.

Abstract: Systems and methods for reducing the magnitude of signal dependent capacitance are provided. Capacitance canceling circuitry is operative to generate cancellation capacitance in response to the magnitude of a signal, which may be the same signal that produces the undesired signal dependent capacitance, to at least partially cancel the signal dependent capacitance.

Abstract: This disclosure relates to a compensating for nonlinearity resulting from a capacitance feedback in current cells of a single ended digital to analog circuit.

Abstract: An integrated circuit includes: a terminal for outputting data, a driver for providing the data to the terminal, and a switch for selectively connecting/disconnecting the driver to the terminal. The disconnection of the driver reduces the capacitive load on the connection between the terminal and driver, thus reducing limitations on data rate from factors such as data reflections that reduce signal quality. Selective connection/disconnection allows the driver to be reconnected to the terminal only when needed.

Abstract: A system-on-chip or other circuit has an on-chip noise-free ground which is added to divert ground noise from the sensitive nodes. An on-chip decoupling capacitor, tuned in resonance with the parasitic inductance of the interconnects, can be provided to add an additional low impedance ground path.

Abstract: Integrated circuit transmitters allow for ultrasound imaging with both pulsed and continuous waves. High voltage and low voltage switches are integrated onto a same semiconductor chip. The high voltage switches are used for pulsed wave operation, and the low voltage switches are used for continuous wave operation. Power dissipation may be reduced by using low voltage circuits for the continuous wave operation. Both the pulsed and continuous waveforms are output on a common output from the integrated circuit. For continuous wave operation, one or more of the high voltage switches is used to provide a low resistance path to the common output or ground. For pulsed wave operation, one or more of the low voltage switches is used to provide a low resistance path to a common output or ground. A switch used for generating waveforms is also used for forming a low resistance path.

Abstract: A semiconductor device arrangement and a method. One embodiment includes at least one power transistor and at least one gate resistor located between a gate of the power transistor and a connecting point in the drive circuit of the power transistor. The semiconductor device arrangement includes a switchable element between the connecting point and a source of the power transistor.

Abstract: An output stage interface circuit for interfacing with a data bus, comprising first and second rails for receiving respectively a high voltage and a low voltage from a power supply; a data output terminal; a first main switch element coupled between said terminal and the first rail and comprising a first main MOS device having a gate and an independently configurable back gate, and responsive to a first data control signal applied to the gate pulling the voltage on the data output terminal toward the first rail voltage; and a first control circuit responsive to the voltage on said terminal being pulled from a first state across a first voltage reference to a second state for coupling said back gate to said terminal and permitting coupling of the gate of said MOS device to said terminal, the first main MOS device presenting a high impedance on the terminal when its voltage is pulled to the second state.

Abstract: A thin film transistor circuit has a main thin film transistor (10), a control input (12) for controlling the operation of the main thin film transistor and a threshold adjustment capacitor (14) connected between the control input and the gate of the main thin film transistor. A charging circuit (16, 18) is used for charging the threshold adjustment capacitor to a desired threshold adjustment voltage. The circuit is used to affect a voltage shift to the voltage applied to the control input. This effectively implements a threshold voltage change by altering the relative voltages on the main transistor gate and the control input.

Abstract: A switch that selectively changes radio frequency signals includes at least three FETs, which are connected in series. The source electrodes or drain electrodes arranged at an intermediate stage have a width narrower than that of the source electrodes or the drain electrodes arranged at the initial and final stages. It is thus possible to lower the parasitic capacitance to ground at the intermediate stage and to thereby realize the switch having a high handling power.

Abstract: An FET switch comprising a single or parallel opposite polarity FETS is illustrated with wells that are driven from internal power rails. The internal power rails are logically coupled by other driving FET switches to, in one case, the higher of a positive power supply or signal level wherein the well of the PMOS FET switch will not allow the drain/source to well diode to be forward biased. In a second case, a second power rail is logically coupled to the lower of either and input signal or ground, wherein the well of the NMOS FET will not allow the drain/source to well diode to be forward biased.

Abstract: A fast acting charge pump is provided which is suitable for use in a locked loop circuit where very short duration first and second adjustment pulses are produced by a phase detector. The first complement of the second adjustment pulses are used to switch the output of the charge pump through respective pairs of switching and associated biasing transistors, while a complement of the first and second adjustment pulses are respectively capacitively coupled to interconnection nodes of the pairs of switching and biasing transistors.

Abstract: A level shift circuit in accordance with the present application seeks to meet the need of high voltage level shift signaling with minimum delay and power dissipation by using parasitic emulation, blocking of signaling during times of common mode noise, and mismatch filtering to enhance operation robustness to circuit mismatch and delay. A dv/dt sensing circuit is provided to detect any slew in offset between negative supply voltages and ground in a circuit. This detection is used to control a noise canceling circuit to ensure that noise that results from that offset is not propagated to the output of the level shift circuit. A parasitic emulator is preferably used to provide dv/dt sensing. The output of the parasitic emulator is used to activate a noise canceling circuit to prevent noise from reaching the output terminal of the level shift circuit.

Abstract: Provided is a digital circuit (30) that comprises: a switching circuit (31) having first transistors (32, 33) supplied with power supply potentials (VDD, VSS): correcting circuits (34, 36) connected between an input terminal (IN) inputted with an input signal and control terminals (gates) of the first transistors: capacitors (C2, C3) connected between the control terminals and the input terminal: diode-connected second transistors (35, 37) that are provided between nodes (N5, N6) between the capacitors and the control terminals and the power supply potentials and have the substantially same threshold voltage as the first transistors; and switches (SW2, SW3) connected in series with the second transistors.

Abstract: An interference modulator (Imod) incorporates anti-reflection coatings and/or micro-fabricated supplemental lighting sources. An efficient drive scheme is provided for matrix addressed arrays of IMods or other micromechanical devices. An improved color scheme provides greater flexibility. Electronic hardware can be field reconfigured to accommodate different display formats and/or application functions. An IMod's electromechanical behavior can be decoupled from its optical behavior. An improved actuation means is provided, some one of which may be hidden from view. An IMod or IMod array is fabricated and used in conjunction with a MEMS switch or switch array. An IMod can be used for optical switching and modulation. Some IMods incorporate 2-D and 3-D photonic structures. A variety of applications for the modulation of light are discussed. A MEMS manufacturing and packaging approach is provided based on a continuous web fed process.

Abstract: The present invention relates generally to a buffer of a drive Integrated Circuit (IC) and, more particularly, to a buffer of a drive IC for driving a spatial light modulator that can meet a desired dynamic slew rate characteristic by controlling current that affects a slew rate.

Abstract: A tracking switch includes an MOS switching transistor with a control terminal coupled to a CMOS inverter. The relative geometries of the transistors that make up the inverter are significantly imbalanced, resulting is substantially different drive strengths (i.e., substantially different on-resistances). The gate of the switching transistor exhibits parasitic capacitances between its current-handling terminals and its control terminal. When the switching transistor is on, these capacitances shunt a portion of the switched signal to a power-supply node, with the problem increasing with the frequency of the propagated signal. The geometry of the transistor used to turn on the switching transistor is selected to produce a high on-resistance, which introduces a high-impedance path from the control terminal of the switching transistor to ground when the switch is closed.

Abstract: An output stage interface circuit (1) comprises a main bipolar transistor (Q1) coupling a data output terminal (5) to a first rail (2) to which the positive of the power supply voltage (VDD) is applied, and a substrate diffusion isolated main NMOS transistor (MN1) coupling the data output terminal (5) to a second rail (3) which is held at ground. Control signals from a data control circuit (6) selectively operate the main bipolar transistor (Q1) and the main MOS transistor (MN1) for determining the logic high and low states of the data output terminal (5) during data output.

Abstract: An integrated memory arrangement based on resistive memory cells that can be changed over between a first state of high electrical resistance and a second state of low electrical resistance, each memory cell having an electrical additional capacitance that increases its capacitance, and to a production method.

Abstract: The present invention relates to an output driver circuit which exhibits a reduced variation in the slew rate of an output signal thereof, irrespective of a variation in temperature occurring during a process carried out by a semiconductor memory device, to which the output driver circuit is applied, or a variation in temperature caused by the operation characteristics of the semiconductor memory device, while exhibiting excellent operation characteristics even in a high-speed operation mode thereof.

Abstract: An input/output circuit in a receiving mode typically has disabled output buffers as well as other electrical components that provide significant receiver input capacities at high operating frequencies. A detection circuit detects the charging/discharging of the parasitic capacitance and operates a regulating circuit to compensate for the charging/discharging of the parasitic capacitance during rising/falling edges of an input signal, thereby correcting for impedance mismatch and reflection glitches.

Abstract: A discrete inductive-capacitive (LC) filter selects between at least two inductor banks to tune the LC filter. The filter receives an input signal that includes one or more bands of frequencies. A control signal selects a band of frequencies for processing. A first inductor bank is selected to filter a first band of frequencies, and a second inductor bank is selected to filter a second band of frequencies. A switch circuit couples the input signal to either the first inductor bank or the second inductor bank. The switch circuit selects the first inductor bank if the first band of frequencies is selected, and selects the second inductor bank if the second band of frequencies is selected. The switch circuit electrically isolates the switching of the input signal to the first and the second inductor banks, so as to enhance the Q factor of the LC filter. Circuit and techniques are disclosed to reduce parasitic capacitance in a capacitive bank that employs MOS transistors.

Abstract: In a level shifter, first and second PMOS transistors are connected in series between first and second power sources for supplying first high level and low level voltages, respectively, and a capacitor is formed between a contact point of the first and second transistors and the second transistor's gate. A third PMOS transistor is diode-connected and connected between the first and second transistors' gates. When a second low level voltage is input to the first transistor's gate, a second high level voltage is output to the contact point according to an on resistance ratio of the first and second transistors. When a first high level voltage is input to the first transistor's gate, the second transistor is bootstrapped according to the voltage charged to the capacitor so that a first low level voltage is substantially output to the contact point.

Abstract: In a level shifter, first and second PMOS transistors are connected in series between first and second power sources for supplying first high level and low level voltages, respectively, and a capacitor is formed between a contact point of the first and second transistors and the second transistor's gate. A third PMOS transistor is diode-connected and connected between the first and second transistors' gates. When a second low level voltage is input to the first transistor's gate, a second high level voltage is output to the contact point according to an on resistance ratio of the first and second transistors. When a first high level voltage is input to the first transistor's gate, the second transistor is bootstrapped according to the voltage charged to the capacitor so that a first low level voltage is substantially output to the contact point.

Abstract: A control circuit for a MEMS (Micro-Electro-Mechanical System) has a semiconductor switch which has a source, a drain and a gate, which is associated with a selected one of spatially arranged fixed and movable plates of a variable capacitor, and is arranged to selectively connect the selected one of the fixed and movable plates with a voltage source. A charge injection control circuit is associated with the semiconductor switch and attenuates current injection into the selected one of the fixed and movable plates of the capacitor.

Abstract: An integrated high-voltage switching circuit includes a switch having ON and OFF states and having a parasitic gate capacitance. The switch consists of a pair of DMOS transistors integrated back to back and having a shared gate terminal, the drains of the DMOS transistors being connected to the input and output terminals of the switch respectively. The switching circuit further includes a turn-on circuit comprising a PMOS transistor having its drain connected to the shared gate terminal of the switch via a first diode, having its source connected to a global switch gate bias voltage terminal from which the PMOS transistor draws current, and having its gate electrically coupled to a switch gate control terminal that receives a switch gate control voltage input.

Abstract: In electronic equipment, such as, for example, a personal computer printed circuit board, an arrangement for mitigating EMI, noise and other spurious signals at high frequencies. The arrangement includes a discrete capacitor coupled between an active pad and a reference pad. A conductor is coupled to the discrete capacitor and is configured to include a serpentine trace and a terminating tuning capacitance that are effectively series resonant at a predetermined frequency. In an exemplary embodiment, the serpentine trace comprises a number of substantially linear, mutually parallel segments that are joined by turns. The length and width of the serpentine trace, together with the number and spacing of linear segments, cooperates with the geometry of the tuning capacitance to determine the frequency of maximum attenuation of spurious signals.

Abstract: In a level shifter, first and second PMOS transistors are connected in series between first and second power sources for supplying first high level and low level voltages, respectively, and a capacitor is formed between a contact point of the first and second transistors and the second transistor's gate. A third PMOS transistor is diode-connected and connected between the first and second transistors' gates. When a second low level voltage is input to the first transistor's gate, a second high level voltage is output to the contact point according to an on resistance ratio of the first and second transistors. When a first high level voltage is input to the first transistor's gate, the second transistor is bootstrapped according to the voltage charged to the capacitor so that a first low level voltage is substantially output to the contact point.

Abstract: Phase locked loop charge pump comprising a drain node (A, B) and at least a cascode transistor (M4, M6) for limiting the variation of the voltage of said drain node, characterized in that an intermediate switch transistor (M3, M5) is placed between the drain node (A, B) and the cascode transistor (M4, M6).

Abstract: An integrated circuit is provided with at least two output drivers (4) without substrate contacts. The integrated circuit is further provided with at least a core with a Vssc contact (7, 9) and a periphery provided with at least one Vssq contact (8). A resistance (11) with a value of between 100 and 300 ohms lies between each Vssq contact (8) and the Vssc contact (7, 9). The value of the resistance (11) is preferably greater than 250 ohms in the case of output drivers which are not slew-rate controlled, and the value of the resistance (11) is preferably at most 250 ohms in the case of slew-rate controlled output drivers. The resistance (11) may be provided in the Vssq pad.

Abstract: A gate drive integrated circuit for switching power transistors using an external controller includes a gate driving capability and low quiescent current and allows use of a bootstrap supply technique for providing the logic supply voltage. The gate driver integrated circuit detects power transistor desaturation, protecting a desaturated transistor from transient over voltages by smoothly turning off the desaturated transistor via a soft shutdown sequence. A fault control circuit of the gate driver integrated circuit manages protection of supply under-voltage and transistor desaturation and is capable of communicating with a plurality of gate driver integrated circuits in a multi-phase system using a dedicated local network.

Abstract: In a semiconductor switch apparatus including an input terminal, an output terminal, an AC ground terminal, a DC ground terminal, at least one series MOS transistor connected between the input terminal and the output terminal, and at least one shunt MOS transistor connected between one of the input terminal and the output terminal and the AC ground terminal, the series MOS transistor is formed within a first region of a semiconductor layer on a silicon-on-insulator configuration surrounded by a first trench insulating layer, and the shunt MOS transistor is formed within a second region of the semiconductor layer surrounded by a second trench insulating layer.

Abstract: A compensating circuit for providing a compensating control signal to a regulating circuit is provided. The compensating circuit includes a multiplying circuit and a miller capacitor. The multiplying circuit may provide a predetermined multiplication factor to a miller current level based on a resistor ratio. The multiplying circuit may also provide a voltage gain stage before the miller capacitor. Both multiplying circuits enable the size of the miller capacitor to be reduced resulting in valuable printed circuit board space savings.

Abstract: A charge pump circuit is configured for charging of parasitic capacitances associated with charge pump capacitors in a manner that minimizes voltage ripple. The charge pump circuit is suitably configured with an independent charging circuit configured for supplying the current needed to charge the parasitic capacitances, rather than utilizing the reservoir capacitor to supply the needed current. The independent charging circuit can be implemented with various configurations of charge pump circuits, such as single phase or dual phase charge pumps, and/or doubler, tripler or inverter configurations. The independent charging circuit includes a parasitic charging capacitor or other voltage source configured with one or more switch devices configured to facilitate charging of the parasitics during any phases of operation of the charge pump circuit.

Abstract: A switch circuit having low charge dumping characteristics includes multiple parallel connected switching transistors and one or more associated cancellation transistors. The switching transistors perform basic switching functions within the switch circuit in response to a digital signal. During transitions of the digital signal, the switching transistors dump charge on an output node thereof due to parasitic capacitances within the devices. The cancellation transistor(s) dumps charge of an opposite polarity on the output node to cancel the charge dumped by the switching transistors. Two switching transistors are used for each cancellation transistor so that equal sized devices can be used throughout the switch circuit.

Abstract: An integrated semiconductor device is provided that has pads with less input signal attenuation. When J-FET (2) is driven by an input signal, the current passing through it varies. The parasitic capacitance (4) is charged or discharged by the input/output signal of the buffer circuit (6) following the varying current. Thus, since the voltage across the parasitic capacitance (3) varies in phase and at the same level, the parasitic capacitance (3) can be ignored. This effect allows attenuation of an input signal due to the parasitic capacitance (3) to be prevented.

Abstract: A high-voltage switching circuit comprising: a switch having ON and OFF states and having a parasitic gate capacitance and a control circuit for turning the switch on and off. The switch comprises a pair of DMOS FETs having a shared gate terminal, the sources of the DMOS FETs being connected to each other and the drains of the DMOS FETs being connected to the input and output terminals of the switch respectively, and biased at a bias voltage level. The control circuit comprises: a programming transistor having its drain connected to the shared gate terminal of the switch, its source connected to receive a programming voltage, and its gate connected to receive a programming transistor gate voltage; first circuitry for causing a first transition from a first level to a second (lower) level of the programming voltage; and second circuitry for causing a second transition from a first level to a second level of the programming transistor gate voltage.