Abstract: In some examples, a circuit includes a capacitor having a first terminal and a second terminal, the first terminal coupled to a voltage supply terminal of the circuit. The circuit also includes a transistor having a transistor gate, a transistor drain, and a transistor source, the transistor source coupled to ground and the transistor drain coupled to an input terminal of the circuit. The transistor is configured to conduct responsive to a gate signal received at the transistor gate, the gate signal based on a signal provided at the second terminal of the capacitor. The circuit also includes a Schmitt trigger having a Schmitt trigger input coupled to the transistor drain.

Abstract: A Schmitt trigger circuit includes a first and second set of transistors, a first and second feedback transistor, and a first and second circuit. The first set of transistors is connected between a first voltage supply and an output node. The first voltage supply has a first voltage. The second set of transistors is connected between the output node and a second voltage supply. The second voltage supply has a second voltage. The first feedback transistor is connected to the output node, a first node and a second node. The second feedback transistor is connected to the output node, a third node and a fourth node. The first circuit is coupled to and configured to supply the second supply voltage to the second node. The second circuit is coupled to and configured to supply the first supply voltage to the fourth node.

Abstract: An electric power system may include numerous devices electrically connected to numerous other devices. In some cases, it may be beneficial to quickly determine and resolve an electric power system topology. The present disclosure is directed to systems and methods for resolving an electric power system topology using bit pattern sequence compression. A multi-node device may be electrically coupled to one node per side. Each node may be associated with a bit value. The bit values may be compared to determine if the nodes are electrically coupled. This process may be recursively performed for all of the multi-node devices, until it is determined which devices are electrically coupled and which are electrically isolated.

Abstract: A system may include a switch, a gate driver, and a signal conditioner. The switch may couple to a load. The gate driver may generate one or more gating signals to control one or more operations of the switch. The signal conditioner may receive an input signal associated with the switch and generate a modification signal that may modify the one or more gating signals based on the input signal. The modified gating signal may be used to reduce an amplitude of a voltage transient received by the switch to below a voltage threshold.

Abstract: In a method of operating a circuit, at a beginning of a first edge of a driving signal, a first transistor is turned ON to pull, at a first changing rate, a voltage of the driving signal on the first edge from a first voltage toward a second voltage. Then, in response to the voltage of the driving signal on the first edge reaching a threshold voltage between the first voltage and the second voltage, the first transistor is turned OFF and an output circuit is caused to start a second edge of an output signal in response to the first edge of the driving signal. The second edge has a slew rate corresponding to a second changing rate of the voltage of the driving signal on the first edge from the threshold voltage toward the second voltage. The second changing rate is smaller than the first changing rate.

Abstract: A driver circuit for a low-inductance power module that has a connection and an output. The connection is connectable to the source contact of a power transistor and the output is connectable to the gate contact of the power transistor. The driver circuit is configured to produce, in a first operating mode, a first gate-source voltage for the gate contact of the power transistor and to provide the first gate-source voltage at the output of the driver circuit. The driver circuit is also configured to produce, in a second operating mode, during at least one preset minimum time span, a lower second gate-source voltage for the gate contact of the power transistor and to provide the second gate-source voltage at the output of the driver circuit.

Abstract: A sampling switch circuit, comprising: an input node, connected to receive an input voltage signal to be sampled; a sampling transistor comprising a gate terminal, a source terminal and a drain terminal, the source terminal connected to the input node; a potential divider circuit connected to the input node and a track-control node to provide a track-control voltage signal dependent on the input voltage signal at the track-control node; a hold-control node connected to receive a hold-control voltage signal; an output node connected to the drain terminal of the sampling transistor; and switching circuitry configured to connect the gate terminal of the sampling transistor to the track-control node or to the hold-control node in dependence upon a clock signal.

Abstract: A circuit for outputting a pulse signal includes: a pulse transformer configured to include a primary coil and a secondary coil; a switch section configured to switch a direction of application of current; a primary-side capacitor disposed on a path for primary-side current; a rectifying section configured to rectify secondary-side voltage and output the rectified voltage; a secondary-side capacitor configured to be charged with the rectified voltage and release charge; a transistor configured to be switched on and off according to voltage of the secondary-side capacitor; and a controller configured to control timings when the switch section switches the direction of application of the primary-side current. And the controller is configured to perform control to switch the direction of application of the primary-side current, when primary-side voltage oscillates and changes to an opposite polarity at a start timing of one switching period of the switch section.

Abstract: A ringing suppression circuit is provided at one or more nodes each having a communication circuit executing communication with another node by transmitting a differential signal through a pair of communication lines connected to the nodes. The circuit includes a suppression circuit and an operation mode controller: The suppression circuit is configured to execute a suppression operation for suppressing ringing in the differential signal. The operation mode controller is configured to set an operation mode of the suppression circuit to one of: a normal operation mode, which enables the suppression circuit to execute the suppression operation in response to detecting a change in a level of the differential signal, and a permanent off mode, which disables the suppression circuit to execute the suppression operation on a steady basis.

Abstract: A ringing suppression circuit is provided at one or more nodes each having a communication circuit executing communication with another node by transmitting a differential signal through a pair of communication lines connected to the nodes. The operation controller is configured to shift a mode of the suppressor to a normal-operation mode when the differential signal is transmitted through the pair of communication lines, and to shift the mode of the suppressor to a low-current operation mode when the differential signal is not transmitted through the pair of communication line. A current consumption of the suppressor is less in the low-current operation mode than the normal-operation mode. The suppressor and the operation controller are configured to receive permanent power from a DC power supply, and the communication circuit is configured to receive power from the DC power supply via a power supply switch.

Abstract: A ringing suppression circuit includes: a single line switching element, which is driven by a voltage, that is connected between a pair of signal lines; a controller that detects a change in a level of the differential signal and turns on the single line switching element to lower an impedance between the pair of signal lines; a period detector that detects a length of a suppressing period indicated by a setting signal, which is an input; and a suppressing period storage that stores the length of the suppressing period which is detected by the period detector. In addition, the pair of signal lines includes a high potential signal line and a low potential signal line. Moreover, the controller turns on the single line switching element for only the suppressing period having the length, which is stored in the suppressing period storage.

Abstract: A semiconductor device which controls output of a plurality of voltages is provided. A power supply control circuit which drives the semiconductor device includes a reference voltage generating circuit and a stabilized power supply circuit. The stabilized power supply circuit has a function of outputting a voltage input from a sample-and-hold circuit and amplified by the amplifier circuit. A control circuit has a function of setting an output voltage of the power supply control circuit. The sample-and-hold circuit in the stabilized power supply circuit includes a transistor whose on/off state is controlled. In such a configuration, a voltage set by the control circuit can be held and output.

Abstract: A MOS capacitor with improved linearity is disclosed. In an exemplary embodiment, an apparatus includes a main branch comprising a first signal path having a first capacitor pair connected in series with reversed polarities and a second signal path having a second capacitor pair connected in series with reversed polarities, the first and second signal paths connected in parallel. The apparatus also includes an auxiliary branch comprising at least one signal path having at least one capacitor pair connected in series with reversed polarities and connected in parallel with the main branch. In an exemplary embodiment, the capacitors are MOS capacitors.

Abstract: Provided are a control circuit for a switching regulator that can switch off a transistor that drives an inductor at high speed, an integrated circuit device, the switching regulator, an electronic device, and the like. A control circuit (100) includes a signal generation circuit (10) and an output circuit (20). The signal generation circuit (10) generates a control signal (SG) for a switching regulator. Upon receiving the control signal (SG), the output circuit (20) outputs a drive signal (GD) to a gate of an N-type transistor (30) that drives an inductor (40). The output circuit (20) outputs a voltage level lower than a source voltage of the N-type transistor (30) as an off-voltage level of the drive signal (GD) for switching off the N-type transistor (30).

Abstract: A semiconductor integrated circuit includes a first power supply line to which an input power supply voltage is to be applied, a second power supply line configured to supply a bias voltage to a load circuit, a MOS transistor having a source-drain current path connected between the first and second power supply lines, an NMOS transistor having a source-drain current path connected between the first and second power supply lines, and a control circuit configured to generate a first control signal that is supplied to a gate electrode of the PMOS transistor at a first point in time, and a second control signal that is boosted to have a voltage level higher than the input power supply voltage and then supplied to a gate electrode of the NMOS transistor at a second point in time point that is after the first point in time.

Abstract: Disclosed is a harmonic cancellation circuit for an RF switch branch having a first transistor with a first gate terminal and a first body terminal, a second transistor having a second gate terminal coupled to the first body terminal, and having a second body terminal coupled to the first gate terminal. Also included is a first resistor coupled between a first coupling node and the second body terminal, and a second resistor coupled between a second coupling node and the first body terminal, wherein the first transistor and second transistor are adapted to generate an inverse phase third harmonic signal relative to a third harmonic signal generated by the RF switch branch, such that the inverse phase third harmonic signal is output through the first resistor and the second resistor to the RF switch branch to reduce the third harmonic signal.

Abstract: A driver circuit for a semiconductor switching device includes a drive power source, a capacitor and four switches, which form a bridge circuit. The capacitor is provided between the four switches. In one cycle of application of a voltage to a gate of the semiconductor switching device to turn on the semiconductor switch, the first and the second switches, which are diagonal, are turned off and the third and the fourth switches, which are diagonal, are turned on to charge the capacitor. Then only the first switch is turned on to apply the voltage to the gate, and lastly only the second switch is turned on to discharge the capacitor thereby to apply a negative voltage to the gate of the semiconductor switching device.

Abstract: A shunt switch includes first switching elements provided in series between a first node and a second node. Second switching elements are provided in series between the nodes but not in series with the first switching elements. A distortion generation element connected in series with second switching elements generates a distortion which may be used for compensating for a signal distortion at the first node. A distortion changeover element is connected in parallel with the distortion generation element and is configured to have a conductance state that is opposite to the conductance state of the first switching elements, such that the changeover element is conducting when the first switching elements are in an non-conductive state and non-conducting when the first switching elements are in a conducting state.

Abstract: A driver may provide a transition of a switch between an on state and an off state in two stages. In the first stage, the voltage slew rate of the voltage at an output terminal of the switch may be controlled. In the second stage, the current gradient of the switch may be controlled. The transition between the first stage and the second stage may be made based on the value of the voltage at the output terminal of the switch.

Abstract: A system and method for reducing simultaneous switching output (SSO) noise. In one embodiment, power supply decoupling capacitances are distributed non-uniformly among a plurality of I/O circuits. Transitions between consecutive values on a data bus are either sent by the transmitter as requested at the input of the transmitter, or, in cases for which the noise of the requested transition is high, converted by an encoder to transitions having lower SSO noise. The converted transitions are decoded in a receiver, so that the data at the output of the receiver are the same as the data at the input to the transmitter.

Abstract: A system and method for reducing simultaneous switching output (SSO) noise. In one embodiment, power supply decoupling capacitances are distributed non-uniformly among a plurality of I/O circuits. Transitions between consecutive values on a data bus are either sent by the transmitter as requested at the input of the transmitter, or, in cases for which the noise of the requested transition is high, converted by an encoder to transitions having lower SSO noise. The converted transitions are decoded in a receiver, so that the data at the output of the receiver are the same as the data at the input to the transmitter.

Abstract: Ringing is securely reduced in a case where a Schottky barrier diode of a wide-gap semiconductor is applied to a power conversion circuit. A gate voltage increasing circuit 11a is included. In a period since a gate voltage of a semiconductor switching element in one of upper and lower arms starts being increased from a value in an off-state until the gate voltage reaches a value in an on-state, the gate voltage increasing circuit 11a is configured to make a gate voltage of the semiconductor switching element in the other one of the upper and lower arms change from a value in an off-state into a value larger than the value in the off-state and is configured to control the value larger than the value in the off-state for a predetermined period of time.

Abstract: An electronic device which includes a first stage having an input capacitance, a switch, a buffer and a second stage having an input sensitive to charge injection and/or voltage glitches. An input of the buffer and the input of the second stage are coupled together at a first node which is configured to be coupled to a voltage source for supplying a reference voltage to the input of the first stage having the input capacitance. In a first configuration of the switch, the switch is arranged to either connect the input of the first stage to the first node and to disconnect the input of the first stage from an output of the buffer. In a second configuration of the switch, to connect the input of the first stage to the output of the buffer and to disconnect the input of the first stage from the first node.

Abstract: A circuit includes a diode circuit and a deactivation circuit. The diode circuit includes a first terminal, a second terminal, and a plurality of diodes coupled in parallel between the first terminal and the second terminal. The diode circuit is configured to be forward biased in an on-time and reverse biased in an off-time. The deactivation circuit is configured to switch a first group of the diodes into a deactivation state at a time instant before the end of the on-time, the first group of diodes including one or more but less than all of the diodes included in the diode circuit.

Abstract: In the device, a pair of transistors includes first and second transistors connected in parallel between a power-supply-line and a power-supply or between a ground-line and a ground-potential. A third transistor is connected between the power-supply-line and the power-supply or between the ground-line and the ground-potential. First to third nodes are gate nodes of the first to third transistors. A first buffer outputs a first control-signal for controlling the first transistor. A second buffer is connected between the first node and the second and third nodes to receive the first control-signal and transmit a second control-signal for controlling the second and third transistors to the second and third nodes in parallel. When power-supplying starts, the second control signal drives the second and third transistors to the conductive-state after the first control-signal controls the first transistor to be driven in an intermediate-state between the conductive-state and a shutoff-state.

Abstract: A data signal is transmitted from a first circuit to a second circuit, with noise and/or jitter added to the data signal by supply noise in the power distribution network in the first circuit and/or a second circuit being effectively canceled out by adjustment of the reference voltage and/or the phase of the sampling clock used for sampling of the data signal in a manner that effectively mimics such noise and/or jitter added to the data signal. The second circuit uses a filter that has the impedance profile and/or the jitter profile of such power distribution network. The bus weight and/or the number of switching bits in the data pattern transmitted from the first circuit to the second circuit is applied to the filter to determine the adjustment to be made to the reference voltage or the phase of the sampling clock.

Abstract: A test apparatus that tests a device under test, including a power supply section that supplies the device under test with power, a comparing section that detects a characteristic value indicating a state of the device under test and compares the characteristic value to a predetermined threshold value, a cutoff section that cuts off the power supplied from the power supply section to the device under test, based on a result of the comparison by the comparing section, and a control section that changes at least one of the threshold value of the comparing section and a detection timing at which the characteristic value is detected.

Abstract: According to one embodiment, a semiconductor device has a transistor comprising a source electrode, a drain electrode, and a gate electrode, a diode and a switch element connected in series between the gate and source electrodes of the transistor, and a control circuit configured to supply a control signal for switching the switch element. The control circuit has a predetermined time constant and is configured to supply the control signal to the switch element if a pulse signal having a voltage that is equal to or higher than a predetermined voltage is supplied to the gate electrode of the transistor.

Abstract: In one embodiment, a power switch driving circuit can include: (i) an upper switch having a first power terminal coupled to a voltage source, and a second power terminal coupled to a driving signal; (ii) a lower switch having a first power terminal coupled to the driving signal, and a second power terminal coupled to a first voltage level, where the first voltage level is higher than a first ground potential; (iii) an upper switch driving sub circuit configured to receive a control signal, and to drive the upper switch in response thereto; and (iii) a lower switch driving sub circuit configured to receive the control signal, and to drive the lower switch in response thereto, where the upper and lower switch driving sub circuits are coupled to a second ground potential.

Abstract: A switch controller is provided that uses one or more capacitors to generate a slow turn on/slow turn off switch control signals to suppress audible switching noise in an audio switch. In some embodiments, an analog inverter and a capacitor are used to generate the switch control signals, while in other embodiments two capacitors are used to generate the switch control signals. To conserve power between switching states, routing logic is provided that ties the switch control signals to respective voltage rails and disables selected portions of the switch controller.

Abstract: Disclosed herein is a gate driver having a function of preventing shoot-through current. The gate driver having a function of preventing shoot-through current includes: a first power switch sourcing current according to voltage applied by a voltage source; a second power switch connected with the first power switch in series and sinking current according to voltage applied by the voltage source; and a shoot-through current preventing circuit preventing the occurrence of shoot-through current in first and second power switches at the time of driving of the first and second power switches. According to the present invention, the shoot-through current preventing circuit configured of the plurality of PMOSs and NMOSs can prevent the shoot-through current from occurring in the power transistor of the output terminal at the time of the driving of the gate driver, thereby preventing the unnecessary power consumption and the occurrence of ground noise.

Abstract: A semiconductor device includes: a first power line to supply a first voltage to a plurality of internal circuits; a second power line to supply the first voltage to the plurality of internal circuits; a first switch provided between said first power line and each of the plurality of internal circuits; a second switch provided between said second power line and each of the plurality of internal circuits; and a control circuit to control the first switch of a second internal circuit included in the plurality of the internal circuits based on the amounts of noise and voltage drop at power-on in a first circuit included in the plurality of internal circuits.

Abstract: A method and system avoid ringing at an external power transistor subsequent to switching OFF the external power transistor. A driver circuit generates a drive signal for switching the external power transistor between OFF-state and ON-state. The driver circuit comprises a drive signal generation unit configured to generate a high drive signal triggering the external power transistor to switch to ON-state, wherein an output resistance of the driver circuit is adjustable, an oscillation detection unit to detect a degree of oscillation on the drive signal, and a resistance control unit to adjust the output resistance of the driver circuit based on the degree of oscillation on the drive signal.

Abstract: In one embodiment, an apparatus includes a power switch to provide a local power voltage at least one gated circuit based on a control signal. The apparatus also includes a delay sensor to provide a delay substantially equivalent to a processing delay of the at least one gated circuit. The apparatus also includes a phase detector to provide the control signal based at least in part on the delay.

Abstract: This disclosure provides a gate driver circuit in a display. The gate driver circuit includes shift registers configured for receiving clock and start signals and generating a gate signal to drive a row of the pixels, arranged at intersections of the gate lines and the data lines on a panel, each register comprising: a control unit having a clock input, a first voltage input, a second voltage input, and a first output; and a first output unit having a first pull-down TFT electrically connected to one of the first outputs and a gate-driving terminal configured for providing the gate signal; wherein one of the clock signals at the clock input is provided to the first output unit; and a first control signal's period at the first output is longer than the clock signal's period at the clock input and shorter than the period of a frame.

Abstract: AFE circuitry handles both voltage and current input signals. In one embodiment, both a voltage path and a current path are provided from the input. Switching circuitry selects one of the paths. A switch also turns on or off a current-to-voltage conversion circuit used to convert a current input into a voltage. In one embodiment, noise is significantly reduced by using a dedicated ground pin or terminal for the negative reference of a differential circuit. This applies the same external board noise, which is on the input signal, to the negative reference, so the noise is canceled in the differential signal. In one embodiment, temperature compensation is provided via an IPTAT circuit which is used to shift the voltage up in order to balance the decrease in DC voltage with increasing temperature.

Abstract: Radio-frequency (RF) switch circuits having switchable transistor coupling for improved switching performance. An RF switch system includes at least one field-effect transistor (FET) disposed between first and second nodes, each FET having a gate and body. A switchable resistive coupling circuit is connected to each of the respective gates. A switchable resistive grounding circuit is connected to each of the respective bodies.

Abstract: A data signal is transmitted from a first circuit to a second circuit, with noise and/or jitter added to the data signal by supply noise in the power distribution network in the first circuit and/or a second circuit being effectively canceled out by adjustment of the reference voltage and/or the phase of the sampling clock used for sampling of the data signal in a manner that effectively mimics such noise and/or jitter added to the data signal. The second circuit uses a filter that has the impedance profile and/or the jitter profile of such power distribution network. The bus weight and/or the number of switching bits in the data pattern transmitted from the first circuit to the second circuit is applied to the filter to determine the adjustment to be made to the reference voltage or the phase of the sampling clock.

Abstract: A method of protection from noise of a digital signal generated by a comparator, including the steps of generating an output signal that switches from a first logic state to a second logic state at a first switching of logic state of the digital signal; detecting a change from the first logic state to the second logic state of the output signal; and inhibiting further switchings of the output signal for a first time interval after the change from the first logic state to the second logic state.

Abstract: The invention provides an electronic device for reducing simultaneous switching noise (SSN). The electronic device includes: a driver, driving an external device according to an input signal, and including: an input end, receiving the input signal; a positive output end, coupled to an external capacitor of the external device; and a negative output end, coupled to a variable capacitor; and a loading calibration circuit, generating an adjusting signal to adjust a first capacitance of the variable capacitor so as to make the first capacitance approximately equal to a second capacitance of the external capacitor.

Abstract: A gate driving circuit for driving a power semiconductor element can include a MSINK that is an n-channel metal-oxide silicon field-effect transistor (MOSFET) with a low resistance value for rapidly drawing out the charges accumulated on the gate of an insulated gate bipolar transistor (IGBT), and a MSOFT that is an n-channel MOSFET with a high resistance value for slowly drawing out the charges. By shifting the time for turning ON of these MOSFETs, soft interruption can be performed rapidly and surely when overcurrent or short circuit current flows in the IGBT. Therefore, device breakdown is minimized or avoided and noise generation is suppressed.

Abstract: The present invention provides a channel estimation apparatus in which channel estimation may be made higher than heretofore in accuracy and may be used for calculating the weight for an equalization filter to achieve an optimum equalizing performance. A subcarrier copying unit 20 copies K items of end-side subcarriers, using the channel estimation obtained by a correlation processing unit 14 and K which is a subcarrier copy number. An IDFT unit 15 transforms the channel estimation obtained at the subcarrier copying unit 20 into the time domain channel response. A noise path removing unit 16 removes noise paths from the channel response output from the IDFT unit 15. A DFT unit 17 performs DFT of the channel response, from which the noise paths are removed by the noise path removing unit 16, to output a noise-suppressed frequency domain channel estimation value. A weight calculation unit 5 inputs the frequency domain channel estimation value output from the DFT unit 17 to calculate an equalizing weight.

Abstract: Various schemes for reducing effects of interference within communication systems are disclosed. A transmitter transmits a signal in a first time interval and a scrambled version of the signal in a second time interval, which does not overlap with the first time interval. A receiver receives a composite signal including a signal transmitted from the desired transmitter as well as signals from interferers in the first or the second time interval. The receiver determines a dominant interferer and obtains knowledge of signal scrambling done by the interferer as well as the desired transmitter by sensing an identification associated with the interferer or the desired transmitter. This knowledge is employed to determine coefficients for combining the received composite signals received in the first and the second time interval in order to recover the desired signal in a manner that maximizes the SNR associated with the desired signal or completely cancels the dominant interference.

Abstract: A load driving circuit in which the off-time Toff and the fall time Tf can be improved in turn-off operation of the N-channel type MOSFET used as a high side switch. The load driving circuit uses an N-channel type power MOSFET as a high side switch connected between a power supply and a load, including a comparator circuit for comparing a gate voltage of the power MOSFET with a power-supply voltage; and a shut-off circuit for discharging the gate terminal of the power MOSFET in turn-off operation of the power MOSFET, the rate of discharging the gate terminal of the power MOSFET performed with the shut-off circuit being set such that the discharge rate provided if the gate voltage Vg is lower than the power-supply voltage Vp is slower than the rate of discharging the same provided if the gate voltage Vg is higher than the power-supply voltage Vp.

Abstract: A ringing suppression circuit for a communication circuit that performs communication through a transmission line includes a high side switch connected between a high potential reference point and a high side line of the transmission line, a low side switch connected between a low potential reference point and a low side line of the transmission line, and a ringing suppression section. The ringing suppression section turns on the high side switch based on a difference between a potential of the high side line and a potential applied to a control terminal of the high side switch. The ringing suppression section turns on the low side switch based on a difference between a potential of the low side line and a potential applied to a control terminal of the low side switch.

Abstract: At least one exemplary embodiment is directed to a semiconductor power switching device including a ctrl switch, a sync switch, where a resistor is electrically connected between the ctrl switch and the sync switch.

Abstract: A controller and a circuit work together to enable a selective and dynamic adjustment to correct phase and gain imbalances in quadrature signal paths of a receiver. Under select conditions, it has been determined that statistical estimates of gain and phase imbalance can be applied to adjust signals in the quadrature signal paths of a receiver. The controller validates the select conditions before updating the estimate of the gain imbalance and the estimate of the phase imbalance. The controller directs a compensator under select operating conditions such that validated dynamic estimates of the gain and phase imbalance or calibration data is applied to the quadrature signal paths. The controller disables the compensator and enables an estimator and a calculator when estimates are unavailable for the present operating conditions.

Abstract: In a first pair of stacked PMOS devices comprising a first PMOS device and a second PMOS device, a first pumping circuit is coupled between a gate of the first PMOS device and a P pre-driver signal. In a second pair of stacked NMOS devices comprising a first NMOS device and a second NMOS device, a second pumping circuit is coupled between a gate of the first NMOS device and an N pre-driver signal. The pumping circuits recognizing the transition from the pre-driver signals provide a voltage to the gate of the first PMOS device and of the first NMOS device so that the first PMOS and NMOS devices are turned on better. As a result, their voltage Vds peaks are suppressed to a safe level; the devices avoid hot-carrier degradations; and their lifetimes are prolonged.

Abstract: The method is for detecting the eventual presence of an interferer that is adapted to interfere with a wireless device. The wireless device is provided with at least one receiving chain including an analog to digital conversion stage. The method includes receiving on the receiving chain an incident signal, and delivering to the ADC stage an analog signal from the incident signal. The method further includes elaborating or determining a binary information from a binary signal delivered by the ADC stage and representative of the level of the analog signal, analyzing a temporal evolution of the binary information and detecting the presence of the interferer from the analysis.

Abstract: According to one embodiment, a first switch transistor and a second switch transistor convert an input current to a first current and a second current by performing a switching operation on the basis of differential input voltages, respectively. An input current source supplies the input current to the first and second switch transistors. A noise current generating circuit generates a dummy current to simulate a noise current flowing through the input current source. A third switch transistor and a fourth switch transistor convert the dummy current to a third current and a fourth current by performing a switching operation on the basis of differential input voltages and negatively superimposes the third current and the fourth current on the first and second currents, respectively.