Abstract: An industrial process field device includes an active component, a switch, a switch monitor, and a controller. The active component may be a sensor configured to sense a process parameter, or a control device configured to control a process of the industrial process. The switch is electrically coupled to first and second terminals. The switch monitor is configured to detect an open or closed state of the switch, and generate a first state output, a second state output, or a chattering state output. An anti-chatter circuit outputs a chatter stabilized state output based on the chattering state output. The controller is configured to set the switch in the open or closed state, and generate a notification based on any one of the first and second state outputs and the chatter stabilized state output that indicates at least one of the current state and a condition of the switch.

Abstract: A power management system is provided. The power management system includes a first voltage regulator having an input coupled to a first voltage supply terminal and an output. The first voltage regulator is configured to provide an operating voltage at the output. A second voltage regulator has an input coupled to the output of the first voltage regulator. The second voltage regulator is configured to provide at an output a retention voltage based on a control signal. A control circuit is coupled to the second voltage regulator and configured to provide the control signal to the second voltage regulator.

Abstract: A method for parameterising the responsiveness of an electronic device observed after the electronic device receives a command emitted by a nearby testing system including a plurality of control buttons, includes establishing a usage profile of the nearby testing system by an operation to analyze operations of pressing the control buttons of the nearby testing system; and adapting a parameter of the responsiveness of the electronic device in accordance with the established usage profile.

Abstract: The present invention discloses a CMOS differential logic circuit. The CMOS differential logic circuit includes a precharge differential logic unit, which is precharged to a source voltage in response to a clock signal and is configured to output voltage having an increased load-driving ability using a boosting voltage; a voltage-boosting unit, which is pulled down by a ground voltage in response to the clock signal and is configured to boost the pulled-down voltage using capacitive coupling and output the boosting voltage; and a switching unit, which is configured to couple the precharge differential logic unit and the voltage-boosting unit in response to the clock signal. The propagation delay of a signal from the input terminal to the output terminal of a circuit in a low-source-voltage environment can be reduced, and the operating speed of the circuit and energy efficiency of the operation thereof can be improved.

Abstract: A circuit and method for debouncing an electrical signal are disclosed. A representative embodiment of the present invention may be set to remove (i.e., filter) noise or glitches in the low and high portions of an input signal, where the width of the noise or glitches while in the high or low state may be set using a programming interface. The filtering is done in a manner that results in a clean, debounced output signal having a low portion approximately equal to the low portion of the input signal, and a high portion approximately equal to the high portion of the input signal. Noise or glitches of less than programmable high or low glitch widths are filtered from the input signal and do not appear in the output signal.

Abstract: A method and apparatus for a multiple lane transmission system that provides a fixed, low-latency mode of operation with reduced lane-lane skew while process, voltage, and temperature (PVT) variation, as well as other sources of variation, occur over time. Multiplexing techniques are utilized within each transmission lane to allow programmably adaptive use of phase alignment circuitry for various modes of operation. As a result, power consumption and semiconductor die area are reduced because multiple copies of phase alignment circuitry within each transmission lane are not required. Also, injection of additional jitter on the serial outputs due to continuous operation of phase alignment circuitry is prevented. Rather, multiplexers within the phase alignment circuitry selectively adapt the timing architecture to that required by the selected mode of operation.

Abstract: One embodiment is a gate drive circuitry for switching a semiconductor device having a non-isolated input, the gate drive circuitry having a first circuitry configured to turn-on the semiconductor device by imposing a current on a gate of the semiconductor device so as to forward bias an inherent parasitic diode of the semiconductor device. There is a second circuitry configured to turn-off the semiconductor device by imposing a current on the gate of the semiconductor device so as to reverse bias the parasitic diode of the semiconductor device wherein the first circuitry and the second circuitry are coupled to the semiconductor device respectively through a first switch and a second switch.

Abstract: A switch de-bouncing device includes a majority counter that counts samples generated by a sampler sampling a switch output where a counter value is incremented for each sample indicating a first switch state and decremented for each sample indicating a second switch state of the switch. A controller determines that the switch is in the first switch state when the counter value is above a first state threshold and is in the second switch state when the counter value is below a second state threshold.

Abstract: A circuit for debouncing a signal from a switch or other input. The invention provides an arrangement which receives an input signal and which monitors the input to provide an output which switches after a predetermined time from the input signal changing from one state to another. However, the output changes back to its original state in a much shorter time if said input changes back to its original state.

Abstract: A mixer is disclosed that includes first and second transconductance modules that, in one embodiment, includes MOSFETs configured to receive a plurality of signals that are to be mixed and a selectively coupled auxiliary current source to inject an auxiliary current into the second transconductance module approximately at or near a zero-crossing point in order to reduce flicker noise and other noise introduced into an output signal during switching. Accordingly, as a first transconductance module approaches a zero-crossing, auxiliary current is injected to reduce the current produced therefrom thereby reducing flicker noise. In a differential mixer, the amount of current produced from a transistor pair to which the signal cycle is being switched is also reduced thereby reducing noise from the transistor pair that is turning on for the next portion of a signal cycle.

Abstract: An object of the present invention is to provide a chattering preventing circuit, a waveform shaping circuit, and a motor drive control circuit including the chattering preventing circuit or the waveform shaping circuit, to provide an FG signal free from noise caused by chattering, without using a hysteresis comparator.

Abstract: A mixer is disclosed that includes first and second transconductance modules that, in one embodiment, includes MOSFETs configured to receive a plurality of signals that are to be mixed and a selectively coupled auxiliary current source to inject an auxiliary current into the second transconductance module approximately at or near a zero-crossing point in order to reduce flicker noise and other noise introduced into an output signal during switching. Accordingly, as a first transconductance module approaches a zero-crossing, auxiliary current is injected to reduce the current produced therefrom thereby reducing flicker noise. In a differential mixer, the amount of current produced from a transistor pair to which the signal cycle is being switched is also reduced thereby reducing noise from the transistor pair that is turning on for the next portion of a signal cycle.

Abstract: A circuit for reducing the noise associated with a clock signal for a flip-flop based circuit has been developed. The circuit includes a charge control portion that stores charge at a pre-determined time of the clock cycle and a dump control portion that releases the stored current also at a pre-determined time of the clock cycle. The charge is released onto the power grid of the system served by the clock signal.

Abstract: A method of reducing the noise of a clock signal distribution system for a flip-flop based circuit has been develop. The method first inputs a synchronized clock signal into a noise reduction circuit. The noise reduction circuit then begins to store charge upon receipt of the clock signal. Finally, the noise reduction circuit dumps the charge onto the system power grid at an appropriate time in conjunction with the clock signal.