Abstract: The power device is formed by a D-mode HEMT and by a MOSFET in cascade to each other and integrated in a chip having a base body and a heterostructure layer on the base body. The D-mode HEMT includes a channel area formed in the heterostructure layer; the MOSFET includes a first and a second conduction region formed in the base body, and an insulated-gate region formed in the heterostructure layer, laterally and electrically insulated from the D-mode HEMT. A first metal region extends through the heterostructure layer, laterally to the channel area and in electrical contact with the channel area and the first conduction region.

Abstract: A drive circuit capable of inhibiting a drop of a voltage of a drive signal is provided. A drive circuit includes: a drive signal output circuit configured to output a pulse signal input to a gate terminal of a first field effect transistor driving a device; a switching circuit having a switching element that is connected between the gate terminal and the signal output terminal and configured to switch a conduction state between the gate terminal and output terminal; a delay circuit configured to delay an input of the drive signal to the gate terminal by switching a state of the switching element between an on state and an off state; and a reverse flow suppressing unit configured to suppress a reverse flow of a current from the static capacitance to the drive signal output circuit.

Abstract: A wideband low power active isolator that may operate with a low voltage supply and provide improved linearity and insertion loss is described. The active isolator includes parallel connected common gate amplifier and common drain amplifier that are implemented using active transistors. A RF choke configured to suppress RF signal is coupled between input to the common gate amplifier and the ground such that the common gate amplifier also functions as a current source biasing the common drain amplifier.

Abstract: Some embodiments relate to a two transistor band gap reference circuit. A first transistor includes a first source, a first drain, a first body region separating the first source from the first drain, and a first gate. The first drain and first gate are coupled to a DC supply terminal. The second transistor includes a second source, a second drain, a second body region separating the second source from the second drain, and a second gate. The second gate is coupled to the DC supply terminal, and the second drain is coupled to the first source. Body bias circuitry is configured to apply a body bias voltage to at least one of the first and second body regions. Other embodiments relate to FinFET devices.

Abstract: Several embodiments of an envelope tracking active circulator is disclosed with a method to cascade them. In an active transistor based circulator (active circulator), gate (base) and drain (collector) bias voltage can be adjusted by RF or microwave input envelop signal. This is called envelop tracking active circulator. In this concept, input RF signal is detected by detection circuit, such as detection diode or coupler and converted into low frequency envelop signal by the proper filtering circuitry. The generated envelop signal controls the supply voltage of the drain and gate with the proper function of the envelop signal to improve active circulator insertion loss, isolation and power handling capability. This concept can be applied to any type of solid-state FET (Field effect transistor) transistor based active circulator, as long as they have bias dependent trans-conductance and capacitances inside.

Abstract: A thermal process chamber having a lamp driver circuit that includes two transistors and two diodes is described. The thermal process chamber includes a plurality of halogen lamps, the lamp driver, a temperature sensor that measures wafer temperature, a temperature controller connected to the temperature sensor and to the lamp driver, the temperature controller providing control signals to the lamp driver that are functions of the wafer temperature and a desired temperature. The lamp driver includes two transistors that are controlled by the control signals so that the power factor of the power supplied to the plurality of halogen lamps is in the range of 0.9 to 1.

Abstract: To provide a thermal processing apparatus where a projection area perpendicular to the axis of a sealing structure and attachment structure of heat radiation heater is decreased and a chamber volume is decreased. The apparatus has a chamber for accommodating a workpiece of a thermal processing object, the chamber having a partition wall for partitioning inside from outside of the chamber, a heat radiation heater disposed penetrating the partition wall, wherein the heater has a ring seal arranged on an outer peripheral surface of the extension section, and hermetically sealing the chamber, and a heat blocking plate arranged between the heat radiation unit and the ring seal in the axial direction of the glass tube, for blocking heat radiated from the heat radiation unit to the ring seal, the heat blocking plate having an inner peripheral surface fitting along the extension section.

Abstract: An active matrix panel includes a gate line connected to control electrodes of a plurality of transistors; and a drive circuit supplying the gate line with a conducting voltage and a non-conducting voltage. The drive circuit includes a shift register including a plurality of shift register unit circuits connected to each other, and a demultiplexer including a plurality of demultiplexer unit circuits into which output signals of the shift register unit circuits are input. The demultiplexer unit circuit includes a first transistor for supplying the gate line with the conducting voltage, and a second transistor for supplying the gate line with the non-conducting voltage. The first transistor is changed from a non-conducting state into a conducting state when the second transistor is in the conducting state.

Abstract: A method of electrically coupling a first node and a second node of a switch cell includes biasing the second node and a bias node of the switch cell at a direct current (DC) voltage level of a second voltage level greater than a first voltage level. A first switch unit coupled between the first node and the second node is tuned on by a first control signal having a third voltage level. The third voltage level being greater than the first voltage level, and a difference between the third voltage level and the first voltage level is about twice a difference between the second voltage level and the first voltage level. Also, a second switch unit coupled between the second node and the bias node is turned off by a second control signal having the first voltage level.

Abstract: A method can be used for driving a switch circuit. The switch circuit includes a first transistor device and a second transistor device. Both the first transistor device and the second transistor device have a load path and a control terminal. The load paths of the first transistor device and the second transistor device are connected in series. The control terminal of the first transistor device is configured to receive a first drive signal and the control terminal of the second transistor device is configured to receive a second drive signal. One of an on-level switching on the first transistor device or an off-level switching off the first transistor device of the first drive signal is selected and one of a first signal level and a second signal level of the second drive signal is selected.

Abstract: A semiconductor integrated circuit includes a P-type MOS transistor and two or more N-type MOS transistors connected together in series between a first and a second power supply, an input terminal connected to a gate terminal of the P-type MOS transistor and gate terminals of the two or more N-type MOS transistors, an output terminal which is a connection node between the P-type MOS transistor and one of the two or more N-type MOS transistors connected to the P-type MOS transistor, and one or more capacitors connected to the output terminal. The drive capability of the P-type MOS transistor is higher than the overall drive capability of the two or more N-type MOS transistors connected together in series. Therefore, a semiconductor integrated circuit is provided in which fluctuations in the delay time of a delay circuit caused by variations in transistor characteristics can be reduced.

Abstract: Various methods and structures related to tristate multiplexer circuits are disclosed. An embodiment provides a selection circuit in which selectively enabled input circuits are coupled to an output circuit through an output enable circuit such that a selected one of the selectively enabled input circuits is operable to provide a pathway for charging and discharging currents used to charge and discharge an output circuit transistor gate. This and other detailed embodiments are described more fully in the disclosure.

Abstract: A drive circuit includes a switching transistor having a design maximum voltage V2 and a cascode transistor having a design maximum voltage V1, wherein the cascode transistor is source-drain coupled in series with the switching transistor. The circuit further includes a current source coupled between an intermediate voltage node and a gate of the cascode transistor. If the drive circuit is a low side driver, the intermediate voltage node receives an intermediate voltage Vmed set below a high supply voltage Vhigh and that meets the following conditions: a) Vmed<=V2 and b) Vhigh?Vmed<=V1. If the drive circuit is a high side driver, the intermediate voltage node receives an intermediate voltage Vmed set below the high supply voltage and that mees the following conditions: a) Vmed<=V1 and b) Vhigh?Vmed<=V2. The circuit may be configured as a push pull driver by coupling a high side driver and low side driver in series.

Abstract: A semiconductor device includes a termination driver for driving a data line with a predetermined termination level by using an external power supply voltage and a drive current controller for controlling a drive current flowing into the data line from the termination driver in response to a voltage level of the external power supply voltage.

Abstract: There is provided a high frequency switch capable of suppressing deterioration in distortion characteristics. The high frequency switch includes: a common port outputting a transmission signal to an antenna; a plurality of transmission ports each having the transmission signal input thereto; and a plurality of switching units each connected between the plurality of transmission ports and the common port to conduct or block the transmission signal from each of the transmission ports to the common port, wherein each of the switching units has one or more metal oxide semiconductor field effect transistors (MOSFETs) formed on a silicon substrate, and a capacitor connected between a body terminal of a MOSFET connected to the common port among the MOSFETs and a terminal of the MOSFET connected to the common port.

Abstract: In a light emitting device, luminance irregularities caused by fluctuation in threshold of TFTs for supplying a current to EL elements among pixels hinder the light emitting device from improving the image quality. A voltage equal to the threshold of a TFT 110 is held in capacitor means 111 in advance. When a video signal is inputted from a source signal line, the voltage held in the capacitor means is added to the signal, which is then applied to a gate electrode of the TFT 110. Even when threshold is fluctuated among pixels, each threshold is held in the capacitor means 111 of each pixel, and therefore, influence of the threshold fluctuation can be removed. Since the threshold is stored in the capacitor means 111 alone and the voltage between two electrodes is not changed while a video signal is written, fluctuation in capacitance value has no influence.

Abstract: A driver circuit includes first and second switching elements connected in series to two ends of an electric voltage source. A driven load having a capacity is connected to a connection line connecting the first and second switching elements to each other. An inverter inverts a control signal into an inverted control signal applied to the second switching element. When the first switching element is turned on by the control signal and the second switching element is turned off by the inverted control signal, a drive voltage is applied from one of the two ends of the electric voltage source to the driven load. When the first switching element is turned off by the control signal and the second switching element is turned on by the inverted control signal, an electric charge of the driven load is discharged to another of the two ends of the electric voltage source.

Abstract: A source follower includes first through third switches, first and second transistors, and a first capacitor. The first switch is used to determine whether or not to couple the source of the first transistor with an input signal. The second switch is used to determine whether or not to couple a gate and a drain of the first transistor with a first voltage. A first end of the first capacitor is coupled with a first control signal, and a second end of the first capacitor is coupled to the drain of the first transistor and a gate of the second transistor. The third switch is used to determine whether to or not couple a drain of the second transistor with the first voltage, and a source of the second transistor serves as an output of the source follower.

Abstract: A compensated buffer circuit operative in one of at least a first mode and a second mode includes a plurality of output blocks and a plurality of predrivers, each of the predrivers having an output connected to an input of a corresponding one of the output blocks. Respective outputs of the output blocks are connected together and form an output of the buffer circuit. The output blocks are arranged in a sequence and are binary weighted such that a drive strength of a given one of the output blocks is about twice as large as a drive strength of an output block immediately preceding the given output block. Each of the predrivers selectively enables the corresponding output block connected thereto as a function of a control signal supplied to the predriver for compensating the buffer circuit for PVT variations to which the buffer circuit may be subjected.

Abstract: A high performance, set associative, cache memory tag multiplexer provides wide output pulse width without impacting hold time by separating the evaluation and restore paths and using a wider clock in the restore path than in the evaluation path. A clock controls the evaluation of the input signals. Its leading edge (i.e., rising edge) turns on NR to allow evaluation, its trailing edge (falling edge) turns off NR to stop evaluation. At this point, when NR is shut off, the inputs can start changing to set up for the next cycle. Hence the hold time of the input is determined by the clock trailing edge.

Abstract: In accordance with the principles of the invention, an integrated circuit comprises a substrate having a first FET formed on the substrate. The first FET has a first terminal coupleable to a load, a second terminal and a control terminal. The second terminal is connected to the substrate. The substrate comprises a parasitic body diode coupled between the first terminal and the substrate. The body diode is disposed such that it becomes conductive when a reverse voltage across the FET first terminal and the substrate is at least a first diode forward voltage. A voltage detector is formed on the substrate. The voltage detector has a first input coupled to the FET first terminal, a second input coupled to the substrate, and an output coupled to the FET control terminal. The voltage detector is responsive to a reverse voltage level at the FET first terminal that is less than the first diode forward voltage to turn the FET on for the duration of a reverse voltage having at least said reverse voltage level.

Abstract: A high performance, set associative, cache memory tag multiplexer provides wide output pulse width without impacting hold time by separating the evaluation and restore paths and using a wider clock in the restore path than in the evaluation path. A clock controls the evaluation of the input signals. Its leading edge (i.e., rising edge) turns on NR to allow evaluation, its trailing edge (falling edge) turns off NR to stop evaluation. At this point, when NR is shut off, the inputs can start changing to set up for the next cycle. Hence the hold time of the input is determined by the clock trailing edge.

Abstract: A signal conversion circuit for converting an inputted differential signal into a single-ended signal comprises a differential amplifier circuit for amplifying the differential signal, and generating a first non-inverted signal and a first inverted signal being inverted the first non-inverted signal, a first inverter for generating a second non-inverted signal being inverted the first inverted signal and an interpolation unit for interpolating a phase difference between the first non-inverted signal and the second non-inverted signal.

Abstract: An embodiment of this invention provides a circuit and method for reducing the number of electronic components needed to calibrate circuits on an IC. A multiplexer is located on the IC where the outputs of a plurality of circuits located on the IC are each connected to a separate data input of the multiplexer. The control input of the multiplexer selects which data input of the multiplexer is connected to an external component. Each data input is individually connected to the component periodically.

Abstract: An electronic module has a heat sink with an upper surface and a lower surface, a plurality of leads arranged adjacent the heat sink and at least one circuit element with two vertical semiconductor power switches. The two vertical semiconductor power switches of each circuit element are arranged in a stack and are configured to provide a half-bridge circuit having a node defining an output. The first vertical semiconductor power switch of each of the circuit elements is mounted on the upper surface of the heat sink by an electrically conductive layer such that the lower surface of the heat sink provides the ground contact area of the electronic module.

Abstract: CMOS circuitry used to multiplex between data inputs suffers from high sensitivity to power supply noise, resulting in delay variations. By utilizing current controlled inverters in a multiplexer structure, power supply insensitivity can be achieved with either of two multiplexing methods. The first method places switches on the data inputs while the second places the switches on the analog bias voltages inherent to a current controlled inverter.

Abstract: An improved high-fanin multiplexer that is highly-scalable, fast and area-efficient. In one embodiment of the present invention, multiple logic “legs” are attached to a common output line. Each leg comprises one pMOS pull-up transistor and one nMOS pull-down transistor. The gate of the pMOS transistor in each leg is connected to the output of an And-Or-Invert (AOI) gate whose inputs are connected to a plurality of select lines and a plurality of data lines. The gate of the nMOS transistor in each leg is connected to the output of an Or-And-Invert (OAI) gate whose inputs are connected to a plurality of select lines (the logical complements of the select lines for the AOI), and a plurality of data input lines. The high-fanin multiplexer of the present invention offers numerous advantages over the prior art. In particular, the high-fanin multiplexer of the present invention has very small self-loading allowing a large number of inputs while also maintaining a high fan out speed.

Abstract: An integrated circuit includes a reset connection to reset the device in response to an externally provided signal. The reset connection is used during test operations to receive elevated supply voltages. The reset connection is coupled to a bias circuit to maintain an inactive state such that the integrated circuit is not reset during the test operation when the reset connection is not actively driven by the external supply.

Abstract: An apparatus for a multiplexor circuit includes a passgate circuit coupled to receive input signals and corresponding select signals comprising a subset of the input signals and select signals received by the multiplexor. The apparatus also includes a default circuit coupled to receive the select signals and coupled to an output node of the passgate circuit. If none of the select signals is asserted, the default circuit supplies a default voltage on the output node. Other passgate circuits and default circuits may be included coupled to other subsets of the input signals and select signals, and an output circuit may be included with inputs coupled to the output nodes of the passgate circuits. The default voltage may represent a logical value which allows the value from another passgate circuit to control the output of the output circuit.

Abstract: An apparatus for a current mode logic variable delay element. A preferred embodiment comprises an input signal that is provided to a multiplexer (for example, multiplexer 210) in both buffered (via a buffer (for example, buffer 205)) and unbuffered form. A control signal of the multiplexer may be used to select from either the buffered or unbuffered input signals. By using a control signal at an intermediate value (somewhere in between values that selects the buffered or unbuffered input signals), the multiplexer may then combine the buffered and unbuffered input signals in proportion with the value of the control signal and imparts a delay upon the input signal that may be in between the delay imparted by the buffer.

Abstract: An integrated circuit includes a reset connection to reset the device in response to an externally provided signal. The reset connection is used during test operations to receive elevated supply voltages. The reset connection is coupled to a bias circuit to maintain an inactive state such that the integrated circuit is not reset during the test operation when the reset connection is not actively driven by the external supply.

Abstract: A high-speed multiplexer that includes a reduced number of components in the pull-up and/or the pull-down circuits operates faster than conventional multiplexers and can process higher frequency input signals. The pull-up circuit may be a singe p-type MOSFET transistor and the pull-down circuit may be a single n-type MOSFET transistor. The switching circuits may include transistor-based NOR gates. The multiplexer may have numerous channels, for example 2 to 256 or more channels.

Abstract: A clock routing circuit is coupled to receive a primary clock signal, a secondary clock signal, and a select signal, all of which may be asynchronous with respect to one another. When the select signal is in a first state, the clock routing circuit passes the primary clock signal as an output clock signal. When the select signal transitions to a second state, the clock routing circuit waits for the primary clock signal to transition in a predetermined direction (i.e., rising edge or falling edge). Upon detecting the transition of the primary clock signal, the clock routing circuit holds the state of the output clock signal. The clock routing circuit then waits for the secondary clock signal to transition in the predetermined direction. Upon detecting the transition of the secondary clock signal, the clock routing circuit passes the secondary clock signal as the output clock signal.

Abstract: An electronic system (101/102) for use in a car has an electronic control unit (10) and, in the alternative, either a passive load (11) or an active logic (12) attached thereto. The control unit (10) comprises a push-pull arrangement (20) which can provide drive signals for the load (11) as well as for the logic (12), a multiplexer (45) to alternatively forward a load drive signal of a bus signal to the arrangement (20), and a register (90) to store a mode signal. Further, the control unit (10) automatically determines whether either the load (11) or the logic (12) is attached by analyzing electrical parameters.

Abstract: The present invention discloses a multiplexer including that provides an output signal having a voltage range substantially equal to an input signal. The multiplexer further provides a breakdown prevention device that protects elements connected to an output terminal. The multiplexer can be used in an LCD driver or the like. The multiplexer according to the present invention can include a first switching circuit that receives a first input signal, a second switching circuit that receives a second input signal, wherein the first and second switching circuits are complementarily enabled in response to a three control signals, a third switching circuit that receives the first input signal switched from the first switching circuit and a fourth switching circuit that receives the second input signal switched from the second switching circuit. The third and fourth switching circuits are complementarily enabled by a selection signal to provide one of the first and second input signals to the output terminal.

Abstract: A semiconductor device is arranged by a push-pull circuit 1 for shifting a first center potential of an amplitude of an input signal to a second center potential, and for outputting first and seconc complimentary signals P1, P2 having said second center potential, and further a bipolar type differential amplifier 2 for receiving the first and second complementary signals as input signals thereof.

Abstract: A video signal processing apparatus of the invention has an image pickup unit for picking up an image of an object and generating a video signal corresponding to the picked-up object image, a signal processing unit for executing various kinds of signal processes to the video signal which is generated from the image pickup unit, and a cable for electrically connecting the image pickup unit and the signal processing unit. In order to transmit and receive a data signal between the image pickup unit and the signal processing unit through the cable, for a predetermined period of time of the video signal which is transmitted from the image pickup unit to the signal processing unit through the cable, a plurality of kinds of video signals of different DC potentials are switched and outputted in accordance with the data signal, thereby multiplexing the data signal to the video signal.

Abstract: A multiplexer selectively connects one of first and second nodes to a third node. The multiplexer includes a first switch coupled between the first and third nodes, a second switch coupled between the second and third nodes, and a control input for receiving a signal to either open the first switch and close the second switch or open the second switch and close the first switch. Additionally, a delay circuit, coupled to the control input and the second switch, delays closure of the second switch until the first switch is open. In a preferred embodiment, the delay circuit includes two field-effect transistors having substantially different width-to-length ratios.

Abstract: A multiplexed output circuit (200) for use in an integrated circuit (500) such as a static random access memory locates a plurality of amplifiers (206, 208), a plurality of output buffers (210, 212), and an output driver (201) on the integrated circuit (500), such that the routing parasitic delay between the plurality of output buffers and the output driver (218-224) is greater than the routing parasitic delay between any output buffer (e.g. 212) and its corresponding amplifier (e.g. 206).

Abstract: A quadrant detector circuit (400) has a comparator (442) having a pair of inputs (438, 440). A first (438) of the pair of inputs (438, 440) is coupled to an in-phase signal (434) and a second (440) of the pair of inputs (438, 440) is coupled to a quadrature phase signal (436). A sample counter (448) has a reset (446) coupled to an output (444) of the comparator (442). A controllable switch (456) has a selection input (454) coupled to an output (452) of the sample counter (448). The controllable switch (456) is capable of switching between a local oscillator signal (458) and an inverse local oscillator signal (460).

Abstract: A selector switch circuit comprises an input terminal to receive a positive voltage, an input terminal to receive a negative voltage, a command input terminal to receive a first command logic signal and an output terminal to provide an output voltage. The output is connected selectively to one of the input terminals, the first and second input terminals being connected to the output terminal by means of a first transistor and a second transistor and the circuit comprising control means for the production, as a function of the command signal, of the control voltages applied to the control gates of the transistors for the selective connection of the output terminal to one of the input terminals.

Abstract: An electronic driver circuit for low-impedance loads, being of a type which comprises an input terminal (IN) to which a voltage signal (Vin) is applied for alternate transfer to an output, and a plurality of output terminals (OUTi), each connected to a corresponding electric load (2), further comprises, between the input terminal and the output terminals, a single operational amplifier (3) having multiple output stages (7), one for each output terminal (OUTi). The operational amplifier (3) is of the single-ended or fully differential multistage type and allows each load to be driven alternately by activation of the corresponding output stage (7i).

Abstract: A high frequency circuit using output drivers with tri-state sections. The plurality of output drivers are connected to an output transmission line. Each driver has a pull-up section, a pull-down section and a tri-state section. Each tri-state section has a low impedance and a high impedance state. Its low impedance state serves to match the impedance of the output transmission line. Its high impedance state isolates its driver from the output transmission line.

Abstract: An off-chip driver with regulated supplies compensates for power supply fluctuations. The circuit reduces di/dt noise by providing complementary voltage regulators to regulate the high and low supplies to the driver stages such that they see a constant operating voltage regardless of changes in supply voltage, V.sub.CC. The circuit uses two push-pull stages which charge and discharge the output load capacitance, C.sub.0. This regulated voltage to the driver stages reduces di/dt noise and provides a constant overdrive voltage, constant gate slew rate, and constant staging delay over a specified external supply voltage range.

Abstract: In an output circuit having first and second MOS transistors in series between a first power supply line and a second power supply line, and a third MOS transistor, the gates of the first and second transistors are connected to first and second input nodes, respectively, and an output node is provided between the first and second MOS transistors. The third MOS transistor is connected between one of the input nodes and the output node. The gate of the third MOS transistor is connected to a third power supply line.

Abstract: A push-pull output driver including two transistors in series, one transistor having its body bias controlled by logic circuitry commanded by the driver input. The driver has a pair of transistors in series, the transistor inputs being complementary to create a push-pull amplifier. A switching transistor is controlled by the inverse of the driver input signal and acts as a switch at the pull-up transistor well-tie. When the driver input is high, the switching transistor is off allowing the well-tie to the pull-up transistor to be connected to the driver output. When the input is low, the switching transistor turns on, switching the well-tie of the pull-up transistor to ground. By controlling the body bias of the pull-up transistor in this way, the switching speed of the output driver is significantly increased. When the output driver is in a disabled tri-state mode, the series transistors, and the switching transistor, are turned off.