Field-effect Transistor Patents (Class 327/408)
  • Patent number: 11489520
    Abstract: A power switching circuit includes a first switch circuit, a second switch circuit, a control circuit, and a driver circuit. The first switch circuit receives a first power voltage and coupled to an output terminal. The first switch circuit includes a first P-type transistor and a second P-type transistor coupled in series. The second switch circuit receives a second power voltage and coupled to the output terminal. The second switch circuit includes a third P-type transistor and a fourth P-type transistor coupled in series. The control circuit generates a control signal according to an output voltage at the output terminal, a power state signal, and one of the first power voltage and the second power voltage. The driver circuit generates a first driving signal or a second driving signal according to the control signal to control the first switch circuit or the second switch circuit.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: November 1, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Chien-Hao Chiu
  • Patent number: 11424741
    Abstract: An n-well voltage switching circuit (60) and methodology are disclosed for generating a maximum bias voltage (VMAX) at the output voltage node with cross-coupled PMOS switching transistors (63) connected to a voltage supply remapping circuit (61, 62, 64) which receives first and second power supplies (VSUP1, VSUP2) and generates first and second gate driving signals (G1, G4), wherein the first and second gate driving signals are connected, respectively, to the gates of the first and second cross-coupled PMOS transistors (P5, P6) to pull a gate for one of the cross-coupled PMOS transistors to ground so that the higher of the first and second power supplies is coupled to the output voltage node over one of the first and second cross-coupled PMOS transistors, thereby generating a maximum bias voltage at the output voltage node.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: August 23, 2022
    Assignee: NXP B.V.
    Inventors: Domenico Liberti, Andre Gunther, Jeffrey Alan Goswick
  • Patent number: 11320850
    Abstract: A voltage selection circuit for selecting a voltage from a plurality of input voltages comprising a plurality of diodes, each diode having a first terminal coupled to one of the input voltages, and a current sensor configured to sense a current flow through each diode, wherein the selected voltage is dependent on the sensed current flow. In operation, the circuit functions as a comparator to detect the maximum among the input voltages. The comparator decision is used to close one or more of the power switches to ensure that the load is powered from the highest input voltage.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: May 3, 2022
    Assignee: Dialog Semiconductor B.V.
    Inventor: Andrew John Myles
  • Patent number: 11283350
    Abstract: A power source switching device that includes: a switch connected to a signal input terminal via a first resistor element and configured to fix a potential of the signal input terminal at a predetermined potential by adopting an ON state in a case in which a selection signal is not input; and a switch control circuit configured to perform control to place the switch in an OFF state based on a state signal indicating an operational state of a circuit that operates when supplied with power from a power source selected according to the selection signal in a case in which a potential of the selection signal is different from the predetermined potential, and to perform control to place the switch in the ON state in a case in which the selection signal is not input.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: March 22, 2022
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Tetsuya Ono
  • Patent number: 11263944
    Abstract: A circuit device includes a transfer gate and a control circuit. The transfer gate includes a P-type transistor and an N-type transistor. The control circuit sets, as a first value, a transistor size ratio that is a ratio of a size of the P-type transistor to a size of the N-type transistor when a voltage of an input signal to the transfer gate is in a first voltage range at a timing at which the transfer gate is turned off. The control circuit sets the transistor size ratio as a second value greater than the first value when a voltage of the input signal is in a second voltage range lower than that in the first voltage range at a timing at which the transfer gate is turned off.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: March 1, 2022
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Akira Morita
  • Patent number: 11133836
    Abstract: A radio frequency (RF) switch circuit is provided. The switch includes a branch configured and arranged to transfer an RF signal coupled at an input node to an output node when a control signal is at a first logic value. A first transistor in the branch includes a first current electrode coupled at the input node and a second current electrode coupled to an intermediate node. The first transistor is formed in a first isolation well coupled to a bias voltage supply terminal. A second transistor in the branch includes a first current electrode coupled to the second current electrode of the first transistor at the intermediate node and a second current electrode coupled at the output node. The second transistor is formed in a second isolation well coupled to the bias voltage supply terminal. A third transistor includes a first current electrode coupled at the first intermediate node and a second current electrode coupled at a first supply terminal.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: September 28, 2021
    Assignee: NXP USA, INC.
    Inventor: Yi Yin
  • Patent number: 11106235
    Abstract: A configurable clock buffer including first and second buffers and isolation circuitry. The first buffer has an input coupled to a clock input node and has an output coupled to a clock output node. The second buffer has an input coupled to an intermediate input node and has an output coupled to an intermediate output node. The isolation circuitry is responsive to at least one mode signal, in which it electrically couples the intermediate input node to the clock input node and electrically couples the intermediate output node to the clock output node when the at least one mode signal is in a first state, and in which it electrically couples the intermediate input node to a static node and electrically isolates the intermediate output node from the clock output node when the at least one mode signal is in a second state.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: August 31, 2021
    Assignee: Silicon Laboratories Inc.
    Inventor: Thomas Saroshan David
  • Patent number: 10924116
    Abstract: A motor controller system that includes an analog switch multiplexer system is disclosed. Specific implementations include a plurality of field effect transistors (FETs) that may be configured to be operatively coupled with one or more phases of a motor. Each of the plurality of FETs may include a gate, an analog switch multiplexer coupled with each of the gates of the plurality of FETs and with an analog output, and a digital control block coupled with the analog switch multiplexer that may be configured to send a multiplexer select control signal to the analog switch multiplexer in response to receiving a serial peripheral interface signal.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: February 16, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Konosuke Taki
  • Patent number: 10917090
    Abstract: A circuit includes a first switch assembly having a first input node and a first output node, and a second switch assembly having a second input node and a second output node. The circuit further includes a third switch assembly an operational amplifier, and a buffer. The third switch assembly has a third input node and a third output node. The third input node is coupled to the second output node, and the third output node is coupled to the first output node. The buffer has a buffer input and a buffer output. The buffer input is coupled to an input stage of the operational amplifier. The buffer output is coupled to the third switch assembly.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: February 9, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Nitin Agarwal, Kunal Suresh Karanjkar, Venkata Ramanan R
  • Patent number: 10609244
    Abstract: A photoelectric conversion element includes a plurality of pixels to receive light; and a signal processor to process a signal of the pixels. The signal processor includes: a first element, being a transistor, having a first effective channel width through which a current can effectively pass through in the first element; and a second element, being a transistor, having a second effective channel width through which a current can effectively pass through in the second element. The first effective channel width of the first element is larger than the second effective channel width of the second element.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: March 31, 2020
    Assignee: Ricoh Company, Ltd.
    Inventors: Masamoto Nakazawa, Yuuya Miyoshi, Atsushi Suzuki
  • Patent number: 10469085
    Abstract: A circuit for providing back-up power includes a switching circuit configured to be coupled to a first power source and a second power source. The circuit includes a domain voltage level monitor circuit coupled with the first power source and the second power source and with output of the switching circuit. The circuit includes a dynamic level shifter circuit coupled with the first power source and the second power source and an output of the domain voltage level monitor. The circuit includes a double controlled latch circuit coupled with the first power source and the second power source and an output of the dynamic level shifter circuit. The double controlled latch circuit is configured to provide control signals to the switching circuit.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: November 5, 2019
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Gabriel Rosca, Richard Hull, Zacharias M. Smit, Razvan Enachescu, Alexandru Vidrasan
  • Patent number: 10431144
    Abstract: A scan circuit unit includes a shift register unit; a first set of transistors operable to selectively transfer a first clock signal to a first output terminal in dependence on an output pulse signal of the shift register unit, and to selectively transfer an inactive level voltage to the first output terminal in dependence on a second clock signal; and a second set of transistors operable to selectively transfer the second clock signal to a second output terminal in dependence on the output pulse signal, and to selectively transfer the inactive level voltage to the second output terminal in dependence on the first clock signal.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: October 1, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Lirong Wang
  • Patent number: 10340704
    Abstract: A switch device includes a common terminal and a selection circuit. The selection circuit includes a primary switch, a first secondary switch, and a second secondary switch. The primary switch includes a plurality of primary transistors coupled in series and is coupled to the common terminal. The first secondary switch is coupled to the primary switch and a first transmission terminal. The first secondary switch includes a plurality of first secondary transistors coupled in series. The second secondary switch is coupled to the primary switch and a second transmission terminal. The second secondary switch includes a plurality of second secondary transistors coupled in series. The number of the first secondary transistors and the number of the second secondary transistors are both greater than or equal to the number of the primary transistors.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: July 2, 2019
    Assignee: RichWave Technology Corp.
    Inventors: Chih-Sheng Chen, Ching-Wen Hsu
  • Patent number: 10312684
    Abstract: Systems and methods for intelligent transfer and management of power maintain a continuous and cost efficient supply of power to electrical loads in a residential or commercial unit when different energy resources such as utility, backup generators, energy storage systems and distributed energy resources (e.g. solar and wind) are available.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: June 4, 2019
    Inventors: Seyed Ali Nabavi Niaki, Saeed Hassan Fard
  • Patent number: 10298228
    Abstract: A multiplexer circuit, of power supply (PS) voltages, includes: selectable finger circuits corresponding to the PS voltages, each selectable finger circuit: having an input node which is finger-circuit-specific and an output node which is common to the finger circuits; being configured to receive a corresponding one of the PS voltages from the input node and, if selected, provide a first version of the corresponding PS voltage to the output node. Each of the selectable finger circuits includes: a non-enhancement mode transistor of a first conductivity (C1) type (C1-type transistor) and enhancement mode first and second transistors of a second conductivity (C2) type (C2-type transistor) connected in series between the input node and the output node.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: May 21, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yang-Chi Yen, Bo-Ting Chen
  • Patent number: 10110060
    Abstract: The disclosed invention is intended to prevent malfunction of an internal circuit because of unwanted power supply switching caused by a noise during operation of a semiconductor device powered by a backup power supply, while eliminating wasteful consumption of the backup power supply. A first switching transition time after coupling the main power supply terminal to the internal power supply node until decoupling the backup power supply terminal from the internal power supply node is made longer than a second switching transition time after coupling the backup power supply terminal to the internal power supply node until decoupling the main power supply terminal from the internal power supply node.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: October 23, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tomoki Yasukawa, Akira Oizumi, Toyohiko Yoshida, Yoshinori Tokioka
  • Patent number: 10078312
    Abstract: The present invention relates to a fault-tolerant control system for a wind power plant comprising a plurality of power units, the control system comprising control means for generating a replica of essentially concurrent power unit set-point values, a data communication network for transmitting the essentially concurrent power unit set-point values to the plurality of power units and a plurality of decentralised voting means being arranged so that a decentralised voting means is assigned to each power unit, each decentralised voting means being adapted to select one power unit set-point value out of the replica of power unit set-points. The present invention further relates to an associated method.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: September 18, 2018
    Assignee: VESTAS WIND SYSTEMS A/S
    Inventors: John Bengtson, Niels Erik Danielsen
  • Patent number: 9841797
    Abstract: A power supply switch apparatus includes a first interface, a switch circuit, and a power supply circuit. The first interface includes a first control signal output terminal, a second control signal output terminal, and a third control signal output terminal. Each of the first control signal output terminal, the second control signal output terminal, and the third control signal output terminal outputs a control signal according to an electronic device inserted in the first interface. The switch circuit receives the control signals and outputs a power supply signal accordingly. The power supply circuit receives the power supply signal, and provides a first direct current (DC) voltage or a second DC voltage to the electronic device according to the power supply signal.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: December 12, 2017
    Assignees: HONG FU JIN PRECISION INDUSTRY (WuHan) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Dao-Wei Li, Chun-Sheng Chen
  • Patent number: 9787135
    Abstract: The disclosed invention is intended to prevent malfunction of an internal circuit because of unwanted power supply switching caused by a noise during operation of a semiconductor device powered by a backup power supply, while eliminating wasteful consumption of the backup power supply. A first switching transition time after coupling the main power supply terminal to the internal power supply node until decoupling the backup power supply terminal from the internal power supply node is made longer than a second switching transition time after coupling the backup power supply terminal to the internal power supply node until decoupling the main power supply terminal from the internal power supply node.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: October 10, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tomoki Yasukawa, Akira Oizumi, Toyohiko Yoshida, Yoshinori Tokioka
  • Patent number: 9742401
    Abstract: First and second p-type transistors are connected in series between an output terminal and a positive power terminal. First and second n-type transistors are connected in series between a node and a negative power terminal. A third p-type transistor is connected between a node and the positive power terminal. Third and fourth n-type transistors are connected in series between the output terminal and a low potential terminal. Fourth and fifth p-type transistors are connected in series between a node and the negative power terminal. A fifth n-type transistor is connected between a node and the negative power terminal. A high potential is outputted without leak current when the first to fifth p-type transistors are turned on and the first to fifth n-type transistors are turned off.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: August 22, 2017
    Assignee: DENSO CORPORATION
    Inventors: Shogo Kawahara, Tomohiro Nezuka
  • Patent number: 9721667
    Abstract: There are provided a high voltage switch circuit and a semiconductor memory device including the same. A high voltage switch circuit may include a switching circuit including a first depletion transistor and a first high voltage transistor, which are coupled in series between an input terminal and an output terminal, and a control signal generator for applying, to the first depletion transistor, a control signal having the same potential level as an input voltage applied to the input terminal, in response to a first enable signal and a second enable signal.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: August 1, 2017
    Assignee: SK hynix Inc.
    Inventors: Yeong Joon Son, Jin Su Park
  • Patent number: 9673758
    Abstract: A differential amplification circuit may include a differential amplification unit including a first input transistor and a second input transistor, and suitable for differentially amplifying input signals inputted through the first and second input transistors; a first input control section suitable for turning off the first input transistor when the differential amplification circuit is disabled and transferring a first input signal to the first input transistor when the differential amplification circuit is enabled; and a second input control section suitable for turning off the second input transistor when the differential amplification circuit is disabled and transferring a second input signal to the second input transistor when the differential amplification circuit is enabled.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: June 6, 2017
    Assignee: SK Hynix Inc.
    Inventor: Kyoung-Han Kwon
  • Patent number: 9654101
    Abstract: An integrated circuit (IC) is disclosed herein for power management through power rail multiplexing. In an example aspect, an IC includes a first power rail, a second power rail, and a load power rail. The IC also includes a first set of transistors including first transistors that are coupled to the first power rail and a second set of transistors including second transistors that are coupled to the second power rail. The IC further includes power-multiplexer circuitry that is configured to switch access to power for the load power rail from the first power rail to the second power rail by sequentially turning off the first transistors of the first set of transistors and then sequentially turning on the second transistors of the second set of transistors.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: May 16, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Lipeng Cao, Divjyot Bhan, Ramaprasath Vilangudipitchai, Dorav Kumar
  • Patent number: 9576675
    Abstract: A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes power management circuitry configured to receive the second voltage and derive one or more internal voltages. The power management circuitry supplies or conveys the internal voltages to the flash memory. The different internal voltages generated by the power management circuitry (e.g., voltage converter circuit) and supplied to the core memory enable operations such as read/program/erase with respect to cells in the core memory.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: February 21, 2017
    Assignee: Conversant Intellectual Property Management Inc.
    Inventors: Jin-Ki Kim, Peter B. Gillingham
  • Patent number: 9571094
    Abstract: To provide a switch circuit which is capable of reliably controlling transmission of a voltage from GND to VDD to an internal circuit or shut-off thereof even when a positive or negative voltage is inputted to an input terminal, and thereby reduces the risk of latch-up. A switch circuit is comprised of NMOS transistors, and the gates of the NMOS transistors are controlled by an output voltage of a boosting circuit, thereby making it possible to reliably control transmission or shut-off of a voltage from GND to VDD.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: February 14, 2017
    Assignee: SII Semiconductor Corporation
    Inventors: Naohiro Hiraoka, Tomohiro Oka
  • Patent number: 9531375
    Abstract: A radio frequency switch circuit may include: a first switch circuit unit connected between a first signal port for transmitting and receiving a signal and a common connection node and operated by a first gate signal; a second switch circuit unit connected between a second signal port for transmitting and receiving a signal and the common connection node and operated by a second gate signal; a first shunt circuit unit including first and second shunt units connected to each other in series between a first connection node connected to the first signal port and a ground, the first shunt unit being operated by the first gate signal and the second shunt unit being operated by the second gate signal; and a second shunt circuit unit connected between a second connection node connected to the second signal port and the ground and operated by the first gate signal.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: December 27, 2016
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Yoo Sam Na, Jong Myeong Kim, Yoo Hwan Kim, Hyun Hwan Yoo, Dae Seok Jang, Hyun Jin Yoo
  • Patent number: 9442875
    Abstract: A receiver circuit configured to operate in a DisplayPort (DP) mode and a High-Definition Multimedia Interface (HDMI) mode. The receiver circuit includes: termination circuitry configured to receive a DP signal in the DP mode and an HDMI signal in the HDMI mode; and voltage common-mode (VCM) level shifter circuitry configured to operate as a pass-through for the DP signal in the DP mode and generate a converted HDMI signal from the HDMI signal in the HDMI mode.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: September 13, 2016
    Assignee: Synaptics Incorporated
    Inventor: Yonggang Chen
  • Patent number: 9438072
    Abstract: A server includes a power module, a detection circuit, a switching circuit, at least one first electric component and at least one second electric component. The power module supplies a standby voltage under a standby mode and supplies a working voltage under a working mode. The detection circuit receives a working mode signal of the server to output a control signal. The working mode signal specifies that the server is under the standby mode or the working mode. The switching circuit is supplied with the working voltage, the standby voltage and a converted control signal generated by converting the control signal, to transfer either the working voltage or the standby voltage. The first electric component works under the working mode only. The second electric component works under the standby mode and the working mode.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: September 6, 2016
    Assignees: INVENTEC (PUDONG) TECHNOLOGY CORPORATION, INVENTEC CORPORATION
    Inventor: Yan-Long Sun
  • Patent number: 9383770
    Abstract: A multi-display device can interface with two or more different types of docking stations. The device can determine the type of dock and change the pin outs for a connector to interface with that dock. Once docked, the device can determine a charge status for the device and the dock to present the status to the user. Further, the dock can enter one of several modes, including a call receipt mode and an entertainment mode. The modes allow for expanded functionality for the device while docked. Two particular docks, the laptop dock and the smart dock, provide special functionality with the device.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: July 5, 2016
    Assignee: Z124
    Inventor: Richard Teltz
  • Patent number: 9279843
    Abstract: A charge transfer circuit for capacitive sensing is disclosed. The charge transfer circuit for capacitive sensing includes a variable capacitor, an X-drive unit, and an active output voltage feedback (AVF) part. The variable capacitor is disposed between the output terminal of an X-drive line and the input terminal of a Y-drive line. The X-drive unit is connected between the input unit of the X-drive line and a voltage input terminal. The active output voltage feedback (AVF) part is connected between the output terminal of the Y-drive line and a voltage output terminal. The output terminal of the AVF part is connected to the output terminal of the Y-drive line.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: March 8, 2016
    Assignee: Hanshin University Industry-Academic Cooperation Foundation
    Inventor: Hyeop Goo Yeo
  • Patent number: 9240785
    Abstract: At least one analog signal compatible complementary metal oxide semiconductor (CMOS) switch circuit is incorporated with digital logic circuits in an integrated circuit. The integrated circuit may further comprise a digital processor and memory, e.g., microcontroller, microprocessor, digital signal processor (DSP), programmable logic array (PLA), application specific integrated circuit (ASIC), etc., for controlling operation of the at least one analog signal compatible CMOS switch for switching analog signals, e.g., audio, video, serial communications, etc. The at least one analog signal compatible CMOS switch may have first and second states, e.g., single throw “on” or “off”, or double throw common to a or b, controlled by a single digital control signal of either a logic “0” or a logic “1”.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: January 19, 2016
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventor: James K. Russell
  • Patent number: 9215046
    Abstract: The fault diagnosis device is for a multiplexer having inner channels selectable by a selection signal. At least two of the inner channels are assigned with input channels. Two of the inner channels in a mutually exclusive relationship are assigned with first and second diagnostic channels. Input voltages of the first and second diagnostic channels are applied with first and second diagnostic voltages, respectively. The fault diagnostic device includes a voltage detection section configured to detect a first detection voltage appearing at the output channel when the first diagnostic channel is selected and a second detection voltage appearing at the output channel when the second diagnostic channel is selected, and a diagnosis section configured to determine that the multiplexer is faulty upon detecting that the first detection voltage is different from the first diagnostic voltage or the second detection voltage is different from the second diagnostic voltage.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: December 15, 2015
    Assignee: DENSO CORPORATION
    Inventor: Tomomichi Mizoguchi
  • Patent number: 9160321
    Abstract: A power efficient multiplexer. In accordance with a first embodiment, a power efficient multiplexer comprises a transmission gate structure for selectively passing one of a plurality of input signals and a stacked inverter circuit for inverting the one of a plurality of input signals. Both the stacked inverter and the transmission gate provide beneficial reductions in static power consumption in comparison to conventional multiplexer designs.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: October 13, 2015
    Inventor: Robert Paul Masleid
  • Patent number: 9124265
    Abstract: A transistor switch that provides isolation is described. The transistor switch is adapted to receive an input signal at an input terminal and either transmit the input signal to an output terminal when the transistor switch is in a first state or ground the input signal when the transistor switch is in a second state. The transistor switch comprises series switches, which couple the input terminal to the output terminal when the transistor switch is in the first state; shunt switches, which couple the input terminal to ground when the transistor switch is in the second state; and filters to provide isolation between the input terminal and the output terminal.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: September 1, 2015
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Jeffrey A. Dykstra
  • Patent number: 9106124
    Abstract: A low-inductive power semiconductor assembly is provided in which semiconductor switches are arranged behind one another in a main current path.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: August 11, 2015
    Assignee: Infineon Technologies AG
    Inventors: Reinhold Bayerer, Daniel Domes
  • Patent number: 9024676
    Abstract: An active matrix panel includes a gate line connected to control electrodes of a plurality of transistors; and a drive circuit supplying the gate line with a conducting voltage and a non-conducting voltage. The drive circuit includes a shift register including a plurality of shift register unit circuits connected to each other, and a demultiplexer including a plurality of demultiplexer unit circuits into which output signals of the shift register unit circuits are input. The demultiplexer unit circuit includes a first transistor for supplying the gate line with the conducting voltage, and a second transistor for supplying the gate line with the non-conducting voltage. The first transistor is changed from a non-conducting state into a conducting state when the second transistor is in the conducting state.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: May 5, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masato Ofuji, Chiori Mochizuki, Minoru Watanabe, Keigo Yokoyama, Jun Kawanabe, Kentaro Fujiyoshi, Hiroshi Wayama
  • Patent number: 9013228
    Abstract: Embodiments described in the present disclosure relate to a method for providing power for an integrated system, including acts of: providing the system with power, ground and body bias voltages, the body bias voltages comprising a body bias voltage of p-channel MOS transistors, greater or lower than the supply voltage, and a body bias voltage of n-channel MOS transistors, lower or greater than the ground voltage, selecting by means of the system out of the voltages provided, depending on whether a processing unit of the system is in a period of activity or inactivity, voltages to be supplied to bias the bodies of the MOS transistors of the processing unit, and providing the bodies of the MOS transistors of the processing unit with the voltages selected.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: April 21, 2015
    Assignee: STMicroelectronics SA
    Inventor: Frédéric Hasbani
  • Publication number: 20150091635
    Abstract: Methods and apparatuses are disclosed for a high speed, low power, isolated multiplexer having architecture and operation that control current flow to minimize coupling and power consumption. Multiplexer architecture may include one or more of BiCMOS components, an input disabling circuit operated to additionally disable an input circuit when it is also disabled by a selection circuit, a multiplexer disabling circuit operated to disable a multiplexer when input circuits are disabled by the selection circuit, a buffer having a buffer input disabling circuit operated to additionally disable a buffer input circuit when it is also disabled by a buffer selection circuit and a buffer disabling circuit operated to disable a buffer when the buffer input circuit is disabled by the buffer selection circuit. Any one or more of these features may be implemented to improve isolation performance. The architecture may be operated by a one-hot coding scheme.
    Type: Application
    Filed: September 30, 2013
    Publication date: April 2, 2015
    Inventor: Chengming He
  • Patent number: 8994440
    Abstract: A voltage select circuit includes a plurality of first transfer elements configured to transfer respective operating voltages to a first output terminal, a transfer select circuit unit configured to output a first voltage necessary to transfer an operating voltage, selected from among the operating voltages, to at least one first transfer element in response to a plurality of enable signals, and a control circuit configured to boost the first voltage to a second voltage in response to the plurality of enable signals.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: March 31, 2015
    Assignee: SK Hynix Inc.
    Inventor: Je Il Ryu
  • Patent number: 8981839
    Abstract: Circuitry, which includes a first switching transistor element having a first gate, a second switching transistor element having a second gate, a third switching transistor element having a third gate, and a fourth switching transistor element having a fourth gate, is disclosed. The first switching transistor element and the third switching transistor element are coupled in series between a first power source and a first downstream circuit. The second switching transistor element and the fourth switching transistor element are coupled in series between a second power source and the first downstream circuit. A voltage swing at the first gate and a voltage swing at the second gate are both about equal to a first voltage magnitude. A voltage swing at the third gate and a voltage swing at the fourth gate are both about equal to a second voltage magnitude.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: March 17, 2015
    Assignee: RF Micro Devices, Inc.
    Inventors: Michael R. Kay, Manbir Singh Nag, Philippe Gorisse
  • Patent number: 8963614
    Abstract: A semiconductor device includes an internal high voltage terminal supplied with an internal high voltage, an internal negative voltage terminal supplied with an internal negative voltage, a monitoring pad suitable for monitoring the internal high and negative voltages, a first switch suitable for controlling electrical connection between the high voltage terminal and the monitoring pad and including two or more transistors coupled in series, and a second switch suitable for controlling electrical connection between the negative voltage terminal and the monitoring pad and including two or more transistors coupled in series.
    Type: Grant
    Filed: December 15, 2013
    Date of Patent: February 24, 2015
    Assignee: SK Hynix Inc.
    Inventor: Sang-Ho Lee
  • Patent number: 8963613
    Abstract: A current mirror circuit is described. The current mirror circuit includes a first transistor and a second transistor. The gates of the first transistor and the second transistor are coupled at a bias voltage. The current mirror circuit also includes an auxiliary transistor that is biased into weak inversion by receiving the bias voltage at a gate of the auxiliary transistor after being reduced by an offset voltage. The sources of the first transistor, second transistor and auxiliary transistor are coupled together. A primary current from the drain of the second transistor is combined with an auxiliary current from the drain of the auxiliary transistor to produce an output current.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: February 24, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Manas Behera, Yanping Ding, Junxiong Deng
  • Publication number: 20150028920
    Abstract: The present invention relates to a multiplexer comprising at least a first input and a second input and one output connected to the first input via a first pass gate and to the second input via a second pass gate, wherein the first pass gate comprises at least a first double-gate transistor, and the second pass gate comprises at least a second double-gate transistor, and each of the first and second double-gate transistors has a first gate controlled based on a first control signal and a second gate controlled based on a second control signal. The invention further relates to a look-up table and a and an FPGA based on the multiplexer.
    Type: Application
    Filed: February 11, 2013
    Publication date: January 29, 2015
    Inventor: Richard Ferrant
  • Patent number: 8901991
    Abstract: Power monitoring circuitry. In some embodiments, comparator circuitry may be configured to receive a first voltage value and a second voltage value, and to identify the greater of the first and second voltage values. Selector circuitry coupled to the comparator circuitry may be configured to power one or more components within the comparator circuitry with a supply voltage corresponding to the greater voltage value. In other embodiments, a method may include identifying, via a comparator, the largest among a plurality of voltage values, and powering one or more logic components within the comparator with the identified voltage value.
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: December 2, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Pedro Barbosa Zanetta, Ivan Carlos Ribeiro Nascimento
  • Patent number: 8773168
    Abstract: A maximum voltage selection circuit and method and a sub-selection circuit are provided. The maximum voltage selection circuit includes a peripheral signal circuit and a selection circuit with N channels of input voltages. The peripheral signal circuit provides an operating mode signal and a reference voltage to the selection circuit including N sub-selection circuits coupled to the N channels of input voltages respectively. A sub-selection circuit determines its operating mode according to the operating mode signal. In the operating mode, when an input voltage of a sub-selection circuit is larger than the reference voltage, the sub-selection circuit sets itself to the output enable state and sets other sub-selection circuits to the output disable state, and outputs its input voltage as a maximum voltage through a PMOS.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: July 8, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Lei Huang
  • Patent number: 8760213
    Abstract: A circuit configured to output a ramp signal having a potential varying depending on time includes a voltage supply unit configured to supply a plurality of voltages having different amplitudes, a current supply unit, an integration circuit configured to output the ramp signal, and a capacitive element. The voltage supply unit is connected to one terminal of the capacitive element. The integration circuit and the current supply unit are connected to another terminal of the capacitive element.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: June 24, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazuhiro Saito, Hiroki Hiyama, Tetsuya Itano, Kohichi Nakamura
  • Patent number: 8749294
    Abstract: An integrated single channel or multi-channel ultrasound transmitter that minimizes the number of input connections to a controller such as an FPGA, field programmable gate array, or a custom integrated circuit in an ultrasound system. The method is accomplished by integrating, in low voltage logic, a means to store and or program the patterns required for the transmitter output. The number of logic input connections can be further reduced by further integrating, in low voltage logic, programmable individual time delays and frequency divider for each transmitter output.
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: June 10, 2014
    Assignee: Supertex, Inc.
    Inventor: Jimes Lei
  • Publication number: 20140117975
    Abstract: A multiplexer for voltage measurement includes: a first switch disposed on a first channel extending between at least one high-voltage input terminal and an output terminal; a plurality of second switches respectively disposed on second channels each extending between each of input terminals other than the high-voltage input terminal and the output terminal; and a third switch disposed between a group of the plurality of second switches and an output terminal side end of the first switch. Each of the first switch and the third switch is configured to operate even by a voltage higher than a power supply voltage.
    Type: Application
    Filed: December 23, 2013
    Publication date: May 1, 2014
    Applicant: PANASONIC CORPORATION
    Inventors: Kazuhiro SHIMOMURA, Ryouta AKEYAMA
  • Patent number: 8686761
    Abstract: A gate driver of a switching element includes a first capacitor having a first end connected to a DC power source, a first switch having a first electrode connected to the first end of the first capacitor and a second electrode connected to a negative electrode of the DC power source, a second switch having a third electrode connected to the second electrode and the negative electrode of the DC power source and a fourth electrode connected to the first capacitor, a second capacitor connected in parallel with the third and fourth electrodes of the second switch and having a first end connected to the DC power source, and a negative voltage controller connecting the gate of the switching element to the second end of the first capacitor and a second end of the second capacitor when the switching element is turned off.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: April 1, 2014
    Assignee: Sanken Electric Co., Ltd.
    Inventor: Keiichiro Ozawa
  • Patent number: 8660502
    Abstract: In a high frequency antenna switch module, an I/O interface generates various control signals for controlling a switch module on the basis of a system data signal and a system clock, a decoder generates a switch control signal SWCNT for controlling a switch in response to a control signal CNT in the control signals, a timing detector for switch-ports switching generates a switch-port switching detection signal t_sw in response to the switch control signal, a frequency control signal generator generates frequency control signals ICONT and CCONT in response to the signal t_sw, and a negative voltage generation circuit generates a negative voltage output signal NVG_OUT while switching the frequency of the clock signal generated in the negative voltage generation circuit to different frequencies in response to signals ICONT and CCONT. The switch switches the paths among the plural switch ports in response to the signals SWCNT and NVG_OUT.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: February 25, 2014
    Assignee: Hitachi Metals, Ltd.
    Inventors: Yusuke Wachi, Takashi Kawamoto, Yuta Sugiyama