Abstract: A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.

Abstract: A disclosed DFE selection element reduces the degree of unrolling that might otherwise be required. In one illustrative embodiment of a method for converting a receive signal from a communication channel into a sequence of symbol decisions, the method includes, for each sampling interval: (a) generating a set of tentative symbol decisions each having a thermometer-coded representation with a least significant bit and a most significant bit; (b) providing each least significant bit as a thermometer-coded input to a first multiplexer; (c) providing each most significant bit as a thermometer-coded input to a second multiplexer; (d) applying a thermometer-coded representation of a preceding output symbol decision as selection inputs to the first and second multiplexers; and (e) capturing a current output symbol decision having a thermometer-coded representation that includes outputs of the first and second multiplexer.

Abstract: An interface circuit is provided and includes a first switching device connected to a first power supply node supplying a first voltage, and controlled by a first input signal, a second switching device connected to a second power supply node supplying a second voltage lower than the first voltage, and controlled by a second input signal different from the first input signal, an output node through which the first switching device and the second switching device are connected to each other in series, outputting an output signal, a first resistor connected between the first power supply node and the first switching device, a second resistor connected between the second power supply node and the second switching device, a first capacitor connected to a node between the first resistor and the first switching device, and a second capacitor connected to a node between the second resistor and the second switching device.

Abstract: An analog-to-digital converter protection circuit, a method for controlling an analog-to-digital converter protection circuit, and a controller are disclosed. The analog-to-digital converter protection circuit includes: an analog switch, an analog-to-digital converter, a controller, and a series circuit including at least two resistors connected in series. The controller is configured to: when the digital voltage is greater than or equal to a preset voltage threshold, output a control signal to the analog switch, to trigger the analog switch to control to a second sampling end from a first sampling end to serve as the conduction sampling end to conduct to the output end of the analog switch, where an analog voltage sampled by the second sampling end is less than an analog voltage sampled by the first sampling end; and when the digital voltage is less than the preset voltage threshold, output the digital voltage.

Abstract: An electronic circuit is disclosed. The electronic circuit includes a substrate having GaN, and a power switch formed on the substrate and including a first control gate and a first source. The electronic circuit also includes a drive circuit formed on the substrate and including an output coupled to the first control gate, and a power supply having a supply voltage and coupled to the drive circuit, where the output can be driven to the supply voltage.

Abstract: The integrated optical receiver module includes a plurality of PDs each converting an optical signal to a current signal, and outputs a current signal selected from a plurality of current signals. The RSSI circuit converts the current signal into a voltage signal, outputs a first amplified signal obtained by amplifying the voltage signal by a first gain, and outputs a second amplified signal obtained by amplifying the voltage signal by a second gain larger than the first gain.

Abstract: An I/O driver and related method are provided herein. The I/O driver includes circuitry for expediting the configuring of the corresponding output FET to operate in the linear region to reduce delay between the transition of the input signal and the corresponding transition of the output signal. Additionally, the I/O driver includes circuitry for controlling the slew rate at which the output signal transitions from a low logic state to a high logic state, or vice-versa. Further, the I.O driver includes circuitry for turning off the turned-on output FET before turning on the other output FET. This prevents “shoot-thru” current from flowing through the output FETs to reduce power consumption associated with the I/O driver.

Abstract: An amplifier with a single-input class-AB output stage comprises an input stage providing a signal to an output stage. The output stage comprises a current-splitting stage having a bias current and providing at least two intermediate output currents, and a drive stage receiving the two intermediate output currents and driving an output signal having a positive side and a negative side.

Abstract: An active matrix panel includes a gate line connected to control electrodes of a plurality of transistors; and a drive circuit supplying the gate line with a conducting voltage and a non-conducting voltage. The drive circuit includes a shift register including a plurality of shift register unit circuits connected to each other, and a demultiplexer including a plurality of demultiplexer unit circuits into which output signals of the shift register unit circuits are input. The demultiplexer unit circuit includes a first transistor for supplying the gate line with the conducting voltage, and a second transistor for supplying the gate line with the non-conducting voltage. The first transistor is changed from a non-conducting state into a conducting state when the second transistor is in the conducting state.

Abstract: A semiconductor device includes an internal high voltage terminal supplied with an internal high voltage, an internal negative voltage terminal supplied with an internal negative voltage, a monitoring pad suitable for monitoring the internal high and negative voltages, a first switch suitable for controlling electrical connection between the high voltage terminal and the monitoring pad and including two or more transistors coupled in series, and a second switch suitable for controlling electrical connection between the negative voltage terminal and the monitoring pad and including two or more transistors coupled in series.

Abstract: A hybrid output driver includes a voltage mode main driver having an adjustable differential output voltage swing, and a current mode emphasis driver. Differential output voltage swing is adjusted by controlling the resistance of a first adjustable resistor coupled to a first voltage supply terminal, and the resistance of a second adjustable resistor coupled to a second voltage supply terminal. Resistances of the first and second adjustable resistors are adjusted by modifying a number of resistors connected in parallel. A calibration process measures the actual resistance of a similar resistor, and uses this resistance measurement to determine the number of resistors to be connected in parallel to provide the desired resistance. The current mode emphasis driver sources/sinks currents to/from differential output terminals of the hybrid output driver in response to an emphasis signal. These currents are selected in view of the selected differential output voltage swing and selected emphasis level.

Abstract: An apparatus relating generally to an analog multiplexer is disclosed. In such an apparatus, the analog multiplexer has first select circuits and at least one second select circuit. The first select circuits have respective input nodes and output nodes. The output nodes are all coupled to one another to provide an output node of the analog multiplexer. The first select circuits are coupled to a first supply voltage of a first supply domain. The at least one second select circuit is coupled to a second supply voltage of a second supply domain different from the first supply domain. The at least one second select circuit has an input port and an output port. The output port is coupled to an input node of the input nodes.

Abstract: There are provided a gate driver circuit and an operating method thereof.

Abstract: A voltage tolerant input/output circuit coupled to an input/output pad, and is able to support a voltage overdrive operation of approximately twice an operational voltage, and have an input tolerance of approximately three times the operational voltage. The circuit includes a pull-up driver, a P-shield, an N-shield, a pull-down driver and a cross-control circuit. The pull-up driver is coupled to a power supply. The P-shield has an N-well and is coupled to the pull-up driver at a node C, and coupled to the input/output pad. An N-shield is also coupled to the input/output pad. A pull-down driver is coupled between ground and the N-shield at a node A. A cross-control circuit is configured to detect voltages at: the node A, the node C, and the input/output pad. The cross-control circuit is configured to output control signals to the P-shield and the N-shield based on the detected voltages.

Abstract: Various methods and structures related to tristate multiplexer circuits are disclosed. An embodiment provides a selection circuit in which selectively enabled input circuits are coupled to an output circuit through an output enable circuit such that a selected one of the selectively enabled input circuits is operable to provide a pathway for charging and discharging currents used to charge and discharge an output circuit transistor gate. This and other detailed embodiments are described more fully in the disclosure.

Abstract: In accordance with embodiments of the present disclosure, a circuit may include a transmission switch and a dummy switch coupled at its output to the output of the transmission switch. The transmission switch may be configured to be selectively enabled and disabled based on a control signal received at a gate of the transmission switch. The transmission switch may be further configured to receive a first polarity of a differential signal at its input and pass the first polarity of the differential signal to its output when enabled. The dummy switch may be configured to be disabled and to receive a second polarity of the differential signal at its input, the second polarity of opposite polarity of the first polarity.

Abstract: The present invention discloses a transistor driving module, coupling to a converting controller, to driving a high side transistor and a low side transistor connected in series, wherein one end of the high side transistor is coupled to an input voltage and one end of the low side transistor is grounded. The transistor driving module comprises a high side driving unit, a low side driving unit, a current limiting unit and an anti-short through unit. The high side driving unit generates a high side driving signal to turn the high side transistor on according to a duty cycle signal, and the low side driving unit generates a low side driving signal turn the low side transistor on according to the high side driving signal. The current limiting unit is coupled to the high side transistor and the high side driving unit, and generates a current limiting signal when a current flowing through the high side transistor higher than a current limiting value.

Abstract: Disclosed is a duty cycle correction device for correcting a duty cycle of a clock signal output from a delay locked loop circuit. The duty cycle correction device includes a mixer for mixing phases of the first and second clock signals, thereby outputting a first signal, a phase splitter receiving the first signal and outputting a third clock signal, a duty detection unit receiving the third and fourth clock signals to detect a difference between duty cycles of the third and fourth clock signals, a combination unit for outputting a second signal, a shift register for outputting a first control signal, a phase detection unit receiving the first and second clock signals and outputting a second control signal representing a difference between duty cycles of the first and second clock signals. The mixer adjusts a mixing ratio by using the first and second control signals.

Abstract: A test circuit according to the present invention performs a test of a first tri-state device and a second tri-state device having their outputs connected to the same node, and includes: a test output terminal; and a test unit operable to output a first logical value or a second logical value to the test output terminal according to whether the voltage of the node is higher or lower than a threshold value, and the test unit converts the intermediate potential occurring at the node into the first logical value and outputs the first logical value to the test output terminal when the first tri-state device outputs a high level signal to the node and the second tri-state device outputs a low level signal to the node.

Abstract: A high performance, set associative, cache memory tag multiplexer provides wide output pulse width without impacting hold time by separating the evaluation and restore paths and using a wider clock in the restore path than in the evaluation path. A clock controls the evaluation of the input signals. Its leading edge (i.e., rising edge) turns on NR to allow evaluation, its trailing edge (falling edge) turns off NR to stop evaluation. At this point, when NR is shut off, the inputs can start changing to set up for the next cycle. Hence the hold time of the input is determined by the clock trailing edge.

Abstract: A mixer for use in a transceiver comprises an LO switching pair and a folded transconductor. The mixer can be used as an upconversion or down conversion mixer and provides increased headroom and linearity, while still reducing current consumption. The mixer can be configured for differential inputs and outputs and the folded transconductor can comprises a MOSFET differential pair.

Abstract: An embodiment of this invention provides a circuit and method for reducing the number of electronic components needed to calibrate circuits on an IC. A multiplexer is located on the IC where the outputs of a plurality of circuits located on the IC are each connected to a separate data input of the multiplexer. The control input of the multiplexer selects which data input of the multiplexer is connected to an external component. Each data input is individually connected to the component periodically.

Abstract: The invention provides a current multiplexing circuit for time-domain multiplexing a plurality of current signals such as photocurrents that are received in a plurality of input terminals. The current signals are multiplexed using one or more analog low-resistance switches operational to connect each of the input terminals to an output switch terminal at a time in a selected sequence, while coupling the other input terminals and the output switch terminal to a reference potential such as ground. The current multiplexing circuit can be used in an optical power monitor with auto-calibration functionality for monitoring a plurality of optical signals.

Abstract: CMOS circuitry used to multiplex between data inputs suffers from high sensitivity to power supply noise, resulting in delay variations. By utilizing current controlled inverters in a multiplexer structure, power supply insensitivity can be achieved with either of two multiplexing methods. The first method places switches on the data inputs while the second places the switches on the analog bias voltages inherent to a current controlled inverter.

Abstract: A high-speed front-multiplexed multi-channel LVDS-compatible repeater circuit that limits input leakage current levels in the event one or more input voltages of the circuit exceeds the supply voltage. The LVDS repeater includes a multiplexor having a plurality of differential inputs and at least one differential output. The multiplexor includes a plurality of transmission gates to allow any one of the differential inputs to be routed to any differential output. Each transmission gate includes a first PMOS transistor and an NMOS transistor. The multiplexor further includes first Schottky diodes coupled between Vcc and the back-gate nodes of the first PMOS transistors, and second PMOS transistors coupled as shunts between the gate nodes of the first PMOS transistors and the source nodes of the NMOS transistors.

Abstract: A driving circuit for driving a capacitive load promptly to a target voltage is to have a broad dynamic range and achieve a high accuracy output and saving in the surface area with low power dissipation. A first period and a second period are provided in one data driving period. During the first period, a transistor amplifier for driving the load for charging, with a setting drive voltage (V1), and a transistor amplifier for driving the load for discharging, with a setting drive voltage (V2), with V1<V2, are both enabled for actuation and, during the second period, the transistor amplifier performing either the driving for charging or the driving for discharging, and a constant current source, performing the reverse of the operation of the transistor amplifier, are actuated, for driving the load to the target voltage.

Abstract: A selection circuit having a comparator with comparator inputs connected to first and second voltage inputs), respectively, and a comparator output connected to a control input of a first controllable switch and an inverter. The selection circuit also has a second controllable switch having a second control input connected to the inverter. The first voltage input is connectable to a selection circuit output by the first controllable switch and the second voltage input is connectable to the selection circuit output by the second controllable switch. The inverter has a power supply connector connected to the first voltage input and the comparator has a power supply connector connected to the second voltage input.

Abstract: An improved high-fanin multiplexer that is highly-scalable, fast and area-efficient. In one embodiment of the present invention, multiple logic “legs” are attached to a common output line. Each leg comprises one pMOS pull-up transistor and one nMOS pull-down transistor. The gate of the pMOS transistor in each leg is connected to the output of an And-Or-Invert (AOI) gate whose inputs are connected to a plurality of select lines and a plurality of data lines. The gate of the nMOS transistor in each leg is connected to the output of an Or-And-Invert (OAI) gate whose inputs are connected to a plurality of select lines (the logical complements of the select lines for the AOI), and a plurality of data input lines. The high-fanin multiplexer of the present invention offers numerous advantages over the prior art. In particular, the high-fanin multiplexer of the present invention has very small self-loading allowing a large number of inputs while also maintaining a high fan out speed.

Abstract: At least two inputs, at least one output and a clock source for the inputs are provided in a multiplexer. Each input balances an input signal and is coupled to a transistor circuit having two transistors with collectors commonly connected to a power potential. The transistor circuit can be supplied with a first balanced input signal on a first input signal path connected to the base of the first transistor, and with a second balanced input signal on a second input signal path connected to the base of the second transistor. The two balanced input signals are able to have a predetermined switching potential applied to them under the clocking of a driver circuit. In addition, two outgoing signal paths from the emitter of each transistor circuit can be combined to form at least two output signal paths for the at least one output. In this arrangement, the two output signal paths can be connected symmetrically with respect to a reference-ground potential.

Abstract: An apparatus for a multiplexor circuit includes a passgate circuit coupled to receive input signals and corresponding select signals comprising a subset of the input signals and select signals received by the multiplexor. The apparatus also includes a default circuit coupled to receive the select signals and coupled to an output node of the passgate circuit. If none of the select signals is asserted, the default circuit supplies a default voltage on the output node. Other passgate circuits and default circuits may be included coupled to other subsets of the input signals and select signals, and an output circuit may be included with inputs coupled to the output nodes of the passgate circuits. The default voltage may represent a logical value which allows the value from another passgate circuit to control the output of the output circuit.

Abstract: A multiplexer includes a first stage that has tri-state buffers each of which has split outputs and a final stage that has a tri-state buffer with an output. The multiplexer includes circuitry configured to enable or disable a signal at an input of a selected one of the first-stage buffers to propagate to the output of the final-stage buffer.

Abstract: A complementary output stage in integrated circuit includes a P-channel transistor (MP1) the segmented into a first group of sections (MP1-1,2 . . . 12) and an N-channel transistor (MN1) segmented into a second group of sections (MN1-1,2 . . . 12). The sections of the first group are disposed in a plurality of N-type well regions (35), respectively, and the sections of the second group are disposed in a plurality of P-type well regions (36), respectively. The sections of the first group are alternately located with respect to the sections of the second group so as to form an interdigitated output stage area of the integrated circuit including the P-channel transistor (MP1) and the N-channel transistor (MN1) so that the higher amount of heat normally generated in the N-channel transistor is dissipated over the entire interdigitated output stage area and reduces peak temperatures in the N-channel transistor.

Abstract: A Dual Rail Time Borrowing Multiplexer (DTBM) generates a dual rail output from a single rail input with a one gate equivalent delay using a negative set up time. In one embodiment, a multiplexer includes a cross-coupled differential domino circuit coupled to a transistor array and to a data input and an enable input through a first and second circuit. The multiplexer outputs a dual rail output corresponding to a selected data input with a one gate equivalent delay using a negative set up time.

Abstract: A high speed static multiplexer comprising: (1) a plurality of data inputs and at least one select input; (2) an output; (3) a high voltage rail and a low voltage rail; (4) a pull-up circuit coupled between the output and the high voltage rail and further coupled to receive the data inputs and the select input so that the pull-up circuit generates a first logic state at the output in response to the selected data input having that first logic state; (5) and a pull-down circuit coupled between the output and the low voltage rail and further coupled to receive the data inputs and the select input, so that the pull-down circuit generates a second logic state at the output in response to the selected data input having that second logic state.

Abstract: An apparatus comprising an input section and an output section. The input section may be configured to generate a first control signal and a second control signal in response to an input signal and a select signal. The output section may be configured to generate an output signal in response to the first and second control signals. The output signal may be (i) related to the input signal when in a first mode and (ii) disabled when in a second mode.

Abstract: Disclosed herewith is a semiconductor integrated circuit provided with a differential input circuit that can transmit data signals fast to an internal circuit free from distortion of their waveforms without increasing the subject chip in size. The differential input circuit is provided with a pair of first differential input transistors used to amplify mainly the low frequency components of those input signals and having gate terminals connected to a pair of input terminals that receive inputs of differential signals respectively, as well as a pair of second differential input transistors used mainly to amplify high frequency components of those input signals and having control terminals connected to a pair of input terminals that receive inputs of differential signals respectively through capacitance elements. The pairs of first and second differential transistors are connected to each other through a differential connection point (common source).

Abstract: A circuit configuration for supplying voltage to an integrated circuit via a pad that is connected to the input of a Schmitt trigger on the integrated circuit. The pad is also provided for configuring the integrated circuit. The integrated circuit has a multiplicity of voltage supply lines for voltage supply purposes. According to the invention, the pad is connected to a respective voltage supply line via a respective switch, and the switches are switched on or off by a control circuit that is controlled by at least one on-chip control signal.

Abstract: A digital electronic circuit having first and second sections. The first section is adapted to transmit one of N input signals. The second section is adapted to receive the signal transmitted by the first section and one or more control signals. The second section is configured to output either an inverse of the signal transmitted by the first section or a logical 0, or to output either an inverse of the signal transmitted by the first section or a logical 1. The second section also may be selectively configurable.

Abstract: A four-to-one multiplexer circuit constructed purely in CMOS technology and fabricated using only pass-gates and inverters. The resulting multiplexer is simpler to fabricate and operates faster than known similarly fabricated and constructed CMOS multiplexers.

Abstract: The present invention discloses a multiplexer including that provides an output signal having a voltage range substantially equal to an input signal. The multiplexer further provides a breakdown prevention device that protects elements connected to an output terminal. The multiplexer can be used in an LCD driver or the like. The multiplexer according to the present invention can include a first switching circuit that receives a first input signal, a second switching circuit that receives a second input signal, wherein the first and second switching circuits are complementarily enabled in response to a three control signals, a third switching circuit that receives the first input signal switched from the first switching circuit and a fourth switching circuit that receives the second input signal switched from the second switching circuit. The third and fourth switching circuits are complementarily enabled by a selection signal to provide one of the first and second input signals to the output terminal.

Abstract: A bridge circuit uses active feedback to control drive phase turn on to substantially eliminate shoot-through current. Voltage sensor 66 senses H-bridge transistor voltage turn off levels and causes control circuit 64 to latch which causes enable circuit 62 to allow the next phase of H-bridge transistor turn on. A critical aspect of the invention is to ensure all H-bridge transistors are off before the enable circuit allows the next phase to turn any H-bridge transistors on.

Abstract: The selector circuit is particularly well suited to the switching over of two voltages VPP1 and VPP2, greater than the supply voltage Vcc of an integrated circuit without a priori knowledge of which of the two voltages is the highest. The selector circuit includes first and second switch circuits coupled by first and second MOS transistors whose well is biased by the output voltage of the selector circuit.

Abstract: A multiplexer has first, second, third and fourth inputs receiving respective first, second, third and fourth input signals, having first and second control inputs receiving respective first and second select input signals and an output. Each of the four input signals is supplied to the input of a CMOS transmission gate. The first and second transmission gates are clocked via the first select signal and its inverse in a first phase. The third and fourth transmission gates are clocked via the first select signal and its inverse in a second phase, opposite to the first phase. A first embodiment includes a first intermediate inverter having an input connected jointly to the outputs of the first and second transmission gates and a second intermediate inverter having an input connected jointly to the outputs of the third and fourth transmission gates.

Abstract: A multiplexer selectively connects one of first and second nodes to a third node. The multiplexer includes a first switch coupled between the first and third nodes, a second switch coupled between the second and third nodes, and a control input for receiving a signal to either open the first switch and close the second switch or open the second switch and close the first switch. Additionally, a delay circuit, coupled to the control input and the second switch, delays closure of the second switch until the first switch is open. In a preferred embodiment, the delay circuit includes two field-effect transistors having substantially different width-to-length ratios.

Abstract: A system of encoding a plurality of logic paths. A number of logic paths are subdivided into groups of N, N being greater than one. Each group of N logic paths is encoded such that an assertion of a given combination of the N logic paths results in a predetermined one out of 2.sup.N signal lines being asserted. Simultaneous assertion of more than one of the 2.sup.N signal lines is defined as an invalid state. A simultaneous non-assertion of all of the 2.sup.N signal lines enables precharging of the signal lines for dynamic operation. 1-of-2.sup.N encoding enables transmission of N variables by firing one out of N wires (rather than every wire, as in static logic, or one out of two wires, as in mousetrap logic). Signal degradation due to noise and coupling is reduced. In a multiplexer, 1-of-2.sup.N encoding reduces the load on the multiplexer's shift lines. Several 1-of-2.sup.

Abstract: A semiconductor integrated circuit device has a data selecting circuit connected to a first power supply terminal, a precharge circuit, connected to a second power supply terminal, for receiving a precharge signal, and a wiring line connected to a common connection point between the data selecting circuit and the precharge circuit. The data selecting circuit includes at least two, i.e., first and second data transmission circuits. A first input data signal and a first selecting signal are supplied to the first data transmission circuit. A second input data signal and a second selecting signal are supplied to the second data transmission circuit.

Abstract: A substrate clamp for non-isolated integrated circuits is disclosed. The substrate clamp comprises a circuit that controls the voltage on a substrate so that the substrate is connected to a specific node if the parasitic PN diodes at all the circuit nodes are not forward biased. If a specific node is then forced with an applied voltage to forward bias, the substrate is disconnected from its original node and maintains itself at a forward biased diode voltage drop away from the powered node. Various embodiments are disclosed. In one embodiment of the invention, a set of bipolar transistors which utilize the substrate as a common base, is implemented. The emitters of these transistors are connected to a set of nodes which may be driven to voltages outside the range between that provided by the power supply and ground, or any other pair of applied voltages. The collectors of these bipolar transistors are connected together.

Abstract: Output signals from a plurality of self reset CMOS a logic circuits are multiplexed by means of the plurality of input multiplex circuits and an output circuit. The multiplex circuits are individually enabled by means of a select lead and true and complement input signals to the multiplex circuits are supplied to input terminals of an output circuit in which the state of the true or complement input is latched to provide a static output. The inputs to the output circuits simultaneously provide an output and initiate the setting of the latch by means of a separate latch setting gate. An inverter tree within the output circuit maintains the state of the output on the output terminal of the output circuit after the latch has been reset. A test access to the output circuit allows a test signal to be gated into a test latch and subsequently gated into the primary latch of the output circuit to provide a test output.

Abstract: An integrated circuit having system logic with programmable elements, decoding logic coupled to the programmable elements for addressing the programmable elements and a plurality of input/output buffer circuits for passing signals between the system logic and the exterior of the integrated circuit through input/output terminals is disclosed. Each input/output buffer circuit comprises an output driver stage having an output terminal connected to an input/output terminal; and a plurality of cells, each cell having a multiplexer, a flip-flop connected to an output terminal of the first multiplexer for storing a signal from the first multiplexer, a latch connected to an output terminal of the flip-flop for storing a signal from the flip-flop, and a second multiplexer connected to an output terminal of the latch.

Abstract: A CMOS motor drive for a disk drive spindle motor. The design of the drive circuit permits the integration of power electronics together with logic or other circuitry on a single integrated circuit wafer. For each motor phase the power electronics formed on the integrated circuit wafer includes a plurality of P-type and N-type MOSFET power transistor pairs and a plurality of corresponding output bonding pads; the drain terminals of each transistor pair being connected together to its corresponding output bonding pad. The wafer is enclosed in packaging which includes an output pin for providing an electrical connection to one phase of the disk drive spindle motor, and a plurality of bond wires corresponding to the plurality of output bonding pads, each bond wire providing an electrical connection between its corresponding bonding pad and the output pin. The transistor pairs and bond wires operate in parallel, each carrying an equivalent portion of the total current output presented at the output pin.