Mesfet (i.e., Metal Semiconductor Field-effect Transistor) Patents (Class 327/431)
  • Patent number: 9621155
    Abstract: A switching circuit includes a normally-on switch, a normally-off switch, a current compensating unit and a current sharing unit. Each of the normally-on switch and the normally-off switch include a first terminal, a second terminal and a control terminal respectively. The first terminal of the normally-off switch is connected to the second terminal of the normally-on switch. The second terminal of the normally-off switch is connected to the control terminal of the normally-on switch. The current compensating unit is connected to the normally-on switch and configured to generate a compensating current when a leakage current of the normally-on switch is smaller than the leakage current of the normally-off switch. The current sharing unit is connected to the normally-off switch and configured to share the leakage current of the normally-on switch when the leakage current of the normally-on switch is larger than the leakage current of the normally-off switch.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: April 11, 2017
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chang-Jing Yang, Li-Fan Lin
  • Patent number: 9367794
    Abstract: A calibrated gate biasing circuit according to one embodiment includes a switched capacitor precision resistor; and a voltage reference. An electronic circuit for initiating a change in state of a host device, according to another embodiment, includes a counter coupled to a host device, the counter counting at a fixed interval, wherein the counter is reset to zero upon receiving a command from a remote device, wherein the count is compared to a reference value, wherein the host device changes states if the count matches the reference value, wherein operation of the counter continues in spite of an interruption in power supply from a power source. Asymmetrical differential amplifiers are also disclosed, according to various embodiments.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: June 14, 2016
    Assignee: Intelleflex Corporation
    Inventor: Roger Green Stewart
  • Patent number: 8729739
    Abstract: A circuit breaker comprising first and second JFETs, each comprising a gate, drain and source connection, the JFETs sources being operatively connected to each other to form a common-source connection and adapted to be connected to and operating to open an external circuit when the current flowing through the JFETs exceeds a predetermined threshold, the JFETs' gates, and common-source connection being operatively connected to a gate driver circuit which causes the JFETs to turn off when the predetermined threshold is exceeded; whereupon the current flows through the common-source connection into the second gate and into the gate driver circuit which causes the gate driver circuit to turn off the first and second JFETs and open the circuit breaker. Also claimed is a method of sensing an overloaded circuit comprising leading and trailing JFETs in a circuit that open the circuit and prevent current flow when a predetermined threshold is exceeded.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: May 20, 2014
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Vadim Lubomirsky, Damian Urciuoli
  • Patent number: 8536931
    Abstract: Power switch devices for high-speed applications are disclosed. The power switch device includes a depletion mode field effect transistor (D-FET), an enhancement mode field effect transistor (E-FET) and a bipolar transistor. In one embodiment, the E-FET is coupled in cascode with the D-FET such that turning off the E-FET turns off the D-FET and turning on the E-FET turns on the D-FET. Furthermore, the bipolar transistor is operably associated with the D-FET and the E-FET such that turning on the bipolar transistor drives current from the D-FET through the bipolar transistor to the E-FET to provide a charge that turns on the E-FET. The bipolar transistor provides several advantages such as a higher Schottky breakdown voltage for the E-FET and faster current switching speed for the power switch device.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: September 17, 2013
    Assignee: RF Micro Devices, Inc.
    Inventors: Kevin W. Kobayashi, Joseph Johnson
  • Patent number: 8519442
    Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer, a two-dimensional carrier gas layer, a first main electrode, a second main electrode, a first gate electrode, and a second gate electrode. The first gate electrode is provided between a part of the first main electrode and a part of the second main electrode opposite to the part of the first main electrode. The second gate electrode is provided between another part of the first main electrode and another part of the second main electrode opposite to the another part of the first main electrode with a separation region interposed between the first gate electrode and the second gate electrode. The second gate electrode is controlled independently of the first gate electrode.
    Type: Grant
    Filed: October 3, 2011
    Date of Patent: August 27, 2013
    Assignee: Sanken Electric Co., Ltd.
    Inventors: Akio Iwabuchi, Hironori Aoki
  • Patent number: 8205104
    Abstract: A power supply control circuit for a motherboard of a computer is provided. The power supply control circuit includes a south bridge chip and a voltage output control circuit connected to the south bridge chip. The south bridge chip includes a control pin and a detecting pin. The voltage output control circuit has a voltage input terminal and a voltage output terminal. The voltage output control circuit includes a transistor connected to the voltage input terminal and also connected to the voltage output terminal via a switch component. The voltage output terminal is connected to the detecting pin of the south bridge chip via a super I/O chip. The transistor is capable of controlling the switch component to transmit a high level voltage to the super I/O chip when the computer is shut down. A method is also provided.
    Type: Grant
    Filed: December 9, 2009
    Date of Patent: June 19, 2012
    Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventor: Ke-You Hu
  • Patent number: 8179188
    Abstract: A method for operating a semiconductor device including a lateral double diffused metal oxide semiconductor (LDMOS) with a first source, a common drain and a first gate, a junction field effect transistor (JFET) with a second source, the common drain and a second gate wherein the second source is electrically connected to the first gate and an inner circuit electrically connected to the first source is provided. The first source provides the inner circuit with an inner current to generate an inner voltage by means of the lateral double diffused metal oxide semiconductor, and the lateral double diffused metal oxide semiconductor turns off when the inner voltage is elevated substantially as high as the first gate voltage.
    Type: Grant
    Filed: October 27, 2011
    Date of Patent: May 15, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Sung-Nien Tang, Wei-Lun Hsu, Ching-Ming Lee, Te-Yuan Wu
  • Patent number: 8130023
    Abstract: A system and method for providing symmetric, efficient bi-directional power flow and power conditioning for high-voltage applications. Embodiments include a first vertical-channel junction gate field-effect transistor (VJFET), a second VJFET, a gate drive coupled to the first VJFET gate and the second VJFET gate. Both VJFETs include a gate, drain (D1 and D2), and a source, and have gate-to-drain and gate-to-source built-in potentials. The first VJFET and the second VJFET are connected back-to-back in series so that the sources of each are shorted together at a common point S. The gate drive applies an equal voltage bias (VG) to both the gates. The gate drive is configured to selectively bias VG so that current flows through the VJFETs in the D1 to D2 direction, flows through the VJFETs in the D2 to D1 direction or voltages applied to D1 of the first VJFET or D2 of the second VJFET are blocked.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: March 6, 2012
    Assignee: Northrop Grumman Systems Corporation
    Inventor: John V. Veliadis
  • Patent number: 7930570
    Abstract: An exemplary power supply control circuit includes a first electric switch, a second electric switch, a third electric switch, a power supply, and an output terminal. The first electric switch has a first terminal connected to an SIO chip to receive a control signal. When the control signal is at a high level, the first electric switch is turned on, the second electric switch is turned off, the third electric switch is turned off, and the output terminal outputs no power supply. When the control signal is at a low level, the first electric switch is turned off, the second electric switch is turned on, the third electric switch is turned on, and the output terminal outputs the power supply.
    Type: Grant
    Filed: August 8, 2008
    Date of Patent: April 19, 2011
    Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventors: Hua Zou, Feng-Long He
  • Publication number: 20100026371
    Abstract: A switching device for switching a high operating voltage is described. The switching device-includes a first switching arrangement with a first self-conducting switching element), which has a control connector and a first and second main connector for forming a switching section. The switching device may include a second switching arrangement having a first and a second connector for forming a switching section, which is wired serially in respect to the switching section of the first switching arrangement. The second switching arrangement includes an optically triggerable switching element for switching the switching section of the second switching arrangement so it becomes conductive. The second connector of the second switching arrangement is connected with the control connector of the first self-conducting switching element.
    Type: Application
    Filed: July 27, 2009
    Publication date: February 4, 2010
    Inventors: Thomas Komma, Norbert Seliger
  • Patent number: 7619462
    Abstract: A novel RF switch for switching radio frequency (RF) signals is disclosed. The RF switch may comprise both enhancement and depletion mode field-effect transistors (E-FETs and D-FETs) implemented as a monolithic integrated circuit (IC) on a silicon-on-insulator (SOI) substrate. The disclosed RF switch, with a novel bleeder circuit, may be used in RF applications wherein a selected switch state and performance are required when the switch and bleeder circuits are not provided with operating power (i.e., when the switch and bleeder circuits are “unpowered”).
    Type: Grant
    Filed: February 9, 2006
    Date of Patent: November 17, 2009
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Dylan J. Kelly, Clint L. Kemerling
  • Patent number: 7446591
    Abstract: A switching circuit uses multiple common-drain JFETs to serve as the low-side switches of the switching circuit, and each of the low-side JFET is coupled between a high-side switch and a power node. Since a JFET can endure high voltage at both drain side and source side, and has good heat dissipation capability at drain side, the drain of the low-side JFET is coupled to the power node to enhance the heat dissipation capability and accordingly, all the low-side JFETs are allowed to be packaged in a same package to reduce the PCB layout area.
    Type: Grant
    Filed: July 3, 2007
    Date of Patent: November 4, 2008
    Assignee: Richtek Technology Corp.
    Inventors: Liang-Pin Tai, Jiun-Chiang Chen
  • Publication number: 20080265980
    Abstract: A gate drive circuit for a wide bandgap semiconductor junction gated transistor includes a gate current limit resistor. The gate current limit resistor is coupled to a gate input of the wide bandgap semiconductor junction gated transistor when in use and limits a gate current provided to the gate input of the junction gated transistor. An AC-coupled charging capacitor is also included in the gate drive circuit. The AC-coupled charging capacitor is coupled to the gate input of the wide bandgap semiconductor junction gated transistor when in use and is positioned parallel to the gate current limit resistor. A diode is coupled to the gate current limit resistor and the AC-coupled charging capacitor on one end and an output of a gate drive chip on the other end When in use, the diode lowers a gate voltage output from the gate drive chip applied to the gate input of the wide bandgap semiconductor junction gated transistor through the gate current limit resistor.
    Type: Application
    Filed: April 30, 2007
    Publication date: October 30, 2008
    Inventors: John Vincent Reichl, David Everett Bulgher, Ty R. McNutt
  • Publication number: 20080197908
    Abstract: A cascode power switch for use in a MESFET based switching regulator includes a MOSFET in series with a normally-off MESFET. The cascode power switch is typically connected in between a power source and a node Vx. The node Vx is connected to an output node via an inductor and to ground via a Schottky diode or a second MESFET or both. A control circuit drives the MESFET (and the second MESFET) so that the inductor is alternately connected to the battery and to ground. The MOSFET is switched off during sleep or standby modes to minimize leakage current through the MESFET. The MOSFET is therefore switched at a low frequency compared to the MESFET and does not contribute significantly to switching losses in the converter.
    Type: Application
    Filed: February 16, 2008
    Publication date: August 21, 2008
    Applicant: ADVANCED ANALOGIC TECHNOLOGIES, INC.
    Inventor: Richard K. Williams
  • Publication number: 20080186004
    Abstract: A MESFET based boost converter includes an N-channel MESFET connected to a node Vx. An inductor connects the node Vx to a battery or other power source. The node Vx is also connected to an output node via a Schottky diode or a second MESFET or both. A control circuit drives the MESFET (and the second MESFET) so that the inductor is alternately connected to ground and to the output node. The maximum voltage impressed across the low side MESFET is optionally clamped by a Zener diode. In some implementations, the MESFET is connected in series with a MOSFET. The MOSFET is switched off during sleep or standby modes to minimize leakage current through the MESFET. The MOSFET is therefore switched at a low frequency compared to the MESFET and does not contribute significantly to switching losses in the converter. In other implementations, more than one MESFET is connected in series with a MOSFET, the MOSFETs being switched off during periods of inactivity to suppress leakage currents.
    Type: Application
    Filed: January 26, 2006
    Publication date: August 7, 2008
    Applicant: ADVANCED ANALOGIC TECHNOLOGIES, INC.
    Inventor: Richard K. Williams
  • Patent number: 7326962
    Abstract: The present invention provides a unit cell of a metal-semiconductor field-effect transistor (MESFET). The unit cell of the MESFET includes a source, a drain and a gate. The gate is disposed between the source and the drain and on an n-type conductivity channel layer. A p-type conductivity region is provided beneath the source and has an end that extends towards the drain. The p-type conductivity region is spaced apart from the n-type conductivity channel region and is electrically coupled to the source. An n-type conductivity region is provided on the p-type conductivity region beneath the source region and extending toward the drain region without extending beyond the end of the p-type conductivity region. Related methods of fabricating MESFETS are also provided.
    Type: Grant
    Filed: December 15, 2004
    Date of Patent: February 5, 2008
    Assignee: Cree, Inc.
    Inventor: Saptharishi Sriram
  • Patent number: 7274246
    Abstract: A switching circuit uses multiple common-drain JFETs to serve as the low-side switches of the switching circuit, and each of the low-side JFET is coupled between a high-side switch and a power node. Since a JFET can endure high voltage at both drain side and source side, and has good heat dissipation capability at drain side, the drain of the low-side JFET is coupled to the power node to enhance the heat dissipation capability and accordingly, all the low-side JFETs are allowed to be packaged in a same package to reduce the PCB layout area.
    Type: Grant
    Filed: June 23, 2005
    Date of Patent: September 25, 2007
    Assignee: Richtek Technology Corp.
    Inventors: Liang-Pin Tai, Jiun-Chiang Chen
  • Patent number: 7173471
    Abstract: Four switching circuit sections consisting of four FETs connected in series are provided between a plurality of input/output terminals which output and input a high frequency signal. Gate control voltages are individually applied to gate terminals of four FETs, respectively, so that an on-state and an off-state are achieved. Further drain control voltages are individually applied to drain terminals or source terminals of the FET in each switching circuit section, and a voltage according to an electric power value of the high frequency signal supplied to each of switching circuit sections is supplied as the gate control voltage and the drain control voltage.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: February 6, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tadayoshi Nakatsuka, Atsushi Suwa, Katsushi Tara
  • Patent number: 7145379
    Abstract: The first and second chips are provided side by side. The first chip includes: a current supply section for outputting a drive current, the current supply section including a current mirror; a current distribution MISFET; a current input MISFET for transmitting an electric current to the current supply section, the current input MISFET being connected to the current distribution MISFET; and a second current distribution MISFET. The current distribution MISFET and the second current distribution MISFET constitute a current mirror. The second chip includes a second current input MISFET which is connected to the second current distribution MISFET. The ratio between the W/L ratio of the current distribution MISFET and the W/L ratio of the current input MISFET connected thereto is the same in the first and second chips.
    Type: Grant
    Filed: April 2, 2004
    Date of Patent: December 5, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshito Date, Tetsuro Omori, Shiro Dosho, Makoto Mizuki
  • Patent number: 6535050
    Abstract: A hybrid power MOSFET having a low blocking-capability MOSFET and a high blocking-capability junction FET is disclosed. In accordance with the present invention, this cascode circuit has at least two high blocking-capability junction FETs which are electrically connected in parallel and whose gate connections are respectively electrically conductively connected to the source connection of the low blocking-capability MOSFET by means of a connecting line. Thus, a hybrid power MOSFET for a high current-carrying capacity is obtained whose design technology has been considerably simplified on account of the use of only one control line and n+1 chips.
    Type: Grant
    Filed: July 23, 2001
    Date of Patent: March 18, 2003
    Assignee: Siemens Aktiengesellschaft
    Inventors: Eric Baudelot, Manfred Bruckmann, Heinz Mitlehner, Benno Weis
  • Patent number: 6218891
    Abstract: An integrated circuit including a metal-semiconductor field-effect transistor (MESFET) having a nominal intrinsic capacitance and requiring a negative voltage to bias the MESFET into a non-conduction state, a method of driving the MESFET and a power converter employing the integrated circuit and method. In one embodiment, the integrated circuit includes a driver including a bias capacitor integrated with the MESFET. The driver is configured to apply a positive voltage to bias the MESFET into a conduction state, and apply the negative voltage to bias the MESFET into the non-conduction state without employing an external negative bias source.
    Type: Grant
    Filed: July 28, 2000
    Date of Patent: April 17, 2001
    Assignee: Lucent Technologies Inc.
    Inventors: Ashraf W. Lotfi, Allen F. Rozman, Jian Tan, Wei Tang
  • Patent number: 6218890
    Abstract: A switching circuit device including a multi-gate field effect transistor having a plurality of gate electrodes between a drain electrode and a source electrode, a low resistor having its one end connected between the gate electrodes, and a high resistor connected between the other end of the low resistor and any one of the drain electrode, the source electrode and the end of the other low resistor.
    Type: Grant
    Filed: July 12, 1999
    Date of Patent: April 17, 2001
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tsutomu Yamaguchi, Seiichi Banba, Tetsuro Sawai, Hisanori Uda
  • Patent number: 6163689
    Abstract: An improved mixing circuit includes a MESFET having an LO signal coupled to its gate through a charging capacitor and an RF signal coupled to its drain through a first bandpass filter. Electrons are pumped onto the charging capacitor to bias the gate of the MESFET. The MESFET drain is coupled to a second bandpass filter which passes a signal at the mixed frequency.
    Type: Grant
    Filed: September 30, 1997
    Date of Patent: December 19, 2000
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yong Hee Lee
  • Patent number: 6130570
    Abstract: A biasing system for an FET utilizes a source biasing capacitor which is charged to a positive DC ground voltage relative to RF ground. The gate of the FET is thus biased negative to the source without requiring a negative power supply.
    Type: Grant
    Filed: September 18, 1997
    Date of Patent: October 10, 2000
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eric Ting-Shan Pan, Roger Lee Foust
  • Patent number: 5945867
    Abstract: A first FET is connected between first and third nodes, a second FET is connected between second and fourth nodes, a third FET is connected between third and fifth nodes and a fourth FET is connected between fourth and fifth nodes. A fifth FET is connected between first and sixth nodes and a sixth FET is connected between second and sixth nodes. The gates of the first, fourth and sixth FETs are connected to a first control terminal and the gates of the second, third and fifth FETs are connected to a second control terminal. A power-supply terminal is connected to the fifth and sixth nodes. The first and second nodes are connected to a common terminal through first and second capacitors, respectively. The fifth and sixth FETs form a pull-up switching circuit. The pull-up switching circuit pulls up the source of an FET in an OFF state to the power-supply voltage and isolates the source of an FET in an ON state from the power-supply voltage.
    Type: Grant
    Filed: February 23, 1998
    Date of Patent: August 31, 1999
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hisanori Uda, Keiichi Honda
  • Patent number: 5900768
    Abstract: The present invention relates to a circuit that pulls down the power supply line in an electronic system to a low state when the electronic system is turned off. More specifically, the present invention is an active circuit that establishes a low impedance between a power supply line and a return line when a system's power is turned off, and establishes a high impedance between a power supply line and a return line when the system is turned on.
    Type: Grant
    Filed: November 17, 1997
    Date of Patent: May 4, 1999
    Assignee: Compaq Computer Corp
    Inventor: Kyle J. Price
  • Patent number: 5812011
    Abstract: A current switching circuit in an integrated semiconductor circuit includes a load connected to a positive power supply; a first pnp bipolar transistor having a collector electrode connected to the load, and a base electrode connected to a DC bias source and an emitter electrode; and a first n channel MOS transistor having a drain electrode connected to the emitter electrode of the first npn bipolar transistor, a source electrode connected to the ground, and a gate electrode connected to an input terminal, the first MOS transistor turning on and off in response to a voltage applied to the input terminal.
    Type: Grant
    Filed: February 6, 1997
    Date of Patent: September 22, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yutaka Hayashi, Takehiko Umeyama
  • Patent number: 5805014
    Abstract: The present invention relates to a circuit that pulls down the power supply line in an electronic system to a low state when the electronic system is turned off. More specifically, the present invention is an active circuit that establishes a low impedance between a power supply line and a return line when a system's power is turned off, and establishes a high impedance between a power supply line and a return line when the system is turned on.
    Type: Grant
    Filed: March 1, 1996
    Date of Patent: September 8, 1998
    Assignee: Compaq Computer Corporation
    Inventor: Kyle J. Price
  • Patent number: 5723996
    Abstract: An integratable reversing switch selectively imposes a ground potential or a supply potential being positive relative thereto upon a terminal of a load having another terminal being connected to a supply potential that is negative relative to the ground potential. A first switch is connected between the load and the positive supply potential. A second switch is controlled in complementary fashion thereto and is connected between the load and the ground potential. The second switch is formed by an inversely operated DMOS field effect transistor.
    Type: Grant
    Filed: February 12, 1996
    Date of Patent: March 3, 1998
    Assignee: Siemens Aktiengesellschaft
    Inventor: Bernhard Zojer
  • Patent number: 5554892
    Abstract: A high frequency power amplifier is implemented by a GaAs FET and is supplied with a positive and a negative power supply. The amplifier amplifies the power of an input signal and delivers the amplified signal to a high frequency switch. The high frequency switch is supplied switch control voltages in the form of the positive and negative voltages. Since the switch control voltages are implemented as the positive and negative voltages, a great difference in level between the switch control voltages is achievable which improves insertion loss. While the high frequency switch may also be implemented by GaAs FETs, the insertion loss will be further reduced if the negative voltage is applied to the high frequency switch only during transmission. In this case, current consumption will also be reduced if the generation of the negative voltage is controlled at the negative voltage source side.
    Type: Grant
    Filed: April 28, 1994
    Date of Patent: September 10, 1996
    Assignee: NEC Corproation
    Inventor: Hidehiko Norimatsu
  • Patent number: 5554954
    Abstract: A power supply circuit disclosed herein includes a three-terminal regulator for stabilizing a positive voltage applied thereto, a voltage converter for converting the stabilized voltage into a negative voltage, a power-supply section for stabilizing a voltage by a light-emitting diode, and a control circuit for applying a bias voltage across a drain and source of a GaAs FET amplifier only when a voltage is being applied across the gate and source of the amplifier. When power is introduced from a power supply, the presence of the negative voltage supplied from the voltage converter is sensed by the control circuit and a bias begins to be applied to the gate. Therefore, when it is sensed that a predetermined voltage is applied to the gate, a bias begins to be applied to the drain of the FET thereafter. When power from the power supply is cut off, a drop in voltage is sensed and the drain bias begins being cut off while the gate bias for the FET is cut off thereafter.
    Type: Grant
    Filed: December 14, 1994
    Date of Patent: September 10, 1996
    Assignee: NEC Corporation
    Inventor: Hideaki Takahashi
  • Patent number: 5517150
    Abstract: An analog switch includes first and second thin film field effect transistors having their gate connected in common to a control terminal. Current paths of the first and second thin film field effect transistors are connected in series between an input terminal and a capacitive load. A voltage adjusting capacitive element is connected to a common connection between the current paths of the first and second thin film field effect transistors.
    Type: Grant
    Filed: October 1, 1992
    Date of Patent: May 14, 1996
    Assignee: NEC Corporation
    Inventor: Fujio Okumura
  • Patent number: 5497118
    Abstract: The invention is intended to offer a signal selector circuit and a signal-generating circuit which are excellent in linearity between input and output signals at high frequencies and in isolation between input signals and isolation between output signals and which do not produce distortion. When an output signal is taken from OUT.sub.1, a circuit connected with the gate terminal of Q.sub.11 is made to have a high impedance, and a cutoff voltage deeper than the pinchoff voltage is applied to the gate of Q.sub.12. With respect to each of Q.sub.11, Q.sub.12, the gate is connected with the source by R.sub.11 or R.sub.12. Both Q.sub.11 and Q.sub.12 have depletion characteristics. The resistances of R.sub.11 and R.sub.12 are lower than the impedances of Q.sub.15 and Q.sub.16 when they drive the gates so as to turn on Q.sub.11 and Q.sub.12. In this case, therefore, the voltage between the gate and the source of Q.sub.11 is made null and Q.sub.11 conducts. Q.sub.12 is cut off.
    Type: Grant
    Filed: July 19, 1993
    Date of Patent: March 5, 1996
    Assignee: Hewlett-Packard Company
    Inventors: Toshiaki Ueno, Shigeru Nakagawa
  • Patent number: 5396132
    Abstract: An FET mixer circuit having a stable input impedance uses two tandem-connected GaAs MESFET's (1) and (2) of pulse doped structure instead of a conventional MESFET or a HEMT, as an active device. A gate biasing point for the FET (1) is set around a pinch-off point of a mutual conductance, and a gate biasing point for the FET (2) is set in a region which assures non-change of a mutual conductance with respect to the increase of a gate voltage. Thus, a mixer circuit having a good isolation characteristic for an RF signal and a local oscillation signal and exhibits substantially no change in the input impedance is attained.
    Type: Grant
    Filed: March 2, 1993
    Date of Patent: March 7, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Nobuo Shiga