Jfet (i.e., Junction Field-effect Transistor) Patents (Class 327/430)
  • Patent number: 10700646
    Abstract: pHEMT-based switch circuits, devices including same, and methods of improving the linearity thereof. In one example, an antenna switch module includes a pHEMT switching circuit connected in series between an input signal terminal and a load terminal, the pHEMT switching circuit including at least one pHEMT configured to produce a first harmonic signal at the load terminal responsive to being driven by an input signal of a fundamental frequency received at the input signal terminal, the first harmonic signal having a first phase, and a gate resistance circuit connected to a gate of the at least one pHEMT and having a resistance value selected to produce a second harmonic signal at the load terminal, the second harmonic signal having a second phase opposite to the first phase.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: June 30, 2020
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Fikret Altunkilic, Haki Cebi, Yu Zhu, Cejun Wei, Jerod F. Mason
  • Patent number: 10270366
    Abstract: A configuration and a method for generating a negative voltage for a high-side switch in an inverter by providing at least one negative bias voltage for an inverter, wherein a simple and safe provision of the negative voltage becomes possible, and the switching costs as well as the costs and expenses for the production of such an inverter are reduced. A secondary winding generating a negative base voltage is arranged on a flyback transformer, wherein a first terminal of the secondary winding is connected to the HV+ potential and a second terminal of the secondary winding is connected via a rectifier diode to the first terminal for outputting the negative base voltage, wherein a bootstrap diode is arranged between the first terminal and a second terminal for outputting a negative base voltage (NEG BIAS A), and wherein a bootstrap capacitor is arranged between the first terminal and the second terminal.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: April 23, 2019
    Assignee: HANON SYSTEMS
    Inventors: Stephen J. Newton, Stephan Werker, Philipp Karutz
  • Patent number: 10200023
    Abstract: A switch control circuit includes: a clock generating circuit that generates one or more periodic signals having a predetermined cycle; a clock adjusting circuit that generates one or more control signals by adjusting a bias voltage of the one or more periodic signals and changing an ON period of the one or more periodic signals; and at least one switching circuit including one or more switches that are switched to ON if respective amplitudes of the generated one or more control signals is equal to or higher than a threshold value and that are switched to OFF if the respective amplitudes of the generated one or more control signals is less than the threshold value.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: February 5, 2019
    Assignee: PANASONIC CORPORATION
    Inventor: Yohei Morishita
  • Patent number: 10135438
    Abstract: The invention relates to a Radio Frequency System and method. A Radio Frequency (RF) system comprising a RF switch comprising a plurality of transistor switching elements implemented on Silicon on Insulator (SOI) for switching at least one or more RF signals and said SOI comprises a bulk substrate region and a buried oxide region. At least one filter is adapted to isolate the RF signal from the substrate and/or other high frequency signals or control signals present in the RF system. There is also provided a coupling capacitor adapted to cooperate with the filter to improve linearity of the transistor switch elements.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: November 20, 2018
    Assignee: FERFICS LIMITED
    Inventors: Eugene Heaney, John O'Sullivan, Stephen Kenney
  • Patent number: 10128829
    Abstract: Provided is a composite semiconductor device that has a low on-resistance and a high load-short-circuit resistance. In a composite semiconductor device (10) including a normally-on first FET (Q1) and a normally-off second FET (Q2) that are cascode-connected to each other. In a case where a voltage applied to a drain of the first FET (Q1) is 400 V, a relation of the following expression is satisfied: [ Math .
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: November 13, 2018
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Akio Nakajima, Hisao Ichijoh
  • Patent number: 9748941
    Abstract: Provided is a stabilizing circuit structure using a sense field effect transistor (sense-FET). A power semiconductor module includes a depletion-mode field effect transistor (D-mode FET) and the sense FET that has same structure as the D-mode FET and varies in area. Also the power semiconductor module includes not only an enhancement-mode field effect transistor (E-mode FET), but also the stabilizing circuit including circuit elements such as a resistor, a capacitor, an inductor, or a diode.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: August 29, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Minki Kim, Hyun-Gyu Jang, Dong Yun Jung, Sang Choon Ko, Hyun Soo Lee, Chi Hoon Jun
  • Patent number: 9748242
    Abstract: A semiconductor device is provided that includes a composite semiconductor body including a high voltage depletion-mode transistor and a low voltage enhancement-mode transistor. The high voltage depletion-mode transistor is stacked on the low voltage enhancement-mode transistor so that an interface is formed between the high voltage depletion-mode transistor and the low voltage enhancement-mode transistor. The low voltage enhancement-mode transistor includes a current path coupled in series with a current path of the high voltage depletion-mode transistor, and a control electrode is arranged at the interface.
    Type: Grant
    Filed: January 18, 2016
    Date of Patent: August 29, 2017
    Assignee: Infineon Technologies Austria AG
    Inventor: Franz Hirler
  • Patent number: 9705489
    Abstract: A cascode transistor circuit comprising a depletion-mode switch in series with a normally-off switch between a drain output terminal and a source output terminal. The circuit also includes a controller comprising a controller output terminal configured to provide a normally-on control signal for a normally-on control terminal of the depletion-mode switch, wherein the normally-on control signal is independent of the normally-off control signal; a negative voltage source configured to provide a negative voltage to the normally-on control terminal of the depletion-mode switch; and a feedback capacitance between the drain output terminal and a control node in a circuit path between the controller output terminal and the normally-on control terminal of the depletion-mode switch.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: July 11, 2017
    Assignee: Nexperia B.V.
    Inventors: Ralf van Otten, Franciscus Schoofs, Matthias Rose, Hendrik Bergveld
  • Patent number: 9654098
    Abstract: A signal reception circuit according to an aspect of the present disclosure includes: an input terminal; an input reference terminal; an output terminal; an output reference terminal; a normally-on type transistor that includes a first terminal connected to the output terminal, a second terminal connected to the output reference terminal, and a control terminal; a first detector circuit that detects an input signal applied between the input terminal and the input reference terminal, to apply an output signal between the output terminal and the output reference terminal; and a second detector circuit that detects the input signal, to apply a negative voltage pulse to the control terminal of the transistor with the output reference terminal as a reference.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: May 16, 2017
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventor: Shuichi Nagai
  • Patent number: 9653449
    Abstract: A semiconductor device of an embodiment includes a normally-off transistor having a first source electrically connected to a source terminal, a first drain, and a first gate electrically connected to a gate terminal, a normally-on transistor having a second source electrically connected to the first drain, a second drain electrically connected to a drain terminal, and a second gate, a capacitor having one end electrically connected to the gate terminal and the other end electrically connected to the second gate; and a first diode having a first anode electrically connected to the capacitor and the second gate and a first cathode electrically connected to the first source.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: May 16, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kentaro Ikeda
  • Patent number: 9621110
    Abstract: A power amplifier of the present invention comprises a first cascode including a MOSFET and a JFET and a first capacitor electrically connected between the source and the drain of the JFET. Two such power amplifiers in parallel form a differential power amplifier. In the differential amplifier a second capacitor can be electrically connected between the source and the drain of the second JFET. Another differential power amplifier comprises a first capacitor electrically connected between the gate of the first MOSFET and the source of the second MOSFET, and a second capacitor electrically connected between the gate of the second MOSFET and the source of the first MOSFET. Some of these differential power amplifiers also include capacitors electrically connected between the sources and the drains of the JFETs.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: April 11, 2017
    Assignee: ACCO
    Inventors: Christophe Boyavalle, Denis A. Masliah, Francis C. Huin
  • Patent number: 9559683
    Abstract: In accordance with an embodiment, a circuit includes a first driver having a first output configured to be coupled to a control node of a normally-off transistor. The first driver is configured to drive a first switching signal at the first output in a cascode mode and configured to drive a first constant voltage at the first output in a direct drive mode. The circuit further includes a second driver having a second output configured to be coupled to a control node of a normally-on transistor that has a second load path terminal coupled to a first load path terminal of the normally-off transistor. The second driver is configured to drive a second switching signal at the second output in the direct drive mode.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: January 31, 2017
    Assignee: Infineon Technologies Austria AG
    Inventor: Bernhard Zojer
  • Patent number: 9293458
    Abstract: An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor both encased in a single package. A source electrode of the high-voltage depletion-mode transistor is electrically connected to a drain electrode of the low-voltage enhancement-mode transistor, a drain electrode of the high-voltage depletion-mode transistor is electrically connected to a drain lead of the single package, a gate electrode of the low-voltage enhancement-mode transistor is electrically connected to a gate lead of the single package, a gate electrode of the high-voltage depletion-mode transistor is electrically connected to an additional lead of the single package, and a source electrode of the low-voltage enhancement-mode transistor is electrically connected to a conductive structural portion of the single package.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: March 22, 2016
    Assignee: Transphorm Inc.
    Inventors: Primit Parikh, James Honea, Carl C. Blake, Jr., Robert Coffie, Yifeng Wu, Umesh Mishra
  • Patent number: 9293465
    Abstract: A monolithic bi-directional device provides bi-directional power flow and bi-directional blocking of high-voltages. The device includes a first transistor having a first drain formed over a first channel layer that overlays a substrate, and a second transistor that includes a second drain formed over a second channel layer that overlays the substrate. The substrate forms a common source for both the first transistor and the second transistor.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: March 22, 2016
    Assignee: Northrop Grumman Systems Corporation
    Inventor: John V. Veliadis
  • Patent number: 9248751
    Abstract: This disclosure provides systems, methods and apparatus for power converters and particularly power converters for wireless power transfer to remote systems such as electric vehicles. In one aspect, the disclosure provides an electronic power supply. The electronic power supply includes at least first and second half-bridge circuitries. The first half-bridge circuitry includes semiconductor material of a first type. The second half-bridge circuitry of the H-bridge includes semiconductor material of a second type. The first semiconductor material type is different from the second semiconductor material type.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: February 2, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Nicholas Athol Keeling, Michael Le Gallais Kissin, Chang-Yu Huang
  • Patent number: 9142544
    Abstract: A semiconductor device of an embodiment includes a normally-off transistor having a first source electrically connected to a source terminal, a first drain, and a first gate electrically connected to a gate terminal, a normally-on transistor having a second source electrically connected to the first drain, a second drain electrically connected to a drain terminal, and a second gate, a capacitor having one end electrically connected to the gate terminal and the other end electrically connected to the second gate; and a first diode having a first anode electrically connected to the capacitor and the second gate and a first cathode electrically connected to the first source.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: September 22, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kentaro Ikeda
  • Publication number: 20150109048
    Abstract: A transistor includes a channel forming layer on a substrate, a gate on the channel forming layer and including an electrochemically indifferent metal, a solid electrolyte layer between the channel forming layer and the gate, the solid electrolyte layer is formed as a stack structure with the gate on the channel forming layer, an active metal layer including an electrochemically active metal capable of enabling channel switching by using an oxidation-reduction reaction of the electrochemically active metal so that the active metal layer forms a metal channel in a channel region between the channel forming layer and the solid electrolyte layer, and a source and a drain electrically connected to the active metal layer.
    Type: Application
    Filed: October 23, 2014
    Publication date: April 23, 2015
    Inventors: Woo-young YANG, Ki-hong KIM, Sang-jun CHOI, Young-eal KIM, Seong-yong PARK
  • Patent number: 9007103
    Abstract: In various embodiments, a switch circuit arrangement may include a switch circuit, a driver circuit and a supply circuit. The driver circuit may be configured to control the switch circuit. The supply circuit may be configured to power the driver circuit. The supply circuit may include a first circuit configured to modify an output impedance of the supply circuit to have a first impedance when the driver circuit controls the switch circuit to be in a conducting state and to have a second impedance when the driver circuit controls the switch circuit to change from a non-conducting state to the conducting state.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: April 14, 2015
    Assignee: Infineon Technologies Austria AG
    Inventor: Bernhard Zojer
  • Patent number: 9007117
    Abstract: According to an embodiment, a solid-state switching device includes a high-voltage switching transistor including a source, a drain and a gate, and being adapted for switching a high voltage on the basis of a switching signal, and a switching driver circuit operationally connected to the high-voltage switching transistor, the switching driver circuit including a low-voltage driver transistor including a source, a drain and a gate, connected in series to the high-voltage switching transistor and being adapted for transferring the switching signal to the high-voltage switching transistor, wherein the high-voltage switching transistor is arranged source-down on top of the drain of the low-voltage driver transistor.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: April 14, 2015
    Assignee: Infineon Technologies Dresden GmbH
    Inventors: Rolf Weis, Anthony Sanders
  • Patent number: 8988132
    Abstract: Provided is a semiconductor device which avoids an adverse effect of high temperatures due to a switching element and in which a circuit to prevent false firing is arranged on the same substrate as the switching element. An N-channel type MOSFET 10 and a JFET 30 of an N-channel type containing a semiconductor material of silicon carbide are individually arranged in proximity on conductive patterns 51, 52 on a substrate 5, and a gate electrode 13 of the MOSFET 10 and a drain electrode 31 of the JFET 30 are connected by a lead 61. When an external drive signal for on/off control of MOSFET 10 propagates between source electrode 32 and drain electrode 31 of JFET 30, the channel resistance of JFET 30 is changed to a large/small value according to a low/high level of gate voltage between source electrode 32 and gate electrode 33, whereby a leading edge of a switching waveform between drain electrode 11 and source electrode 12 of MOSFET 10 comes to have a gentler slope than a trailing edge thereof.
    Type: Grant
    Filed: February 23, 2011
    Date of Patent: March 24, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Kenichi Sawada
  • Patent number: 8963513
    Abstract: A switching power source according to one embodiment includes a first transistor and a second transistor. The first transistor is connected to a positive electrode of a DC voltage source. The second transistor is connected between the first transistor and a negative electrode of the DC voltage source. The first transistor and the second transistor are alternately placed in conducting state. A gate signal is applied to a gate terminal of the first transistor with reference to a voltage of a terminal of the first transistor that is connected to the positive electrode. A gate signal is applied to a gate terminal of the second transistor with reference to a voltage of a terminal of the second transistor that is connected to the negative electrode. The first transistor and the second transistor are configured with wide bandgap semiconductors of mutually different materials, respectively.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: February 24, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Takashi Tsuno
  • Patent number: 8958193
    Abstract: A system/method for providing an optically triggered circuit breaker is provided. The system comprises a junction field-effect transistor (JFET) and gate drive coupled to the JFET's gate. The gate drive applies voltage bias (VG) to the gate and the gate drive is configured to bias VG so that the system allows current flow through the JFET in the Drain to Source or Source to Drain directions, or so that the system blocks voltages applied to the Drain and/or Source. The system also comprises a photodetector which detects light emitted by the JFET resulting from a fault condition. The photodetector transmits a signal to the gate drive to provide the selectively biased VG so that the system blocks voltages applied to the Drain and/or Source, in response to the light detection. A system/method for providing an optically triggered bidirectional circuit breaker comprising common source JFETs and two photodetectors is alternatively provided.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: February 17, 2015
    Assignee: Northrop Grumman Systems Corporation
    Inventor: John V. Veliadis
  • Patent number: 8947154
    Abstract: An electronic circuit comprising a driver and a main transistor are provided. The driver may include a bias voltage generator, a supplementary transistor, and an output driver. The bias voltage generator may be configured to receive a voltage input and generate a biased voltage output based on the voltage input. The supplementary transistor may have a gate coupled to the biased voltage output of the bias voltage generator, and a source of the supplementary transistor providing a current to the bias voltage generator. The output driver may be configured to receive the biased voltage output from the bias voltage generator and the voltage input, receive the voltage input, and output a drive voltage. The main transistor of the electronic circuit may have a gate, a coupled to the drive voltage, and a drain coupled to a drain of the supplementary transistor.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: February 3, 2015
    Assignee: Avogy, Inc.
    Inventors: Hemal N. Shah, Donald R. Disney, Heratch Amirkhani Namagerdi
  • Patent number: 8928392
    Abstract: This document discusses, among other things, a switching device and method configured to receive a signal at a signal input, to provide the signal at an output in a first state without an applied voltage at a first control input, and to isolate the signal from the output in a second state with an applied voltage at the first control input. In an example, the switching device can include first, second, and third transistors, wherein the source of the first transistor is coupled to the drain of the second transistor and to the gate of the third transistor, wherein the signal input is coupled to the drain of the first transistor and to the drain of the third transistor, and wherein the output is coupled to the source of the third transistor.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: January 6, 2015
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Tony Cheng Han Lee, Shawn Barden
  • Patent number: 8912840
    Abstract: A switching device for switching a current between a first connection and a second connection including a series circuit of at least two JFETs (J1-Jn), with further JFETs (J2-Jn), which are connected in series to a lowest JFET (J1), and wherein a wiring network for stabilizing the gate voltages of the JFETs (J1-Jn) is connected between the second connection and the first termination. One additional circuit is connected between each gate connection (GJ2, GJ3 . . . GjN) of the further JFETs (J2-Jn) and associated cathode connections of diodes (DAV) of the wiring network. During switch-on and in the switched-on state, said additional circuit keeps the potential of the respective gate connection higher than the potential of the associated source connection.
    Type: Grant
    Filed: April 6, 2011
    Date of Patent: December 16, 2014
    Assignee: Eth Zurich, Eth Transfer
    Inventors: Daniel Aggeler, Jürgen Biela, Johann Walter Kolar
  • Patent number: 8866200
    Abstract: An electrostatic discharge (ESD) protection circuit is disclosed. The circuit includes a first terminal (200), a first power supply terminal (Vdd), and a second power supply terminal (Vss). The circuit further includes a junction field effect transistor (JFET) having a current path coupled between the first terminal and the second power supply terminal. The JFET has a control terminal (202) coupled to the first power supply terminal.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: October 21, 2014
    Inventor: Robert Newton Rountree
  • Patent number: 8860494
    Abstract: A method for rendering a half-bridge circuit containing normally on switches such as junction field effect transistors (JFETs) inherently safe from uncontrolled current flow is described. The switches can be made from silicon carbide or from silicon. The methods described herein allow for the use of better performing normally on switches in place of normally off switches in integrated power modules thereby improving the efficiency, size, weight, and cost of the integrated power modules. As described herein, a power supply can be added to the gate driver circuitry. The power supply can be self starting and self oscillating while being capable of deriving all of its source energy from the terminals supplying electrical potential to the normally on switch through the gate driver. The terminal characteristics of the normally on switch can then be coordinated to the input-to-output characteristics of the power supply.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: October 14, 2014
    Assignee: Power Integrations, Inc.
    Inventors: Michael S. Mazzola, Robin Schrader
  • Patent number: 8779841
    Abstract: A cascode switch includes a first power transistor configured to be coupled to a load and a second power transistor coupled in series with the first power transistor so that the second power transistor is between ground and the first power transistor. The second power transistor is operable to switch on and off responsive to a pulse source coupled to a gate of the second power transistor. The first power transistor is operable to switch on and off responsive to the same pulse source as the second power transistor or a DC source coupled to a gate of the first power transistor. Alternatively or in addition, a transistor device is coupled to the gate of the first power transistor and operable to actively turn off the first power transistor independent of the load current.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: July 15, 2014
    Assignee: Infineon Technologies Austria AG
    Inventor: Mladen Ivankovic
  • Patent number: 8760214
    Abstract: The invention relates to a switching device for switching a current between a first connection (1) and a second connection (2), comprising a series connection of at least two JFETs (J1-J6), of which a lowest JFET (J1) is connected to the first connection (1), or the lowest JFET (J1) is connected in a cascade circuit to the first connection (1) via a control switch (M), and at least one further JFET (J2-J5), which is connected in series to the lowest JFET (J1), wherein the JFET (J6) farthest away from the lowest JFET (J1) is referred to as the uppermost JFET (J6) and is connected with the drain connection to the second connection (2), and wherein a stabilization circuit (D11-D53) is connected between the gate connections of the JFETs (J1-J6) and the first connection (1) in order to stabilize the gate voltages of the JFETs (J1-J6).
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: June 24, 2014
    Assignee: ETH Zurich
    Inventors: Jürgen Biela, Johann W. Kolar, Daniel Aggeler
  • Publication number: 20140139282
    Abstract: A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.
    Type: Application
    Filed: January 28, 2014
    Publication date: May 22, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jen-Hao Yeh, Chih-Chang Cheng, Ru-Yi Su, Ker Hsiao Huo, Po-Chih Chen, Fu-Chih Yang, Chun-Lin Tsai
  • Patent number: 8729739
    Abstract: A circuit breaker comprising first and second JFETs, each comprising a gate, drain and source connection, the JFETs sources being operatively connected to each other to form a common-source connection and adapted to be connected to and operating to open an external circuit when the current flowing through the JFETs exceeds a predetermined threshold, the JFETs' gates, and common-source connection being operatively connected to a gate driver circuit which causes the JFETs to turn off when the predetermined threshold is exceeded; whereupon the current flows through the common-source connection into the second gate and into the gate driver circuit which causes the gate driver circuit to turn off the first and second JFETs and open the circuit breaker. Also claimed is a method of sensing an overloaded circuit comprising leading and trailing JFETs in a circuit that open the circuit and prevent current flow when a predetermined threshold is exceeded.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: May 20, 2014
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Vadim Lubomirsky, Damian Urciuoli
  • Patent number: 8723589
    Abstract: A switching device for switching a current between a first terminal (1) and a second terminal (2) comprises a cascode circuit having a series connection of a first semiconductor switch (M) and a second semiconductor switch (J), wherein the two semiconductor switches (M, J) are connected to each other by a common point (13), and the first semiconductor switch (M) is controlled by way of a first control input in accordance with a voltage between the first control input and the first terminal (1), and the second semiconductor switch (J) is controlled by way of a second control input (4) in accordance with a voltage between the second control input (4) and the common point (13). To this end, a control circuit having a specifiable capacitance (C) is connected between the second terminal (2) and at least one of the control input.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: May 13, 2014
    Assignee: ETH Zurich
    Inventors: Jürgen Biela, Johann W. Kolar, Daniel Aggeler
  • Patent number: 8710543
    Abstract: A semiconductor device including: an FET; a MOSFET having a drain thereof connected with a source of the FET; a resistor having one end thereof connected with a gate of the FET and having the other end thereof connected with a source of the MOSFET; and a diode having an anode thereof connected with the gate of the FET and having a cathode thereof connected with the source of the MOSFET.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: April 29, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Yuhji Ichikawa
  • Patent number: 8704585
    Abstract: A method for driving a field effect transistor for shaping an electrical signal, representing a sound, to an output signal is disclosed. The method comprises modifying the input signal to an intermediate signal, and output of the intermediate signal to the field effect transistor for shaping the output signal. The method comprises the steps of adjusting the quiescent point of the field effect transistor such that the same is placed in the quadratic region of the transfer characteristics of the field effect transistors, and adjusting the amplitude of the intermediate signal, such that the same causes the potential swing between the gate terminal and the source terminal to at least partly be in the quadratic region of the transfer characteristics of the field effect transistor.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: April 22, 2014
    Assignee: Research Electronics Leksand AB
    Inventor: Sven-Ake Eriksson
  • Patent number: 8698547
    Abstract: A control circuit includes: a first switching element having a source, a gate, and a drain; a battery configured to supply a voltage to the gate through a second switching element; a PWM signal generator circuit configured to supply a PWM signal to the gate through a third switching element; and a gate control circuit configured to, under a power-off condition, turn on the second switching element to supply the voltage of the battery to the gate and turns off the third switching element, and configured to under a power-on condition, turn on the third switching element to supply the PWM signal voltage to the gate and turns off the second switching element.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: April 15, 2014
    Assignee: Fujitsu Limited
    Inventor: Hiroshi Nakao
  • Patent number: 8653881
    Abstract: A circuit includes a high-side switch, a low-side switch, a diode, a transformer having a primary winding and a secondary windowing, and an input connected to a first terminal of the primary winding. The high-side switch has a source, a gate connected to a drive source and a drain connected to a second terminal of the primary winding. The low-side switch has a source connected to ground, a gate connected to a drive source and a drain connected to the source of the high-side switch. The diode is connected between the gate of the high-side switch and the first terminal of the primary winding. The diode forms a current loop with the primary winding and the high-side switch to circulate current when low side switch is off until the high side switch turns off.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: February 18, 2014
    Assignee: Infineon Technologies Austria AG
    Inventor: Mladen Ivankovic
  • Publication number: 20140015592
    Abstract: A circuit includes first and second semiconductor switches each having a load path and control terminal and their load paths connected in series. At least one of the first and second switches includes a first semiconductor device having a load path and a control terminal, the control terminal coupled to the control terminal of the switch. A plurality of second semiconductor devices each have a load path between a first load terminal and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices. One of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device.
    Type: Application
    Filed: July 11, 2012
    Publication date: January 16, 2014
    Applicant: INFINEON TECHNOLOGIES DRESDEN GMBH
    Inventor: Rolf Weis
  • Patent number: 8610489
    Abstract: This document discloses, among other things, a switch circuit that includes a depletion-mode field-effect transistor (DMFET) having an ON-state and an OFF-state, wherein the DMFET is configured to couple a first node to a second node in the ON-state, and wherein the DMFET is configured to isolate the first node from the second node in the OFF-state, a negative charge pump that is coupled to a gate terminal of the DMFET, the charge pump configured to supply a negative charge pump voltage to the gate terminal of the DMFET, and a negative discriminator coupled to the charge pump, the discriminator configured to compare a first voltage at the first node and a second voltage at the second node and determine the negative charge pump voltage based on the comparison.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: December 17, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Tyler Daigle, Julie Lynn Stultz, Kenneth P. Snowdon
  • Publication number: 20130293002
    Abstract: An electrical switching device includes at least two electronic components, with a control circuit designed to control the or each component. Each component is connected to the control circuit by a respective connection, and each component has a switching speed that is higher than 10 kA/?s or higher than 20 kV/?s and wherein the or each connection has an inductance that is lower than 10 nH.
    Type: Application
    Filed: May 1, 2013
    Publication date: November 7, 2013
    Applicant: Alstom Transport SA
    Inventors: Johnny BOU SAADA, Fisal AL KAYAL
  • Patent number: 8536931
    Abstract: Power switch devices for high-speed applications are disclosed. The power switch device includes a depletion mode field effect transistor (D-FET), an enhancement mode field effect transistor (E-FET) and a bipolar transistor. In one embodiment, the E-FET is coupled in cascode with the D-FET such that turning off the E-FET turns off the D-FET and turning on the E-FET turns on the D-FET. Furthermore, the bipolar transistor is operably associated with the D-FET and the E-FET such that turning on the bipolar transistor drives current from the D-FET through the bipolar transistor to the E-FET to provide a charge that turns on the E-FET. The bipolar transistor provides several advantages such as a higher Schottky breakdown voltage for the E-FET and faster current switching speed for the power switch device.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: September 17, 2013
    Assignee: RF Micro Devices, Inc.
    Inventors: Kevin W. Kobayashi, Joseph Johnson
  • Publication number: 20130194027
    Abstract: A cascode switch includes a first power transistor configured to be coupled to a load and a second power transistor coupled in series with the first power transistor so that the second power transistor is between ground and the first power transistor. The second power transistor is operable to switch on and off responsive to a pulse source coupled to a gate of the second power transistor. The first power transistor is operable to switch on and off responsive to the same pulse source as the second power transistor or a DC source coupled to a gate of the first power transistor. Alternatively or in addition, a transistor device is coupled to the gate of the first power transistor and operable to actively turn off the first power transistor independent of the load current.
    Type: Application
    Filed: January 31, 2012
    Publication date: August 1, 2013
    Applicant: INFINEON TECHNOLOGIES NORTH AMERICA CORP.
    Inventor: Mladen Ivankovic
  • Patent number: 8476961
    Abstract: A system and method are provided for biasing transistor switches in a semiconductor based high power switch. Off-state Vgsd biasing for the off transistor switches is based upon acceptable levels of spurious harmonic emissions and linearity.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: July 2, 2013
    Assignee: SiGe Semiconductor, Inc.
    Inventors: Chun-Wen Paul Huang, Mark Doherty, Philip Michael Antognetti
  • Patent number: 8466735
    Abstract: Gate drivers for wide bandgap (e.g., >2 eV) semiconductor junction field effect transistors (JFETs) capable of operating in high ambient temperature environments are described. The wide bandgap (WBG) semiconductor devices include silicon carbide (SiC) and gallium nitride (GaN) devices. The driver can be a non-inverting gate driver which has an input, an output, a first reference line for receiving a first supply voltage, a second reference line for receiving a second supply voltage, a ground terminal, and six Junction Field-Effect Transistors (JFETs) wherein the first JFET and the second JFET form a first inverting buffer, the third JFET and the fourth JFET form a second inverting buffer, and the fifth JFET and the sixth JFET form a totem pole which can be used to drive a high temperature power SiC JFET. An inverting gate driver is also described.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: June 18, 2013
    Assignee: Power Integrations, Inc.
    Inventor: Robin Kelley
  • Patent number: 8456218
    Abstract: A method for rendering a half-bridge circuit containing normally on switches such as junction field effect transistors (JFETs) inherently safe from uncontrolled current flow is described. The switches can be made from silicon carbide or from silicon. The methods described herein allow for the use of better performing normally on switches in place of normally off switches in integrated power modules thereby improving the efficiency, size, weight, and cost of the integrated power modules. As described herein, a power supply can be added to the gate driver circuitry. The power supply can be self starting and self oscillating while being capable of deriving all of its source energy from the terminals supplying electrical potential to the normally on switch through the gate driver. The terminal characteristics of the normally on switch can then be coordinated to the input-to-output characteristics of the power supply.
    Type: Grant
    Filed: February 4, 2011
    Date of Patent: June 4, 2013
    Assignee: Power Integrations, Inc.
    Inventors: Michael S. Mazzola, Robin Kelley
  • Patent number: 8441128
    Abstract: A semiconductor arrangement includes a circuit carrier, bonding wire and at least N half bridge circuits. The circuit carrier includes a first metallization layer, a second metallization layer, an intermediate metallization layer arranged between the first metallization layer and the second metallization layer, a first insulation layer arranged between the intermediate metallization layer and the second metallization layer, and a second insulation layer arranged between the first metallization layer and the intermediate metallization layer. Each half bridge circuit includes a controllable first semiconductor switch and a controllable second semiconductor switch. The first semiconductor switch and the second semiconductor switch of each half bridge circuit are arranged on that side of the first metallization layer of the circuit carrier facing away from the second insulation layer. The bonding wire is directly bonded to the intermediate metallization layer of the circuit carrier at a first bonding location.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: May 14, 2013
    Assignee: Infineon Technologies AG
    Inventor: Daniel Domes
  • Patent number: 8416007
    Abstract: An apparatus is provided that includes a first field effect transistor with a source tied to zero volts and a drain tied to voltage drain drain (Vdd) through a first resistor. The apparatus also includes a first node configured to tie a second resistor to a third resistor and connect to an input of a gate of the first field effect transistor in order for the first field effect transistor to receive a signal. The apparatus also includes a second field effect transistor configured as a unity gain buffer having a drain tied to Vdd and an uncommitted source.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: April 9, 2013
    Assignee: The United States of America as Represented by the Administrator of National Aeronautics and Space Administration
    Inventor: Michael J Krasowski
  • Publication number: 20130057332
    Abstract: A switching device for switching a current between a first connection and a second connection including a series circuit of at least two JFETs (J1-Jn), with further JFETs (J2-Jn), which are connected in series to a lowest JFET (J1), and wherein a wiring network for stabilizing the gate voltages of the JFETs (J1-Jn) is connected between the second connection and the first termination. One additional circuit is connected between each gate connection (GJ2, GJ3 . . . GjN) of the further JFETs (J2-Jn) and associated cathode connections of diodes (DAV) of the wiring network. During switch-on and in the switched-on state, said additional circuit keeps the potential of the respective gate connection higher than the potential of the associated source connection.
    Type: Application
    Filed: April 6, 2011
    Publication date: March 7, 2013
    Applicant: ETH ZURICH
    Inventors: Daniel Aggeler, Jürgen Biela, Johann Walter Kolar
  • Patent number: 8344788
    Abstract: The semiconductor device includes a power element which is in an on state when voltage is not applied to a gate, a switching field-effect transistor for applying first voltage to the gate of the power element, and a switching field-effect transistor for applying voltage lower than the first voltage to the gate of the power element. The switching field-effect transistors have small off-state current.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: January 1, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Patent number: 8299835
    Abstract: A switch circuit is provided that includes at least one main switching device and at least one shunt switching device. Each main switching device is connected in series with a conductor that carries an RF signal between an input circuit and an output circuit. Each shunt switching device is connected between a controlling terminal of the main switching device and a high frequency ground. The switch circuit can provide substantially improved OFF state isolation over other approaches.
    Type: Grant
    Filed: February 2, 2009
    Date of Patent: October 30, 2012
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Alexei Koudymov, Grigory Simin, Michael Shur, Remis Gaska
  • Publication number: 20120262220
    Abstract: Switches comprising a normally-off semiconductor device and a normally-on semiconductor device in cascode arrangement are described. The switches include a capacitor connected between the gate of the normally-on device and the source of the normally-off device. The switches may also include a zener diode connected in parallel with the capacitor between the gate of the normally-on device and the source of the normally-off device. The switches may also include a pair of zener diodes in series opposing arrangement between the gate and source of the normally-off device. Switches comprising multiple normally-on and/or multiple normally-off devices are also described. The normally-on device can be a JFET such as a SiC JFET. The normally-off device can be a MOSFET such as a Si MOSFET. The normally-on device can be a high voltage device and the normally-off device can be a low voltage device. Circuits comprising the switches are also described.
    Type: Application
    Filed: April 13, 2011
    Publication date: October 18, 2012
    Applicant: SEMISOUTH LABORATORIES, INC.
    Inventor: Nigel SPRINGETT