Abstract: Features for high intensity focused ultrasound (HIFU) are described. The application of HIFU for ablating tissue may be monitored in real time by imaging bubbles generated during HIFU. A single transducer array may be used by fast switching between imaging and HIFU. For imaging, the array or portions thereof may be used in receive only mode to locate bubbles generated by the HIFU. The application of HIFU, such as location and/or intensity, may be adjusted based on information from the imaging of the bubbles. Physicians and/or others may use these systems and methods to monitor HIFU procedures in real-time for optimal ablation of target tissue with minimal damage to healthy tissue.

Abstract: Third order distortion is reduced in a CMOS transconductor circuit that includes a first N-channel transistor and a first P-channel transistor, gates of the first N-channel transistor and the first P-channel transistor being coupled to receive an input signal. Drains of the first N-channel transistor and first P-channel transistor are coupled to an output conductor. A first degeneration resistor is coupled between a source of the first P-channel transistor and a first supply voltage and a second degeneration resistor is coupled between a source of the first N-channel transistor and a second supply voltage. A first low impedance bypass circuit is coupled between the sources of the first P-channel transistor and the first N-channel transistor.

Abstract: A diode selection circuit for a light emitting apparatus according to some embodiments includes a plurality of light emitting devices coupled in series. The diode selection circuit includes a comparator configured to receive a rectified AC input signal and a reference voltage and to generate a control signal in response to comparison of the rectified AC input signal with the reference voltage, a voltage controlled current source configured to supply a current to the plurality of light emitting diodes that is proportional to the rectified AC input signal, and a switch configured to receive the control signal and to shunt current away from at least one of the plurality of light emitting devices in response to the control signal.

Abstract: An electrical-optical modulator may function at high data rates and may be realized in comparably low cost silicon base technology, typically in BJT, BiCMOS or CMOS technologies. The output signal path may include a high transition frequency BJT and by using an active load constituted by a MOS driven by an inverted version of the modulating signal that drives the BJT, the falling edge of the output signal is sped up.

Abstract: New designs of high power switching circuits and controller circuits are provided. Principal silicon bipolar switch is connected in parallel to snubber switch that is formed of a wide bandgap material. The snubber switch is activated during at least one of turn-on and turn-off of the principal silicon switch so as to minimize (or reduce) the switching loss and to bypass safe operation area limitations.

Abstract: A circuit for a phase connection of an inverter includes upper and lower bridge halves and respectively associated upper and lower bridge segments. Each bridge half has an outer switch and an inner switch connected in series. Each bridge segment has a diode and the inner switch of the associated bridge half connected in series. An output of the circuit is respectively connected to upper and lower potentials through the outer switches and is further connected to a center potential applied between the upper and lower potentials through each of the upper and lower bridge segments. Each bridge half further has a parallel power switch. The parallel switch of each bridge half is connected in parallel to the series-connected outer and inner switches of the bridge half. The output of the circuit is further respectively connected to the upper and lower potentials through the parallel switches.

Abstract: A solid-state relay is provided, which includes a first transistor, a second transistor, a first transmission circuit, and a second transmission circuit. A gate of the first transistor is connected to one of a source and a drain of the second transistor, one of a source and a drain of the first transistor is connected to a first terminal, and the other of the source and the drain of the first transistor is connected to a second terminal. The first transmission circuit supplies a first signal to the gate of the first transistor. The second transmission circuit supplies a second signal to a gate of the second transistor. The first terminal is connected to the second terminal when the first transistor is turned on by the first signal.

Abstract: A circuit is provided and includes current sources, switches, a control module, and capacitances. The current sources adjust current flowing through a load. Each of the switches activates a respective one of the current sources. Kick-back voltages are generated at inputs of the current sources in response to the current sources being turned ON. A control module generates control signals to change states of the switches to alternate a direction in which the current flows through the load. A first capacitance is connected between a first pair of the current sources and a second pair of the current sources. A second capacitance is connected between the first pair of the current sources and a reference terminal. A third capacitance connected between the second pair of the current sources and the reference terminal. The first capacitance, the second capacitance, and the third capacitance reduce magnitudes of the kick-back voltages.

Abstract: A method and system for limiting the slew rate of the output voltage of one or more high side (HS) NMOS power switches is disclosed. A circuit arrangement configured to control a first NMOS switch is described. The arrangement comprises voltage provisioning means configured to supply a gate voltage to a gate terminal of the first NMOS switch; current provisioning means configured to provide a current; a first control stage configured to provide and/or remove a connection between the gate terminal of the first NMOS switch and the voltage provisioning means, thereby switching the first NMOS switch to an on-state and/or an off-state, respectively; and a first feedback control link between an output terminal of the first NMOS switch and the current provisioning means configured to control the slew-rate of a voltage at the first output terminal.

Abstract: An identifying circuit is connected between a Universal Serial Bus (USB) interface and a controller. The identifying circuit includes first to fourth electronic switches. When a power adapter connects to the USB interface, the first and fourth electronic switches are not turned on, and the second and third electronic switches are turned on. An identification pin of the controller receives a low level signal and determines that the power adapter connects to the USB interface. When a computer connects to the USB interface, the first and fourth electronic switches are turned on, and the second and third electronic switches are not turned on. The identification pin receives a high level signal and determines that the computer is connected to the USB interface.

Abstract: A front-end module comprises a plurality of chips that includes first and second functional blocks and an interconnection circuit. The first functional block is formed using a first process type and includes a digital control circuit that generates a digital control signal in response to an external control signal from outside the front end module. The second functional block is formed using a second process type and includes a digitally controlled circuit controlled by the digital control signal generated by the first functional block. The second process type is different from the first process type. The interconnection circuit couples the digital control circuit and the digitally controlled circuit to provide the digital control signal to the digitally controlled circuit. In one aspect, the first functional block may be a low noise amplifier formed by a pseudomorphic high electron mobility transistor process.

Abstract: A solid-state switch according to the invention is designed to be connected in series with a load. The switch comprises at least two electric switching means connected in parallel, measuring means designed to measure an electric voltage at the terminals of the electric switching means and a main current flowing in the load, and control means delivering a control signal to act on opening and closing according to the value of the main current. The state of conduction of the first electric switching means depends at the same time on the main current flowing in the load, on a control current, on a control voltage delivered by the control means, and on the gain of the first electric switching means.

Abstract: It is possible to reliably prevent two switching elements comprising a half-bridge circuit from turning ON simultaneously even when two pulse signals allowing both the two switching elements to turn ON are input thereto. A first drive signal is allowed to be output from a first output terminal 4 to a P-type MOSFET 10 based on a first pulse signal and a second pulse signal, and a second drive signal is allowed to be output from a second output terminal 5 to an N-type MOSFET 11 that operates as a second switching element based on the first pulse signal and the second pulse signal, and a protecting circuit 20 is configured to allow at least one of the P-type MOSFET 10 and the N-type MOSFET 11 to turn OFF.

Abstract: A circuit including a voltage-controlled transistor to be switched. A first transistor is switched on, mediated by a control signal, and a first current flows through a series circuit and starts to subject a control input of the voltage-controlled transistor to charge reversal. The first current brings about a first potential shift at a connecting node. A second transistor is switched on by this first potential shift and a second current therefore flows through the switching path of the second transistor into the control input of the first transistor, which amplifies the first current. The increasing charge reversal of the control input of the voltage-controlled transistor brings about a second potential shift at the connecting node, the second transistor is switched off by this second potential shift, and the first transistor remains switched on, however, and holds the voltage-controlled transistor in its new switching state.

Abstract: A solid state switching device (SSSD) for AC and DC high power solid state power controller includes, for DC applications, a MOSFET and an IGBT connected in parallel and an optional zener diode connecting a collector and a gate of the IGBT. For AC applications, the SSSD includes a “back to back” pair of MOSFETs connected in parallel with a pair of counter-parallel IGBTs, each in series with a diode, and, optionally, zener diodes “back to back” with conventional diodes connecting a collector and a gate of each of the IGBT. A method of switching establishes a sequence of turning on/off the MOSFET(s) and the IGBT(s) wherein the IGBT(s) turn on before and turn off after the MOSFET(s). A negative feedback prevents a voltage of SSSD rising above predetermined level.

Abstract: An embodiment of the invention relates to a driving circuit for an emitter-switching configuration of transistors having at least one first and one second control terminal connected to the driving circuit to form a controlled emitter-switching device having in turn respective collector, source and gate terminals. Advantageously the driving circuit comprises at least one IGBT device inserted between the collector terminal and a first end of a capacitor, whose second end is connected to the first control terminal, the IGBT device having in turn a third control terminal connected, through a first resistive element, to the gate terminal, as well as a second resistive element inserted between the gate terminal and the second control terminal. Advantageously, the driving circuit further comprises an additional supply inserted between the first and second ends of the capacitor to ensure its correct biasing.

Abstract: A monolithic interface circuit for providing a voltage, from a control circuit supplied by a supply voltage referenced to a reference voltage, to a terminal likely to be at a high voltage with respect to the reference voltage, comprising a high-voltage N-channel MOS transistor having its gate intended to receive a control signal referenced to the reference voltage and having its source intended to be connected to the reference voltage, and a high-voltage PNP transistor having its base connected to the drain of the MOS transistor, having its emitter intended to receive the supply voltage and having its collector intended to provide a voltage to the terminal likely to be at a high voltage.

Abstract: Two systems consisting of an on-off control section corresponding to the saturation drive system and a constant voltage control section corresponding to the constant voltage drive system are provided as a circuit for controlling the conduction state of a transistor QP11 provided at the output section. The constant voltage unit comprises an operational amplifier A1, which monitors the output voltage Vout and feedback-controls the gate voltage of QP11. On the other hand, the on-off control section delivers a control signal for turning on and off QP11 corresponding to an input signal input to IN-U through inverters 40 and 42. Switches 46 and 48 for selectively applying the output from the control unit of either one of these two systems are provided to select the switch to be turned on based on a mode signal input to SW. This configuration enables the realization of different drive systems and restricts increase in circuit size while commonly using the output unit configured with comparatively large transistors.

Abstract: A half-bridge circuit, in which an input signal that is applied between two input terminals can be picked up at a phase output comprises two switching transistors controlled by a respective control signal that is applied between a control electrode and an auxiliary electrode and two diodes. The first input terminal is connected to the first electrode of the first switching transistor and to the first diode's cathode. A second electrode of the first switching transistor is connected to the first diode's anode by means of the phase output, via a line, to a first electrode of the second switching transistor and to a cathode of the second diode. A second electrode of the second switching transistor is connected to an anode of the second diode and to the second input terminal. The auxiliary electrode of the first switching transistor is connected to the line of the phase output.

Abstract: A basic switching circuit combines CMOS and bipolar technique on SiGe basis and operates at a low operating voltage of only slightly more than 2V. To achieve this low operating voltage, switching operation of the circuit is effected by switching a constant current source of the switching circuit on or off using MOS transistors. In addition, the constant current source is implemented using a MOS transistor rather than a bipolar transistor, which basically acts as a controllable resistor. Moreover, the logic levels in the output signal are accurately controlled using a constant current source that is controlled by an operational amplifier and a resistor voltage divider at the output to pull the voltage level down by an amount that corresponds to the logical levels.

Abstract: An integrated device having a pad receiving, in a standard operative condition, an input signal having a first value and, in a test operative condition, a test voltage having a second value higher than the first value; an input stage connected to the pad and including an electronic component having a first terminal connected to the pad; a third-level detecting stage connected to the pad and supplying a logic third-level signal having a first level in presence of the input signal and a second level in presence of the test voltage; and a selector connected to a second terminal of the electronic component and structured to connect the second terminal to a reference potential in the presence of the first logic level of the third-level signal and to a biasing voltage higher than the reference potential and lower than the second value in the presence of the second logic level of the third-level signal.

Abstract: A semiconductor power converting apparatus including at least one series arrangement of MOS control semiconductor devices such as Insulator-gate Bipolar Transistors (IGBTs) or metal oxide MOS transistors which are respectively applied with a gate voltage under the control of corresponding a driver. The driver contains a supply line having a higher potential than a gate voltage of an IGBT coupled thereto when the IGBT is in a steady ON state, and is such that is causes an increase of the gate voltage of the IGBT in accordance with the current of the supply line when a potential difference between the power supply line and an emitter of the IGBT is constant and the collector voltage thereof exceeds a predetermined value under an ON state of the IGBT.

Abstract: A bipolar transistor breakdown voltage enhancement circuit extends the voltage swing which can be tolerated at an output terminal driven by an emitter follower-connected bipolar output transistor operating in a high impedance state. The enhancement circuit connects the base of the output transistor to a voltage which extends the allowable high impedance output voltage swing: an NPN output transistor's base is tied to a voltage that is the lower of the output voltage or ground, and a PNP output transistor's base is tied to a voltage which is the higher of the output voltage or VDD.

Abstract: A current mode logic circuit having npn transistors coupled to an NMOS current source provides a substantially constant current when controlled by an opamp comparator. A gate of the NMOS current source is directly coupled to an output terminal of the opamp. A source of the NMOS transistor is connected to one of the inputs of the comparator opamp. Another input terminal is connected to voltage source. The opamp compares the two inputs and provides an output signal which ensures that the opamp will provide a substantially constant current source.

Abstract: A level shifter for use in an integrated circuit that translates a binary input signal having a low voltage level to a binary output signal having a different voltage level. The level shifter (10) includes an input stage (20) that receives the input signal and provides control signals to a low state voltage translation circuit (30) and a high state voltage translation circuit (40). The low state voltage translation circuit (30) controls the level shifter (10) when the input signal is low and provides a bias signal to a bipolar device (Q2) adapted to pull the external output signal low. The high state voltage translation circuit (40) controls the level shifter (10) when the input signal is high and includes a voltage reducing circuit (44) operating as a current mirror with a pull-up PMOS transistor (P13) to couple an internal high voltage power supply to the output node (Vout).

Abstract: A circuit controls switching of a load between two supply terminals by a device in an emitter-switching configuration formed by a high-voltage bipolar power transistor and a low-voltage switch element. The bipolar power transistor has a collector connected to the load. The switch element has a first terminal connected to the emitter of the bipolar power transistor, a second terminal connected to ground, and a control terminal connected to a control terminal of the circuit. The circuit has a biasing circuit connected to a base terminal of the bipolar power transistor. To ensure that the bipolar power transistor operates in the saturation region throughout the period of conduction, even with a sinusoidal driving voltage, the biasing circuit includes a capacitive device and a charging circuit for charging the capacitive device to bias the base of the bipolar power transistor.

Abstract: A semiconductor integrated circuit device has an output circuit formed in a CMOS structure and composed of a P-channel MOS transistor that has its gate connected to an input terminal, has its source connected to a power source line, and has its drain connected to an output terminal and an N-channel MOS transistor that has its gate connected to the input terminal, has its source connected to ground, and has its drain connected to the output terminal. A first protection diode is formed in parallel with the source-drain channel of the P-channel MOS transistor. A first NPN-type transistor is so formed that its base is connected to ground and its collector-emitter path is connected in parallel with the source-drain channel of the P-channel MOS transistor. A second protection diode is formed in parallel with the source-drain channel of the N-channel MOS transistor. A thyristor circuit is provided in parallel with the source-drain channel of the N-channel MOS transistor.

Abstract: An electronic inductor circuit comprises a pair of cascoded Darlington bipolar or MOSFET transistors, configured such that the impedance presented by the collector (drain) of the top transistor of the electronic inductor is increased, relative to the other resistive components in the electronic inductor circuit and DAA. The impedance is increased to a magnitude such that small fluctuations in the collector (drain) impedance do not vary the over-all electronic inductor circuit impedance. Therefore, as heat generated by the circuit causes the impedance of the transistor in the electronic inductor to change, the impedance change does not adversely affect over-all modem circuit performance.

Abstract: In a digital BiCMOS process the storage capability of MOS transistors and the large transconductance of bipolar transistors can be utilized in such a way, that the speed is primarily determined by the capacitance seen by the MOS transistor (4) and the transconductance of the bipolar transistor (5). The advantages over the prior SI technique in CMOS are higher speed, smaller errors and higher accuracy. The advantages over other techniques in BiCMOS are smaller errors and higher accuracy. The unique feature of the invented technique is the combination of high input impedance of the MOS devices and high transconductance of the bipolar devices, where both devices are only available in BiCMOS process and not in the CMOS process.

Abstract: A device in an emitter-switching configuration comprises a high-voltage transistor having a first terminal connected directly to a first power terminal of the device, a control terminal connected to a control terminal of the device, and a second terminal. The device also includes a low-voltage transistor having a first terminal connected directly to the second terminal of the high-voltage transistor and a second terminal and a control terminal which are connected directly to a second power terminal and to the control terminal of the device, respectively. A circuit portion is provided for recovering an electrical charge discharged from the control terminal of the high-voltage transistor to the second terminal of the low-voltage transistor during the turning-off of the device.

Abstract: A small amplitude signal output circuit comprises an output section for receiving a logic signal to output a small amplitude signal, a level sense circuit for sensing the rise or fall of an output voltage at an output terminal, and a level control circuit for responding to the output of the level sense circuit to suppress the rise or fall of the output voltage. The output circuit suppresses voltage variations caused by variations in fabrication process of transistors, ambient temperature and source voltage noise.

Abstract: The disclosure relates to an electrical circuit used in automotive passenger restraint systems. The circuit utilizes reliable and inexpensive electrical components to provide one-shot actuation of a load. In addition, the circuit allows for very low quiescent current draw, making it ideal for automotive applications.

Abstract: A high power MOS transistor consists of a large number of sub-transistors (T1 to T6) connected in parallel. The gate electrodes of the sub-transistors (T1 to T6) can be driven individually via controllable switching elements (SW1 to SW6; SQ1 to SQ5).

Abstract: A circuit and method for implementing a MOSFET gate driver. Two bipolar NPN transistors (Q1, Q2), constructed to achieve rail-to-rail swings when driving a capacitive load (23) by overlapping their respective emitter regions (13) over their contained contact regions (19) to prolong internal device saturation and resulting turn-off delays, alternately connect the gate drive terminal (31) to either a supply terminal (HVDC) or an output terminal (29). Predrive circuitry for these transistors comprises NMOS transistors (M9, M18, M12 and M13). The NPN transistors are supplemented by a CMOS inverter (PMOS transistor M6 and NMOS transistor M17). A PMOS transistor (M7) provides additional base drive for transistor Q1 when the gate drive node is approaching the supply node. A diode (D2) protects transistor Q1 against base-emitter avalanche and protects transistor M7 from excessive drain-to-source voltages.

Abstract: An electronic delay circuit (10) for use in a detonator (100) has a switching circuit (20) and a timer circuit (22). Switching circuit (20) controls the flow of a stored charge of electrical energy from a storage capacitor (12) to a bridge initiation element such as a semiconductor bridge (18) or a tungsten bridge. The timing of the release of this energy is controlled by timer circuit (22). Switching circuit (20) is an integrated, dielectrically isolated, bipolar CMOS (DI BiCMOS) circuit, whereas timer circuit (22) is a conventional CMOS circuit. The use of a DI BiCMOS switching circuit allows for greater efficiency of energy transfer from the storage capacitor (12) to the semiconductor bridge (18) than has previously been attained.

Abstract: A drive circuit for a voltage controlled power switching device includes a transformer, a full-wave rectifier bridge coupled to the transformer, first and second capacitors connected in series between nodes of the full-wave rectifier bridge and first and second controlled switches coupled between a control electrode of the power switching device and the first and second capacitors, respectively, wherein each controlled switch has a control electrode coupled to a secondary winding of the trans-former. Current is provided by the first capacitor to the control electrode of the power switching device through the first controlled switch at the beginning of a negative pulse appearing at the secondary winding of the transformer and charging current is provided to the first capacitor from the secondary winding of the transformer through the full-wave rectifier bridge after the beginning of the negative secondary pulse.

Abstract: The present invention relates to a power amplifier having an output stage in MOS technology, including an upper half-output stage comprised of two P-channel MOS power transistors mounted as a current mirror, a lower half-output stage comprised of two N-channel MOS power transistors mounted as a current mirror, an output terminal of the amplifier corresponding to the common drains of a first MOS transistor of the upper stage and of a first MOS transistor of the lower stage, and a control stage in bipolar technology for setting, according to a control voltage, two control currents of the half-output stages.

Abstract: High-side physical interface driver circuit (10), for use in a variety of data transmission applications, includes an external connection (18) for connecting and providing drive current to an external physical interface. Output transistor (16) for channeling high-side drive current to external connection (18). Output transistor (16) includes base (18), collector (14), and emitter (24). Control transistor (28) controls the on state of output transistor (16) to supply high-side drive current to external connection (18). At least one shorting transistor (30) shorts base (19) of output transistor (16) to emitter (24), when high-side voltage reaches a predetermined minimum voltage level.

Abstract: The latch circuit having an input stage supplied with an input signal and, when activated, producing an output signal responsive to the input signal, and an latching stage coupled to the input stage and, when activated, holding a level of the output signal, the input stage including a pair of bipolar transistors Q1, Q2 coupled in a differential form, the latching stage including a pair of insulated gate field effect transistors M1, M2 coupled in a differential form.

Abstract: An output circuit of the present invention comprises a logic gate having a data signal and a control signal as input signals, a first P channel transistor having a gate connected to an output terminal of the logic gate and a source.cndot.drain path connected between a first power source terminal and a node, a first N channel transistor having a gate connected to the output terminal of the logic gate and a source.cndot.drain path connected between a second power source terminal and the node, a bipolar transistor having a base connected to the node, a collector connected to the first power source terminal and an emitter connected to an output terminal of the output circuit, a second P channel transistor having a gate connected to the output terminal of the logic gate and a source.cndot.drain path connected between the first power source terminal and the output terminal of the output circuit, a second N channel transistor having a gate connected to the output terminal of the logic gate and a source.cndot.

Abstract: A current memory cell comprises a first bipolar transistor providing a current source and coupled to the emitters of a second and a third bipolar transistor, the latter forming the storage elements of the memory cell. The memory cell is calibrated, to avoid mismatch between the second and third transistors, by adjustment of the current source via a parallel arrangement of a resistor and a field effect transistor in the emitter circuit of the first transistor.

Abstract: A pull-up output driver circuit includes a field effect transistor (FET) fabricated in a well region having a first conductivity type. The well region, in turn, is surrounded by a semiconductor region having a second conductivity type. The FET has a source connected to an output pad and a drain connected to a V.sub.CC voltage supply rail. The gate of the FET and the well region are connected to a driving circuit, and the semiconductor region is connected to the V.sub.CC voltage supply rail. A lateral bipolar transistor is formed by the drain, the source and the well region, and a vertical parasitic bipolar transistor is formed by the source, the semiconductor region and the well region. The driving circuit provides a signal (or signals) to the gate and well region to control the pull-up driver circuit. The FET turns on at a relatively low threshold voltage because the lateral bipolar transistor and the FET are turned on at substantially the same time.

Abstract: An integratable reversing switch selectively imposes a ground potential or a supply potential being positive relative thereto upon a terminal of a load having another terminal being connected to a supply potential that is negative relative to the ground potential. A first switch is connected between the load and the positive supply potential. A second switch is controlled in complementary fashion thereto and is connected between the load and the ground potential. The second switch is formed by an inversely operated DMOS field effect transistor.

Abstract: A BiCMOS circuit includes a CMOS circuit for inverting data applied to an input terminal and a first bipolar transistor, having a base connected to an output point of this CMOS circuit, a collector connected to a power supply voltage and an emitter connected to an output terminal, for charging the output terminal. The BiCMOS circuit also includes a second bipolar transistor, having a collector connected to the output terminal, for discharging the output terminal, a first MOS transistor of a first conductivity type connected in parallel between the base and the collector of the second bipolar transistor and a second MOS transistor of the first conductivity type connected in series with the first MOS transistor and having a gate connected to an output point of the CMOS circuit.

Abstract: A pull-up circuit including an NPN bipolar transistor, a P-MOS transistor connected in parallel with the bipolar transistor, a first CMOS inverter for receiving an input signal and controlling the P-MOS transistor, and a second CMOS inverter for receiving the output of the first inverter and controlling the bipolar transistor. An output stage includes the pull-up circuit and also includes a pull-down circuit comprising an N-MOS transistor, a second NPN bipolar transistor connected in parallel with the N-MOS transistor, a control circuit for switching on the second NPN bipolar transistor, and a third inverter whose input is connected to the output terminal and whose output controls the N-MOS transistor and provides a signal to the control circuit for switching off the second NPN bipolar transistor.

Abstract: A BIMOS driver circuit and method in which a push-pull pair of PNP-NPN bipolar transistors replaces the middle CMOS inverter stages in a circuit for driving a capacitive load. The rise and fall times of the circuit are made symmetrical by feeding back driver circuit output to operate a feedback transistor which removes the base charge stored in a PNP transistor of the bipolar push-pull pair, and maintains low propagation delay.

Abstract: The invention relates to a transconductor circuit with a double input and a single output, comprising two input transistors (M1, M2) whose primary conduction terminals (D1, S1, D2, S2) are respectively connected together; in this way, variations in load current and voltage can be made lower, thereby also lowering distortion from changes in their transconductance.

Abstract: A high speed switching technology suitable for implementing field programmable gate arrays using current mode logic in the high speed data path, and CMOS steering logic outside the high speed data path to enable the high speed switching logic and to implement multiplexer, selector and crossbar switch functions. High speed emitter follower logic compatible with the high speed switching logic for level shifting, buffering, and providing more current sink or source capacity is also disclosed.

Abstract: An improved current cell and current switch is described for use in digital-to-analog converters and other current mode circuits. The current switch is implemented using BiCMOS circuitry which is characterized by an absence of base current error and a switching speed which is approximately twice as fast as the switching speed of prior art MOS-based switches. According to one embodiment, the current cell is implemented in BiCMOS which offers higher output resistance, smaller minimum voltage, and improved accuracy over prior art MOS-based self-calibrated current cells. According to another embodiment, the current cell is implemented in CMOS and is characterized by a significant reduction in charge injection, leakage current and error due to coupling of the cell output voltage back to the storage node, as compared with prior art MOS-based current cells.

Abstract: A semiconductor memory device including a plurality of cell array sections each having a plurality of memory cells disposed in a matrix form, the plurality of cell array sections being juxtaposed in a row direction. Main word lines, are each provided in common for all of the plurality of cell array sections in each row, a row select signal being applied to each main word line. Section word lines are connected to memory cells, in each cell array section at each row, for activating the memory cells. Section select lines are provided for each cell array section, a section selection signal being applied to each section select line. Logical circuits are provided for each cell array section, each logical circuit being connected to each main word line and the section select line, executing a logical operation between the row select signal and the section select signal, and activating the section select line when the logical operation result satisfies a predetermined logical condition.