Abstract: An apparatus includes a capacitive device configured to provide bias power for a high-side switch, a gate drive path having variable resistance connected between the capacitive device and a gate of the high-side switch, wherein the gate drive path having variable resistance is of a first resistance value in response to a turn-on of the high-side switch, and the gate drive path having variable resistance is of a second resistance value in response to a turn-off of the high-side switch, and wherein the second resistance value is greater than the first resistance value, and a control switch connected between the gate of the high-side switch and ground.

Abstract: There is provided a radio frequency switch circuit including a first switch circuit unit connected between a first node connected to a first signal port and a common node connected to a common port, and operated according to a first control signal, a second switch circuit unit connected between a second node connected to a second signal port and the common node and operated according to a second control signal having a phase opposite to that of the first control signal, a first shunt circuit unit connected between the second node and a common source node and operated according to the first control signal, a second shunt circuit unit connected between the first node and the common source node, and a source voltage generating unit generating a source voltage, wherein the source voltage is lower than a high level of the first control signal and higher than a ground potential.

Abstract: An apparatus comprising an RF circuit, a converter circuit, an amplifier, and a delay circuit. The RF circuit may be configured to generate (i) an output signal and (ii) a first intermediate signal, in response to (i) an input signal and (ii) a control signal. The converter circuit may be configured to generate a second intermediate signal in response to the first intermediate signal. The amplifier may be configured to generate a third intermediate signal in response to the second intermediate signal. The delay circuit may be configured to generate the control signal in response to the third intermediate signal. The RF circuit may generate the output signal having a flattened response by providing pulse shaping in response to the control signal.

Abstract: The present invention provides a current limit circuit apparatus, coupled with the gate of a GaN transistor. The current limit circuit comprises a diode, a first transistor, a second transistor, a first resistor, a second resistor, a third resistor and a fourth resistor. The source and the drain of the first transistor couple with the diode. The source of the second transistor couples with the gate of the first transistor. The source of the first transistor couples with the first transistor. The source of the second transistor couples with the second resistor. The third resistor couples with the fourth resistor and the gate of the first transistor. The first transistor turned off and the gate current is limited. When the current of the gate of the GaN transistor exceeds the predetermined value, the breakdown voltage is increased by limiting the gate current.

Abstract: In accordance with embodiments of the present disclosure, a circuit may include a transmission switch and a dummy switch coupled at its output to the output of the transmission switch. The transmission switch may be configured to be selectively enabled and disabled based on a control signal received at a gate of the transmission switch. The transmission switch may be further configured to receive a first polarity of a differential signal at its input and pass the first polarity of the differential signal to its output when enabled. The dummy switch may be configured to be disabled and to receive a second polarity of the differential signal at its input, the second polarity of opposite polarity of the first polarity.

Abstract: Disclosed are an apparatus and a method for switching RF signals. An RF switching apparatus according to an exemplary embodiment of the present invention includes: a plurality of FETs passing or blocking high-frequency signals depending on driving voltage applied to a gate; a control power supply generating control voltage for controlling the passing or blocking of the high-frequency signals; and a charge pump increasing the level of the control voltage and outputting the corresponding voltage as the driving voltage. According to the exemplary embodiment of the present invention, it is possible to minimize insertion loss generated in an RF switch.

Abstract: A power switching circuit in CMOS technology has a power MOS transistor and a driver stage. The power MOS transistor is operated at a higher supply voltage in excess of its maximum allowable gate-source voltage; and the driver stage of the level shifter is operated at a lower supply voltage substantially lower than the supply voltage for the power MOS transistor. The driver stage includes a pair of driver MOS transistors coupled in series between a higher supply voltage rail and a reference potential rail, and at an interconnection node coupled to the gate of the power MOS transistor. The gates of the driver MOS transistors are AC-coupled to drive signals of mutually opposite phase; and the gates of the driver MOS transistors are each connected to the higher voltage supply rail through a respective parallel connection of a first resistor and a second resistor connected in series with a non-linear component.

Abstract: A one mode of a gate driving circuit that drives a gate electrode of an electric power switching element (9), comprising drive means (6) configured to supply to the gate electrode a current in accordance with a voltage applied across the principal electrodes of the electric power switching element (9), while utilizing a voltage produced by dividing a voltage applied across the principal electrodes by use of resistors (4a, 4b). Since the drive means (6) utilizes a voltage produced by a voltage dividing resistor circuit, which divides the voltage applied across the principal electrodes of the electric power switching element (9) as a power source voltage, only an addition of the dividing resistors (4a, 4b) makes it possible to constitute the power source for the current drive means (6).

Abstract: There is provided with a gate drive circuit including: a first switching element connected at one end to a power terminal; a second switching element connected at one end to the other end of the first switching element and connected at the other end to a reference terminal; a gate voltage output terminal which supplies a voltage at a node between the first switching element and the second switching element to a drive switching element as an output gate voltage; a gate voltage monitoring circuit which monitors the output gate voltage; an overcurrent detection circuit which monitors a current through the drive switching element; and a control circuit which generates a control voltage for controlling impedance of the second switching element based on an on/off signal for indicating that the drive switching element should be turned on/off, a gate voltage monitoring signal and an overcurrent monitoring signal.

Abstract: In an electronic high-frequency switch, comprising a field-effect transistor as the switching element, the size of the gate voltage may be switched between at least two values (?5.5 V and ?8 V), according to the desired linearity or switching speed. The switching device for the gate voltage is preferably coupled to a correction device in which different correcting values for the different gate voltage values corresponding to different correcting values for transmission or reflection by the high frequency switch are stored.

Abstract: A semiconductor device controller includes a current supply control unit for controlling a conduction state of a semiconductor device connected to a load in response to a control signal to supply current to the load, a current level judging unit for comparing one or more switching judgment values set in an area smaller than an overcurrent judgment value with current detected by a current detecting unit to carry out a current level judgment and a time constant changing unit for changing the circuit time constant of the input signal processing circuit in accordance with a judgment result by the current level judging unit.

Abstract: The drain of a power transistor M1 is connected to the non-inverting input terminal of an operational amplifier A and the drain of a transistor M2 is connected to the inverting input terminal of the operational amplifier A to make substantially equal the drain voltages of the power transistor M1 and the transistor M2, of which the gates are connected together and of which the sources are connected together. The drain current of the transistor M2 is outputted via a detection terminal 13 as a current signal proportional to the drain current of the power transistor M1.

Abstract: A gate sink circuit includes a comparator for monitoring a gate voltage of a switching device in comparison with a predetermined threshold value; a sink switching device connected between the gate of the switching device and a ground line; an inverter for inverting an output of the comparator; another inverter for inverting an input signal for the switching device; an AND circuit for operating the logic product of each output from the inverters; and an RS flip-flop FF provided with the output of the AND circuit as a set signal and the input signal as a reset signal, thereby securely keeping an off-state of the switching device and greatly reducing flow-through current in turn-on.

Abstract: A transconductor for generating a current corresponding to an input voltage. The transconductor has a crossing pairs structure. The transconductor comprises a first and a second MOS (Metal-Oxide Semiconductor) transistors mutually connected in series to a voltage source. A first bipolar transistor is connected to a current source. A collector terminal of the first bipolar terminal is connected to an output current terminal. An emitter terminal of the first bipolar terminal is connected to a gate terminal of the second MOS transistor. A second bipolar transistor is connected in series to the first bipolar transistor. A base terminal of the second bipolar transistor is connected to a node between the first MOS transistor and the second MOS transistor. A third MOS transistor is provided. A gate terminal of the third MOS transistor is connected to an input terminal for a signal from outside. A drain terminal of the third MOS transistor is connected to an emitter terminal of the second bipolar transistor.

Abstract: A power module is provided with an insulating substrate with a heat sink being bonded to one surface thereof and a circuit pattern being formed on the other surface. The circuit pattern is formed by an electrode layer. A switching semiconductor element and a free wheeling diode that is connected to a switching semiconductor element in anti-parallel therewith are placed on the circuit pattern. A controlling IC for controlling the switching semiconductor element is placed on the free wheeling diode. Thus, it is possible to make the entire power module compact, and it becomes possible to provide an inexpensive power module which can prevent the controlling IC from malfunctioning due to heat generated by the switching semiconductor element.

Abstract: The detection of the presence of a load associated with a power MOS transistor integrated with its control circuit, using a delay determined taking into account the detection with respect to the occurrence of a turn-off control order of the power transistor, and where the filtering time is controlled with the power transistor switching time.

Abstract: A buffer circuit having an input and output terminals includes a first Schottky gate transistor connected between a voltage setting node and ground, a load device connected between a power supply and the voltage setting node, a second Schottky gate transistor connected between the output terminal and ground, the gate of the second Schottky gate transistor being connected to the voltage setting node, a third Schottky gate transistor connected between the output terminal and the power supply, the gate of the third Schottky gate transistor being connected to the input terminal, a resistor means connected the gate of the first Schottky gate transistor and input terminal for increasing a voltage level applied to the gate of the third Schottky gate transistor.

Abstract: According to this invention, there is provided a drive apparatus for a power device having high- and low-voltage main electrodes and a control electrode, including a circuit for decreasing a voltage of the control electrode to a voltage of the control electrode which is not higher than a threshold voltage of the power device before a voltage between the high- and low-voltage main electrodes enters an overshoot region in a case where the power device is to be turned off. Therefore, electron injection can be stopped before the voltage between the main electrodes rises, the stability of the current density can be improved, and current concentration, oscillation, and the like can be prevented to improve reliability.

Abstract: The invention relates to a driver circuit for P-channel MOS switches including a power transistor having a control terminal and first and second conduction terminals, a controlled current generator connected to the control terminal for turning on the power transistor, a control circuit for controlling the turning on of the current generator, and a protection circuit coupled to the control terminal. The driver circuit may also include a second current generator connected to the control terminal of the power transistor which is in turn driven by the control circuit to control the transistor turn-off. Advantageously, the control circuit may also receive a control signal from the protection circuit at the end of the latter's action.

Abstract: In a switching circuit, low insertion loss and enough isolation can be ensured at a desired frequency at the same time. An inductor is externally connected in parallel with the path between the drain and source of each of field-effect transistors built in a switching integrated circuit, and the inductor and the OFF capacitance of the field-effect transistor are made to generate parallel resonance. At this time, by suitably adjusting the inductance, low insertion loss and enough isolation are ensured at a desired frequency at the same time.

Abstract: To keep a constant gate bias voltage to prevent a saturation output power from being decreased even when a GaAs FET for power amplification is operated near the saturation region, current amplification of an output from an operational amplifier (23) is performed by a transistor (24), and a gate bias voltage (Vg) is supplied to the gate of a GaAs FET (1). The gate bias voltage (Vg) is fed back to one input terminal of the operational amplifier (23), and a voltage obtained through voltage-dividing resistors (21, 22) is supplied to the other input terminal so that the operational amplifier serves as a voltage follower.

Abstract: A high-speed solid state buffer circuit and method for producing the same. A buffer circuit accepts logic input signals and transforms the signals to an output signal which can drive a heavy load. By using an output stage pull-up device that includes a parallel combination of an enhancement mode FET and a depletion mode FET, a solid-state buffer circuit with increased speed and output voltage swing is achieved. Most conveniently, the buffer takes the form of a logic inverter. However, the buffer can also be used to form a multiple input NOR gate. The circuit is most suitable for realization in GaAs technology.

Abstract: A monolithic upconverter integrated circuit is described which performs the first frequency conversion of a dual conversion cable television (CATV) receiver. The upconverter chip includes three functional blocks: a Gilbert type image-rejecting mixer, a phase splitter, and a voltage-controlled oscillator. Mixing is performed by a novel Gilbert type mixer including image-rejection inductors to improve the noise figure of the mixer. A differential circuit topology allows the monolithic upconverter chip to utilize a plastic dual inline batwing package without considerable performance loss. On-chip RF bypass networks, in the form of series RC terminations, also help compensate for the undesirable effects of pin inductances in the dual inline package. A resistor-based DC biasing scheme dramatically reduces power-up latency, allowing faster testing.