Insulated Gate Fet (e.g., Mosfet, Etc.) Patents (Class 327/434)
  • Patent number: 10348287
    Abstract: A switched-capacitor circuit, a radio frequency device and a switched-capacitor circuit manufacturing method, relating to discrete capacitance design. The switched-capacitor circuit comprises a first capacitor branch and a second capacitor branch, wherein each of the first capacitor branch and the second capacitor branch has at least one high-resistance resistor; and a transistor connecting the first capacitor branch and the second capacitor branch. This inventive concept effectively reduces the parasitic capacitance when the transistor is in an “OFF” state without affecting the quality factor when the transistor is in an “ON” state.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: July 9, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Hai Long Jia
  • Patent number: 10348192
    Abstract: An electronic device includes: a clock booster including a doubler capacitor, the clock booster configured to precharge the doubler capacitor to store a boosted intermediate voltage greater than an input voltage; a secondary booster including a booster capacitor, the secondary booster configured to use charges stored on the doubler capacitor to generate a stage output greater than the boosted intermediate voltage; and a connecting switch connected to the clock booster and the secondary booster, the connecting switch configured to electrically connect the doubler capacitor and the booster capacitor during a recycling duration for discharging a recycled charge from the booster capacitor to the doubler capacitor through the connecting switch, wherein the recycling duration is after generating the stage output.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: July 9, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Michele Piccardi
  • Patent number: 10277205
    Abstract: A single-pole double-throw switch. In some embodiments, the switch includes a first switching transistor connected between a common terminal of the single-pole double-throw switch and a first switched terminal of the single-pole double-throw switch, a second switching transistor connected between the common terminal of the single-pole double-throw switch and a second switched terminal of the single-pole double-throw switch, a first auxiliary transistor connected between the common terminal of the single-pole double-throw switch and a gate of the first switching transistor, and a second auxiliary transistor connected between the common terminal of the single-pole double-throw switch and a gate of the second switching transistor.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: April 30, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Vaibhav Tripathi
  • Patent number: 10200027
    Abstract: A radio frequency (RF) switch apparatus includes a first series switch circuit including a first series switch disposed between a first terminal and a second terminal and operating in response to a first gate signal, and a first capacitor circuit and a second capacitor circuit connected across the first series switch; a first shunt-bias circuit disposed between a first connection node between the first terminal and the first series switch, and a ground, and providing a power voltage or a ground potential to the first connection node in response to a second gate signal; and a first shunt-impedance circuit connected between the first connection node and the first shunt-bias circuit and adjusting path impedance in response to a third gate signal. Each of the first capacitor circuit and the second capacitor circuit passes an alternating current (AC) signal or blocks a direct current (DC) voltage.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: February 5, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jeong Hoon Kim, Hyun Paek, Byeong Hak Jo
  • Patent number: 10090674
    Abstract: A method includes providing supply voltages to a supply voltage switching circuit that controls routing of the supply voltages to power consuming circuitry associated with the supply voltage switching circuit. The method includes comparing the supply voltages, including using at least one relatively lower precision comparator to compare the supply voltages for a relatively large difference between the supply voltages; and using at least one relatively higher precision comparator to compare the supply voltages for a relatively smaller difference between the supply voltages. The method further includes, based on a result of comparing the supply voltages, selectively coupling the supply voltages to at least one of an isolation well and a power supply rail of the supply voltage switching circuit.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: October 2, 2018
    Assignee: Silicon Laboratories Inc.
    Inventors: Mohamed Mostafa Elsayed, Kenneth W. Fernald, Axel Thomsen
  • Patent number: 10020555
    Abstract: An electronic device includes circuitry configured to determine an antenna operation mode for one or more antenna arrays. The circuitry is further configured to control the one or more antenna arrays to operate in a combined antenna mode via a Wilkinson combiner. The circuitry is also configured to control the one or more antenna arrays to operate in an isolated antenna mode via a single-pole, multi-throw switch.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: July 10, 2018
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Saikat Sarkar, Seunghwan Yoon, Bagher Afshar, Michael Boers, Jesus Castaneda, Tirdad Sowlati
  • Patent number: 9973189
    Abstract: A large-power insulated gate switching device (e.g., MOSFET) is used for driving relatively large surges of pulsed power through a load. The switching device has a relatively large gate capacitance which is difficult to quickly discharge. A gate charging and discharging circuit is provided having a bipolar junction transistor (BJT) configured to apply a charging voltage to charge the gate of the switching device where the BJT is configured to also discontinue the application of the charging voltage. An inductive circuit having an inductor is also provided.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: May 15, 2018
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: David C. Wyland, Jonathan Alan Dutra
  • Patent number: 9866209
    Abstract: A radio frequency (RF) switch which comprises an RF domain section having a plurality of RF switching elements. A DC domain section is provided having circuitry configured for controlling the RF switching elements in response to one or more control signals. A resistive load is provided between the RF domain section and the DC domain section. A bypass circuit is configured for selectively bypassing at least a portion of the resistive load.
    Type: Grant
    Filed: January 6, 2015
    Date of Patent: January 9, 2018
    Assignee: Ferfics Limited
    Inventors: John Keane, Ian O'Regan
  • Patent number: 9825628
    Abstract: An electronic device includes a transmission interface and a control circuit. The transmission interface includes a signal reference contact and a signal transmission contact. The control circuit is electrically coupled between the signal reference contact and a ground layer, in which the control circuit is configured to selectively conduct the signal reference contact and the ground layer, and when the signal reference contact and the ground layer are conducted, the signal transmission contact is configured to transmit a first signal, and when the signal reference contact the ground layer are not conducted, the signal reference contact is configured to transmit a second signal. A transmission frequency of the second signal is less than a transmission frequency of the first signal.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: November 21, 2017
    Assignee: Synology Incorporated
    Inventors: Yen-Li Hsieh, Ming-Hung Tsai, Hung-Ming Tsai
  • Patent number: 9806637
    Abstract: An inverter comprises a first switch coupled to an input of an output filter and a positive dc bus, a second switch coupled to the input of the output filter and a negative dc bus, a first freewheeling apparatus coupled to the first switch, the second switch and ground, a first soft switching network coupled to the first freewheeling apparatus and the first switch, wherein the first soft switching network is configured such that the first switch is of a first zero voltage transition during a turn-on process of the first switch and a second soft switching network coupled to the first freewheeling apparatus and the second switch, wherein the second soft switching network is configured such that the second switch is of a second zero voltage transition during a turn-on process of the second switch.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: October 31, 2017
    Assignee: Futurewei Technologies, Inc.
    Inventor: Dianbo Fu
  • Patent number: 9722598
    Abstract: A semiconductor device, according to one possible configuration, includes switching circuits, each switching circuit comprising IGBT chips connected in series and clamping diodes. The semiconductor device also includes a first and a second wiring line and auxiliary emitter lines. The first wiring line and a first auxiliary emitter line connect the emitter terminals of IGBT chips of the first and second switching circuits. The second wiring line and another auxiliary emitter line connect the emitter terminals of the third IGBT chips of the first and second switching circuits. The wiring lines have a large current carrying capacity and a lower resistance value than their respectively connected auxiliary emitter line.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: August 1, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Hiroaki Ichikawa
  • Patent number: 9660475
    Abstract: A control circuit for reducing a charging time and a method thereof are provided. The charging device includes an input unit configured to receive a control signal indicating that applied power is process power, and a switch configured to cut off a path between a terminal set and a battery while the process power is applied, when the applied power is the process power.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: May 23, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ku-Chul Jung, KiSun Lee, Chul-Eun Yun, Seung-Su Hong
  • Patent number: 9621156
    Abstract: An analog switch may be maintained reliably in an off state. The switch comprises: a P-type first transistor having a source, a drain and a gate, a N-type second transistor having a source, a drain and a gate, and a switch control circuit to drive the gates of the first and second transistors. The drain of the first transistor and the source of the second transistor are connected at a first node, and the source of the first transistor and the drain of the second transistor are connected at a second node. When the voltage at the first or second nodes falls outside of a supply voltage range of the switch control circuit, the switch control circuit is operable, in response to a signal to make the switch high impedance, by adjusting the gate voltages of the first transistor and the second transistor.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: April 11, 2017
    Assignee: Analog Devices Global
    Inventor: David Aherne
  • Patent number: 9614520
    Abstract: A semiconductor switch includes a plurality of metal-oxide-semiconductor field effect transistors (MOSFETs) and a pad. The MOSFETs are connected in series between a first node and a second node. The pad is provided above one or more of MOSFETs in the plurality without being provided above other MOSFETs in the plurality. The pad is connected to the first node. A value of an off capacitance (as determined without inclusion of any parasitic capacitance between the pad and the MOSFET) for each the MOSFETs under the pad is smaller than a value of an off capacitance of each of MOSFETs not under than the pad.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: April 4, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yugo Kunishi, Toshiki Seshita
  • Patent number: 9614438
    Abstract: A method, in some embodiments, comprises: receiving a feedback voltage signal generated by a switch-mode power supply; generating an error signal based on a difference between a switching frequency of the switch-mode power supply and a target frequency; and using the error signal to adjust a ripple amplitude of the feedback voltage signal to control said switching frequency in the switch-mode power supply.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: April 4, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Robert Davis
  • Patent number: 9608625
    Abstract: According to one embodiment, a semiconductor device includes: a voltage line to which a first voltage is applied; a first circuit configured to operate by using the first voltage; and a second circuit configured to control a connection between the voltage line and the first circuit. The second circuit includes: at least one first switch circuit configured to connect the first circuit and the voltage line based on a first control signal; and a second switch circuit including a plurality of switch sections configured to connect the first circuit and the voltage line based on a plurality of second control signals different from the first control signal.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: March 28, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shuichi Kunie, Masanori Inoue
  • Patent number: 9590621
    Abstract: The present application is directed to drive arrangement for semiconductor switches and in particular to a method of driving the gate of a switch with pulses corresponding to turn-on and turn-off commands through separate turn-on and turn-off transformers. The application provides a fail safe reset feature, a more efficient turn-on circuit and an energy recovery circuit for recovering energy from the gate upon turn-off. The application also provides a novel arrangement for assembling multiple pulse transformers on a circuit board.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: March 7, 2017
    Assignee: Icergi Limited
    Inventor: George Young
  • Patent number: 9577627
    Abstract: First and second external terminals are connected to high-voltage and low-voltage terminals, respectively, of a direct-current voltage source circuit in which first and second direct-current voltage sources are connected in series. A third external terminal is connected to a connecting point between the first and second direct-current voltage sources. A first switching element is connected between the first and fourth external terminals. A second switching element is connected between the fourth and second external terminals. A first AC switch unit includes third and fourth switching elements connected in inverse series between the third and fourth external terminals. A second AC switch unit includes fifth and sixth switching elements connected in inverse series between the third and fourth external terminals. The first and second AC switch units are connected in parallel. The first and second switching elements and the first and second AC switch units are incorporated in one module.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: February 21, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventor: Akiko Goto
  • Patent number: 9465395
    Abstract: A voltage generating circuit includes: (1) a driving unit having an input terminal and an output terminal, wherein the input terminal is configured to receive an input signal, wherein when the input signal is at a first logic level, power is configured to be charged from a first voltage terminal to the output terminal, and when the input signal is at a second logic level, power is configured to be discharged from the output terminal to a second voltage terminal; (2) a first switch configured to couple the second voltage terminal to a capacitance-compensating terminal based on the input signal; (3) a compensating capacitor configured to be coupled between the capacitance-compensating terminal and a third voltage terminal; and (4) a second switch configured to couple the capacitance-compensating terminal to a fourth voltage terminal based on the input signal.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: October 11, 2016
    Assignee: M31 Technology Corporation
    Inventor: Hung-Cheng Fan
  • Patent number: 9401601
    Abstract: A circuit for protecting a voltage supply to a sensor from a transient event is provided. The circuit includes at least one buffer capacitor configured to provide output during the transient event, the output substantially equivalent to output of a regulated supply during normal operation of the sensor. A method of fabrication and a sensor are disclosed.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: July 26, 2016
    Assignee: Sensata Technologies, Inc.
    Inventors: Eric A. Wolf, David L. Corkum
  • Patent number: 9368221
    Abstract: A device for use with non-volatile memory, includes a first transistor of a first channel type coupled between first and second nodes, including a control gate supplied with a first control signal having a first phase, a second transistor of a second channel type different from the first channel type including a first terminal coupled to the first node, a second terminal coupled to a third node, a back gate coupled to the first terminal thereof, and a control gate supplied with a second control signal having a second phase substantially opposite to the first phase, a third transistor of the second channel type including a first terminal coupled to the second node, a second terminal coupled to the third node, a back gate coupled to the first terminal thereof, and a control gate supplied with the second control signal, and a protection circuit coupled between the first and second node.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: June 14, 2016
    Assignee: PS4 LUXCO S.A.R.L.
    Inventors: Stefano Sivero, Chiara Missiroli
  • Patent number: 9322852
    Abstract: Gate drive faults are detected for an inverter which comprises a phase switch having an insulated gate, such as an IGBT. A complementary transistor pair is adapted to receive a supply voltage and a pulse-width modulated (PWM) signal to alternately charge and discharge the insulated gate. A comparator compares the voltage at the insulated gate with a reference voltage representing a gate drive fault to generate a first logic signal. A latch samples the first logic signal when the PWM signal has a value corresponding to charging the insulated gate. A logic circuit inhibits charging of the insulated gate when the latched logic signal indicates the gate drive fault. An insulated gate voltage less than the reference voltage is indicative of an under-voltage fault as well as other device failures of the IGBT or the complementary transistors.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: April 26, 2016
    Assignee: FORD GLOBAL TECHNOLOGIES, LLC
    Inventors: Lihua Chen, Dong Cao, Yan Zhou, Craig Rogers
  • Patent number: 9305917
    Abstract: A high electron mobility transistor includes a buffer region and a barrier region adjoining and extending along the buffer region, the buffer and barrier regions are formed from semiconductor materials having different band-gaps and form an electrically conductive channel from a two-dimensional charge carrier gas. A gate structure is configured to control a conduction state of the channel and includes an electrically conductive gate electrode, a first doped semiconductor region, a second doped semiconductor region, and a resistor. The first doped semiconductor region is in direct electrical contact with a first section of the gate electrode. The second doped semiconductor region is in direct electrical contact with a second section of the gate electrode. The first and second doped semiconductor regions form a p-n junction with one another. The first and second sections of the gate electrode are electrically coupled to one another by the resistor.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: April 5, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Gilberto Curatola, Oliver Haeberlen
  • Patent number: 9287793
    Abstract: In one embodiment, method of generating a control signal for an isolated power supply, can include: (i) generating a first ground noise component with a first predetermined proportionality to a ground noise signal; (ii) generating a first peak signal based on a first control signal having the ground noise signal, where the first peak signal comprises a second ground noise component with a second predetermined proportionality to the ground noise signal; (iii) generating a second control signal based on a difference between the first peak signal and the first ground noise component; and (iv) controlling, by the second control signal, a switch of the isolated power supply.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: March 15, 2016
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventors: Lingdong Zhang, Chen Zhao
  • Patent number: 9197216
    Abstract: A system includes an inverter element to gate forward current flow from a first signal source, and a reverse current inhibition element to block reverse current flow towards the first signal source from a second signal source.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: November 24, 2015
    Assignee: Broadcom Corporation
    Inventor: Dario Soltesz
  • Patent number: 9190992
    Abstract: The present invention provides a semiconductor device of a bi-directional analog switch having a high linearity and a low electric power loss. An ultrasonic diagnostic apparatus having a high degree of detection accuracy, comprising the semiconductor device, is also provided. A semiconductor device of a bi-directional analog switch, comprising a switch circuit capable of switching ON or OFF bi-directionally, and built-in driving circuits for the switch circuit, wherein the driving circuit is connected to first and second power supplies, and a first power supply voltage is higher than a maximum voltage of a signal applied to an input/output terminal of the switch circuit, a second power supply voltage is lower than a minimum voltage of a signal applied to an input/output terminal of the switch circuit, and the driving circuit comprises a Zener diode and a p-type MOSFET connected in series between the first power supply and the switch circuit.
    Type: Grant
    Filed: October 27, 2011
    Date of Patent: November 17, 2015
    Assignee: Hitachi Power Semiconductor Device, Ltd.
    Inventors: Kenji Hara, Junichi Sakano
  • Patent number: 9178412
    Abstract: A bidirectional switch circuit includes two switching elements connected to conduct a current in both directions. The two switching elements are connected in series to each other. Of the two switching elements, the switching element to which a reverse voltage is applied, a voltage of a source of one of the switching elements being higher than a voltage of a drain of the one, is configured to conduct a current from the source to the drain even when an on-drive signal is not being input to a gate terminal of the one.
    Type: Grant
    Filed: January 18, 2010
    Date of Patent: November 3, 2015
    Assignee: Daikin Industries, Ltd.
    Inventors: Reiji Kawashima, Kazushi Hisayama, Hiroshi Hibino, Morimitsu Sekimoto, Toshiyuki Maeda, Sumikazu Matsuno
  • Patent number: 9164522
    Abstract: A wake up circuit includes a bias signal control block configured to receive a sleep signal and to generate a plurality of bias control signals. The wake up circuit further includes a bias supply block configured to receive each bias control signal of the plurality of bias control signals and to generate a header bias signal. The bias supply block includes a first bias stage configured to receive a first bias control signal of the plurality of bias control signals, and to control the header bias signal to be equal to a first voltage. The bias supply block further includes a second bias stage configured to receive a second bias control signal of the plurality of bias control signals, and to control the header bias signal to be equal to a second voltage different from the first voltage. The wake up circuit further includes a header configured to receive the header bias signal, and to selectively connect a supply voltage to a load based on the header bias signal.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: October 20, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jung-Ping Yang, I-Han Huang, Chia-En Huang, Fu-An Wu, Chih-Chieh Chiu
  • Patent number: 9093836
    Abstract: A description is given of a method for the pulsed control of a transistor which has a control terminal and a load path. The load path of the transistor is connected in series with a load. A control circuit is provided for a transistor. In the method, the transistor is controlled with a control pulse of a first type, which has a first control level at least for a first time duration, before a control pulse of a second type, which has a second control level, which is higher in comparison with the first control level. A voltage across the load path of the transistor is evaluated and the pulsed control is terminated if the voltage across the load path exceeds a predefined threshold value.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: July 28, 2015
    Assignees: Infineon Technologies Austria AG, ZF Friedrichshafen AG
    Inventors: Tomas Manuel Reiter, Juergen Kett, Bernhard Doemel
  • Patent number: 9048838
    Abstract: In an embodiment, a switching circuit includes input drain, source and gate nodes, a high voltage depletion mode transistor including a current path coupled in series with a current path of a low voltage enhancement mode transistor, and a current sense circuit for sensing the current flowing through a current sense path.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: June 2, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Klaus Schiess, Rainald Sander
  • Publication number: 20150149794
    Abstract: Methods and systems to adjust a resistance between a supply grid and a power-gated grid during an active state of a power-gated circuitry in response to load changes in the circuitry to maintain a relatively consistent IR droop. Subsets of power gates (PGs) may be selectively enabled and disabled based on changes in a load factor, such as a voltage, which may be monitored at a gated power distribution grid and/or proximate to a transistor gate within the power-gated circuitry. The adjusting may be performed to minimize a difference between the monitored voltage and a reference, such as with successive approximation or CMS software. PG subsets may be distributed within one or more layers of an integrated circuit (IC) die and may be selectively enabled/disabled based on location. PGs may be embedded within lower layers of an integrated circuit (IC) die, such as within metal layers of the IC die.
    Type: Application
    Filed: December 27, 2011
    Publication date: May 28, 2015
    Applicant: Intel Corporation
    Inventors: Michael Zelikson, Vjekoslav Svilan, Norbert Unger, Shai Rotem
  • Patent number: 9041457
    Abstract: An electronic apparatus includes a switching element which has a control terminal and is driven by controlling voltage of the control terminal, a driving power supply circuit which supplies voltage required for driving the switching element, an on-driving circuit which is connected to the driving power supply circuit and the control terminal of the switching element and is supplied with voltage from the driving power supply circuit, and which applies a constant current to the control terminal of the switching element to charge the control terminal, thereby turning on the switching element, and at least one diode which is connected between the on-driving circuit and the control terminal of the switching element. The on-driving circuit applies a constant current to the control terminal of the switching element through the diode.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: May 26, 2015
    Assignee: DENSO CORPORATION
    Inventors: Jyunji Miyachi, Tsuneo Maebara, Kazunori Watanabe
  • Patent number: 9041456
    Abstract: A transistor being one of an IGBT and a MOSFET and arranged near a gate control circuit applies a gate control signal from the gate control circuit to the gate of a transistor arranged far from the gate control circuit. A gate control signal is applied via a resistive element to the transistor arranged near the gate control circuit.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: May 26, 2015
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Maki Hasegawa, Masataka Shiramizu, Shinji Sakai, Takuya Shiraishi
  • Patent number: 9035691
    Abstract: A gate drive circuit is disclosed that charges the gate of a switching transistor to a voltage that is high enough to turn the switching transistor fully on and then prevent the charge from flowing back into the gate drive circuit. The gate drive circuit works with a ground rectifier switch by providing a fully differential connection of the switching transistor and its capacitor and resistor in parallel with the antenna.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: May 19, 2015
    Assignee: Atmel Corporation
    Inventor: Wolfgang Roeper
  • Patent number: 9024677
    Abstract: A method and apparatus for current drain switching with a replica loop. The method comprises the steps of: matching a voltage across a current sense resistor with a voltage created by a reference current across a matched reference resistor; replicating an operating point of an output transistor using a scaled matched replica of the output transistor and the current sense resistor. The method then shifts a feedback voltage from the output sense resistor to the matched replica sensor and shifts the output of a gate from an output transistor to the replica transistor. A first switch is then actuated in order to preserve the gate charge of the output transistor. A second switch is actuated to sample and hold a drain voltage in the buffer in order to bias the drain of the replica transistor. A third switch is then activated to stop the output current.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: May 5, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Hua Guan, Eric B. Zeisel, Qi Lou
  • Patent number: 9024678
    Abstract: A circuit arrangement including a first transistor, a second transistor and a third transistor. The first transistor and the second transistor are configured so that the current flowing through the first transistor is proportional to the current flowing through the second transistor and the third transistor. The first transistor, the second transistor and the third transistor are configured to operate in an ohmic mode. The second transistor and the third transistor are coupled in series to each other. The first transistor, the second transistor and the third transistor match each other in at least one characteristic.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: May 5, 2015
    Assignee: Infineon Technologies AG
    Inventors: Daniele Vacca Cavalotto, Enrico Orietti
  • Publication number: 20150117065
    Abstract: A gate driving circuit may include: a bias unit receiving an input signal having preset high and low signal levels, including a first N-MOSFET turned on in the case in which the input signal has the high level and a first P-MOSFET turned on in the case in which the input signal has the low level, and supplying bias powers by the turning-on of the first N-MOSFET and the first P-MOSFET; and an amplifying unit including a second N-MOSFET turned on by receiving the bias power supplied from the first N-MOSFET in the case in which the input signal has the high level and a second P-MOSFET turned on by receiving the bias power supplied from the first P-MOSFET turned on in the case in which the input signal has the low level and providing a gate signal depending on the turning-on of the second N-MOSFET and the second P-MOSFET.
    Type: Application
    Filed: May 27, 2014
    Publication date: April 30, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Sang Hyun CHA, Deuk Hee PARK, Yun Joong LEE, Joong Ho CHOI, Je Hyeon YU, Hyeon Seon YU, Chang Seok LEE
  • Publication number: 20150116025
    Abstract: In an embodiment, a switching circuit includes input drain, source and gate nodes, a high voltage depletion mode transistor including a current path coupled in series with a current path of a low voltage enhancement mode transistor, and a current sense circuit for sensing the current flowing through a current sense path.
    Type: Application
    Filed: October 30, 2013
    Publication date: April 30, 2015
    Inventors: Ralf Otremba, Klaus Schiess, Rainald Sander
  • Patent number: 9019001
    Abstract: A DC-coupled two-stage gate driver circuit for driving a junction field effect transistor (JFET) is provided. The JFET can be a wide bandgap junction field effect transistor (JFET) such as a SiC JFET. The driver includes a first turn-on circuit, a second turn-on circuit and a pull-down circuit. The driver is configured to accept an input pulse-width modulation (PWM) control signal and generate an output driver signal for driving the gate of the JFET.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: April 28, 2015
    Assignee: Power Integrations, Inc.
    Inventors: Robin Lynn Kelley, Fenton Rees
  • Patent number: 9013226
    Abstract: Various embodiments of circuits configured to improve second order harmonic distortion of Metal Oxide Semiconductor (MOS) transistors operating in linear region are provided. In one embodiment, a circuit includes an averaging circuit configured to average signals at a drain and a source of a MOS transistor and provide the averaged signal to a gate of the MOS transistor, and one or more current sources coupled with the gate; the circuit is configured to vary voltage at the gate so as to vary a resistance of the MOS transistor. The averaging circuit comprises a first MOS circuit coupled between the drain and the gate, a first capacitor coupled in parallel to the first MOS circuit between the drain and the gate, a second MOS circuit coupled between the source and the gate, and a second capacitor coupled in parallel to the second MOS circuit between the source and the gate.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: April 21, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Shagun Dusad, Visvesvaraya Pentakota
  • Patent number: 9013212
    Abstract: An output driver circuit includes first, second, third, and fourth transistors having a common current path, wherein a gate of the first transistor receives a first switching signal, a gate of the second transistor receives a first reference voltage, a gate of the third transistor receives a second reference voltage, and a gate of the fourth transistor receives a second switching signal, and wherein a first capacitor is coupled between the gate of the first transistor and the gate of the third transistor, a second capacitor is coupled between the gate of the second transistor and the gate of the fourth transistor, and an output signal is provided at a node coupling the second and third transistors.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: April 21, 2015
    Assignee: STMicroelectronics International N.V.
    Inventor: Vinod Kumar
  • Patent number: 9007117
    Abstract: According to an embodiment, a solid-state switching device includes a high-voltage switching transistor including a source, a drain and a gate, and being adapted for switching a high voltage on the basis of a switching signal, and a switching driver circuit operationally connected to the high-voltage switching transistor, the switching driver circuit including a low-voltage driver transistor including a source, a drain and a gate, connected in series to the high-voltage switching transistor and being adapted for transferring the switching signal to the high-voltage switching transistor, wherein the high-voltage switching transistor is arranged source-down on top of the drain of the low-voltage driver transistor.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: April 14, 2015
    Assignee: Infineon Technologies Dresden GmbH
    Inventors: Rolf Weis, Anthony Sanders
  • Patent number: 9000831
    Abstract: A pass gate circuit includes a first transistor coupled between an input node (receiving an input signal) and an output node (outputting an output signal). A second transistor is configured to generate a voltage difference in response to a bias current flowing therethrough, wherein that voltage difference is applied between a first gate of the first transistor and the output node. A differential amplifier functions to compare the voltage at the output node to a reference voltage and generate the bias current in response to that comparison.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: April 7, 2015
    Assignee: STMicroelectronics R&D (Shanghai) Co. Ltd
    Inventors: Fei Wang, KunKun Zheng
  • Patent number: 8994443
    Abstract: In a bidirectional switch using a metal-oxide-semiconductor field-effect transistor (MOSFET), the source terminal and the backgate terminal of the MOSFET are connected to each other via a transfer gate. A switch may be used between the connection point of the backgate terminal and the transfer gate of the MOSFET and the ground potential (where the MOSFET is an n-channel type) or supply potential (where the MOSFET is a p-channel type).
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: March 31, 2015
    Assignee: Semiconductor Components Industries, LLC
    Inventor: Kouichi Yamada
  • Patent number: 8994438
    Abstract: A control voltage is generated at a control input of a semiconductor circuit breaker by an actuation circuit at switching flanks of a switching signal, said control voltage having a profile which is flattened in relation to the profile of the switching signal. With the disclosed method, the switching losses in a semiconductor circuit breaker are reduced. By defining a value for a switching parameter of a control device of the actuation circuit, the switching behavior of the actuation circuit can be influenced by the switching parameter. A specific parameter value of the switching parameter can be varied during operation of the actuation circuit.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: March 31, 2015
    Assignee: Siemens Aktiengesellschaft
    Inventors: Swen Gediga, Karsten Handt, Rainer Sommer
  • Patent number: 8988133
    Abstract: There are disclosed herein various implementations of nested composite switches. In one implementation, a nested composite switch includes a normally ON primary transistor coupled to a composite switch. The composite switch includes a low voltage (LV) transistor cascoded with an intermediate transistor having a breakdown voltage greater than the LV transistor and less than the normally ON primary transistor. In one implementation, the normally on primary transistor may be a group III-V transistor and the LV transistor may be an LV group IV transistor.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: March 24, 2015
    Assignee: International Rectifier Corporation
    Inventor: Michael A. Briere
  • Publication number: 20150070077
    Abstract: Signal distribution circuitry for use in an integrated circuit, the signal distribution circuitry comprising: first and second output nodes, for connection to respective output signal lines; first and second supply nodes for connection to respective high and low voltage sources; and switching circuitry connected to the first and second output nodes and the first and second supply nodes and operable based on an input signal to conductively connect the first and second output nodes either to the first and second supply nodes, respectively, in a first state when the input signal has a first value, or to each other, in a second state when the input signal has a second value different from the first value, so as to transmit output signals dependent on the input signal via such output signal lines.
    Type: Application
    Filed: September 12, 2013
    Publication date: March 12, 2015
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Ian Juso DEDIC, Gavin Lambertus ALLEN
  • Publication number: 20150070076
    Abstract: A half bridge is described with at least one transistor having a channel that is capable in a first mode of operation of blocking a substantial voltage in at least one direction, in a second mode of operation of conducting substantial current in one direction through the channel and in a third mode of operation of conducting substantial current in an opposite direction through the channel. The half bridge can have two circuits with such a transistor.
    Type: Application
    Filed: November 12, 2014
    Publication date: March 12, 2015
    Inventors: James Honea, Yifeng Wu
  • Patent number: 8977217
    Abstract: Embodiments provide a switching device including one or more field-effect transistors (FETs). In embodiments, a negative bias circuit is configured to generate a negative voltage signal based on a radio frequency (RF) signal applied to the circuit. When the FET is in an off state, the negative voltage signal is provided to a gate terminal of the FET.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: March 10, 2015
    Assignee: TriQuint Semiconductor, Inc.
    Inventors: Richard Connick, Arjun Ravindran
  • Patent number: 8975950
    Abstract: Radio-frequency (RF) switch circuits are disclosed providing improved switching performance. An RF switch system includes at least one field-effect transistor (FET) disposed between a first node and a second node, each having a respective source, drain, gate, and body. The system includes a coupling circuit including a first path and a second path, the first path being between the respective source or the respective drain and the respective gate of the at least one FET, the second path being between the respective source or the respective drain and the respective body of the at least one FET. The coupling circuit may be configured to allow discharge of interface charge from either or both of the coupled gate and body.
    Type: Grant
    Filed: July 6, 2013
    Date of Patent: March 10, 2015
    Assignee: Skyworks Solutions, Inc.
    Inventors: Anuj Madan, Fikret Altunkilic, Guillaume Alexandre Blin