Abstract: A rectifier circuit includes: a first input line to which a first alternating-current voltage is supplied and that is wired along a first direction; a second input line to which a second alternating-current voltage is supplied and that is wired along the first direction on a second direction side of the first input line; a first output line that is configured to output a first rectified voltage and is wired along the second direction; a second output line that is configured to output a second rectified voltage and is wired along the second direction on a first direction side of the first output line; a first rectifier element that is arranged corresponding to an intersection of the first input line and the first output line; a second rectifier element that is arranged corresponding to an intersection of the second input line and the first output line; a third rectifier element that is arranged corresponding to an intersection of the first input line and the second output line; and a fourth rectifier element t

Abstract: A passive sensor for detecting the operation of a light source includes a photosensor which, when illuminated by the light source, delivers a voltage to a field effect transistor (FET) which can switch a circuit to control a device at a remote location. The FET transitions rapidly between very low resistance (short circuit) and very high resistance (open circuit), allowing a binary indication to be given in the circuit. The circuit can be used to charge an electrical storage device to allow later download of recent status of the lamp by detecting the charge stored in the device.

Abstract: An actuation device for actuating a circuit breaker, has a circuit arrangement and a plurality of resistor devices, wherein a plurality of first switching elements of the circuit arrangement are connected to a respectively assigned first voltage source and a respectively assigned resistor device and have a switching input that is connected to an actuation logic unit, wherein this actuation logic unit furthermore has a superordinate actuation input and a plurality of sensor inputs. A method for operating such an actuation device is also presented, wherein, during the switching-on or the switching-off process of the circuit breaker, the plurality of first switching elements are switched on in a clocked manner and therefore generate a target voltage profile at the control input of the circuit breaker.

Abstract: Circuitry for an ultrasound device is described. The ultrasound device may include a symmetric switch positioned between a pulser and an ultrasound transducer. The pulser may produce bipolar pulses. The symmetric switch may selectively isolate a receiver from the pulser and the ultrasound transducer during a transmit mode of the device, when the bipolar pulses are provided by the pulser to the ultrasound transducer for transmission, and may selectively permit the receiver to receive signals from the ultrasound transducer during a receive mode. The symmetric switch may be provided with a well switch to remove well capacitances in a signal path of the device.

Abstract: A gate driver device includes a first field effect transistor and a first driver circuit. The first field effect transistor includes a first gate electrode and a first backgate structure. The first driver circuit supplies a first backgate drive signal to the first backgate structure.

Abstract: A face-down mountable chip-size package semiconductor device includes a semiconductor layer and N (N is an integer greater than or equal to three) vertical MOS transistors in the semiconductor layer. Each of the N vertical MOS transistors includes, on an upper surface of the semiconductor layer, a gate pad electrically connected to a gate electrode of the vertical MOS transistor and one or more source pads electrically connected to a source electrode of the vertical MOS transistor. The semiconductor layer includes a semiconductor substrate. The semiconductor substrate functions as a common drain region for the N vertical MOS transistors. For each of the N vertical MOS transistors, a surface area of the vertical MOS transistor in a plan view of the semiconductor layer increases with an increase in a maximum specified current of the vertical MOS transistor.

Abstract: According to one embodiment, electronic circuitry includes: a detection circuit including a diode, a cathode side of the diode being connected to one end of a semiconductor switching element and an anode side of the diode being connected to a first node; a comparator circuit configured to compare a voltage of the first node and a threshold voltage and generate a first signal; a first filter connected between the first node and another end of the semiconductor switching element and configured to suppress the voltage of the first node in a first period based on a control signal indicating turn-on of the semiconductor switching element; and a control circuit configured to determine at least one of the threshold voltage and the first period based on the first signal.

Abstract: A driving apparatus drives a load. An N-channel MOSFET is disposed downstream of the load on a current path of a current that flows via the load. A circuit resistor is connected between a direct current power source and the gate of the MOSFET. A first switch is connected between the gate and the source of the MOSFET. A microcomputer outputs a voltage relative to a potential at an output terminal of a second switch to a control terminal of the second switch. As a result, the second switch is turned ON or OFF. A switching circuit turns the first switch ON when the second switch is turned ON and turns the first switch OFF when the second switch is turned OFF.

Abstract: The present disclosure provides a voltage fluctuation detection circuit, which includes a voltage adjustment circuit and a comparator. The voltage adjustment circuit includes an adjustment circuit input terminal to receive the operating voltage, a first adjustment circuit output terminal to output a first voltage, and a second adjustment circuit output terminal to output a second voltage that is step-shaped, the second voltage differs from the first voltage by a bias voltage at the beginning of a preset clock period and falls within a first amplitude within the preset clock period, the magnitude of the bias voltage is related to the first voltage. The comparator includes: a first comparator input terminal to receive the first voltage, a second comparator input terminal to receive the second voltage, and a comparator output terminal to output a comparison result of the first voltage and the second voltage.

Abstract: An apparatus comprises an energy transfer device configured to supply power from a primary side of an isolation barrier through the isolation barrier to a secondary side of the of the isolation barrier for driving a gate of a switch for controlling output of the switch at the secondary side. The apparatus comprises a monitoring component. The monitoring component is configured to monitor an operating state of the switch. The monitoring component is configured to evaluate the operating state to determine whether a fault has occurred, perform a countermeasure, and/or provide a signal of the fault.

Abstract: A circuit to multiplex supply voltages may include a set of chains of transistors. Each chain of transistors may correspond to a voltage supply that is desired to be multiplexed and may include a set of transistors coupled in series. A first end terminal of each chain of transistors may be coupled to a corresponding voltage supply, and a second end terminal of each chain of transistors may be coupled to an output terminal of the circuit. A given supply voltage may be selected by turning on transistors in a chain of transistors that corresponds to the given supply voltage and turning off transistors in other chains of transistors.

Abstract: A gate driver for a panel, wherein the gate driver comprises at least an output channel unit, each of the output channel unit includes a first driving unit; a second driving unit; a first current limit circuit, coupled to the first driving unit, configured to control an output current according to an output voltage of the gate driver to limit an output current slew rate of the gate driver; and a second current limit circuit, coupled to the second driving unit, configured to control the output current according to the output voltage of the gate driver to limit the output current slew rate of the gate driver.

Abstract: A circuit comprising a NMOS having a gate coupled to a first node and a source terminal coupled to a second node, a second NMOS having a gate coupled to the second node and a source terminal coupled to an output node, a PMOS having a gate coupled to a third node, a drain terminal coupled to a fourth node, and a source terminal coupled to a fifth node, and a second PMOS having a gate coupled to the fourth node, a drain terminal coupled to the output node, and a source terminal coupled to the fifth node. The circuit also includes a voltage protection sub-circuit coupled to the first node, a fast turn-off sub-circuit coupled to the output node, a fast turn-on sub-circuit coupled to the third and fourth nodes, and a node initialization sub-circuit coupled to the first, second, and fourth nodes and the fast turn-on sub-circuit.

Abstract: Disclosed are a gate-on voltage generation circuit, a display panel driving device and a display device. The gate-on voltage generation circuit includes an on/off voltage output terminal, a power management integrated circuit and a voltage switching circuit. The power management integrated circuit includes a detection terminal connected to the on/off voltage output terminal, is configured for detecting a voltage output by the on/off voltage output terminal, and outputting first switch control signal or second switch control signal according to the voltage output from the on/off voltage output terminal. The voltage switching circuit includes a first input terminal for inputting a first voltage value and a second input terminal for inputting a second voltage value larger than the first voltage value. The voltage switching circuit outputs the first voltage value upon receiving the first switch control signal, and outputs the second voltage value upon receiving the second switch control signal.

Abstract: A communication device includes a first client group in a first region; a second client group in a second region different from the first region; a first data hub configured to generate first burst data and a first control packet based on first client data received from the first client group; a second data hub configured to generate second burst data and a second control packet based on second client data received from the second client group; and a data transfer unit connected to the first data hub and the second data hub via a control protocol, the data transfer unit configured to, store the first burst data in a target memory based on the first control packet, and store the second burst data in the target memory based on the second control packet.

Abstract: A microcontroller unit for controlling a three-level inverter including delayed fault protection is provided. The microcontroller unit includes an input port configured to receive a trip signal from a fault detection module, and a plurality of EPWM modules, each configured to control a power switch within the three-level inverter. The microcontroller unit includes an auxiliary EPWM module configured to receive the trip signal and produce a delayed trip signal, and processing circuitry coupled with the input port, the plurality of EPWM modules, and the auxiliary EPWM module. The processing circuitry is configured to, in response to activation of the trip signal, direct one of the plurality of EPWM modules to shut off its corresponding power switch upon activation of the trip signal, and to direct a different one of the plurality of EPWM modules to shut off its corresponding power switch upon activation of the delayed trip signal.

Abstract: A driver circuit may be configured to control a power switch. The driver circuit may comprise an output pin configured to deliver signals to a gate of the power switch to control an ON/OFF state of the power switch, and a comparator configured to compare a gate-to-source voltage of the power switch to a first threshold when the power switch is ON and to compare the gate-to-source voltage of the power switch to a second threshold when the power switch is OFF.

Abstract: Techniques are provided for writing a high-level state to a memory cell capable of storing three or more logic states. After a sense operation performed by a first sense component and a second sense component, a digit line may be isolated from the first sense component and the second sense component. The high-level state may be stored in the memory cell, then a second state may be stored in the memory cell, in which the second state may be a mid-level state or a low-level state. The second state may be stored based on a write-back component identifying that the second state was stored in the memory cell before the write back procedure.

Abstract: Provided are a semiconductor device and a sensor system capable of achieving improvement of noise resistance. Thus, an output circuit 106a in the semiconductor device includes: input terminals 207n, 207p; and an output terminal 208; an output amplifier 201 connecting the input terminals 207n, 207p to the output terminal 208; a feedback element 203 returning the output terminal 208 to the input terminal 207n; a switching transistor 204; and a resistance element 206. A drain of the switching transistor 204 is connected to the input terminal 207n. The resistance element 206 is provided between a back gate of the switching transistor 204 and a power source Vdd and has impedance of a predetermined value or more for suppressing noise of a predetermined frequency generated at the input terminal 207n.

Abstract: A drive circuit drives a power semiconductor element including a control terminal, a first main electrode, and a second main electrode. The drive circuit includes a first switching-off circuit and a second switching-off circuit each for turning off the power semiconductor element. The second switching-off circuit is lower in impedance than the first switching-off circuit. In a case where the power semiconductor element is turned off, only the first switching-off circuit operates when the power semiconductor element is in an unusual state, and the first switching-off circuit and the second switching-off circuit complementarily operate when the power semiconductor element is in a normal state.

Abstract: A switch comprising: a channel path comprising first and second MOS transistors with common source and gate terminals and drain terminals defining first and second terminals of the channel path; and control circuitry comprising: a third MOS transistor comprising: a gate coupled to the common source terminal; a source coupled to the common gate terminal by a resistor; and a drain coupled to a first reference terminal; a first current source coupled between the first reference terminal and the common gate terminal for providing a first current; a second current source coupled between the source terminal of the third MOS transistor and a second reference terminal for providing a second current greater than the first current; and a first switching arrangement configured to selectively enable and disable the first current source; and a second switching arrangement configured to selectively couple the common source terminal to the second reference terminal.

Abstract: Provided is a gate drive device, including: a gate drive unit for driving a gate of a switching element; a measurement unit for measuring a parameter that changes according to a current flowing through the switching element; and a switching unit for switching a changing speed of a gate voltage of the switching element by the gate driving unit after a first reference period from a start of turning off the switching element based on the parameter.

Abstract: Time folding power combining circuits convert a continuous wave into a pulsed wave of greater peak power.

Abstract: A switching circuit includes a first transmission terminal, a second transmission terminal, a third transmission terminal, and a variable impedance circuit. The first and the second transmission terminals coupled to a common node form a first transmission path. The third transmission terminal coupled to the common node forms a second transmission path with the first transmission terminal. The variable impedance circuit has a first terminal coupled between the common node and the third transmission terminal, and a second terminal coupled to a first reference potential terminal. When the first transmission path transmits a first signal, a first frequency bandwidth range provided by the variable impedance circuit is determined according to a first frequency of the first signal so that the variable impedance circuit provides low impedance in the first frequency bandwidth range, and the first frequency bandwidth range covers the first frequency.

Abstract: An apparatus is provided which comprises: a power gate device coupled to a gated power supply node and an ungated power supply node; and a control circuitry coupled to the power gate device, wherein the control circuitry is to turn on the power gate device by providing at least two bias voltages separated in time to gradually turn on the power gate device.

Abstract: A hybridization system for an electric device having two terminals and two states including a closed state allowing an electric current to circulate between the two terminals and an open state blocking the circulation of the electric current between the terminals, the device being suitable for an electric arc to be generated during the switching from the closed state to the open state. The hybridization system includes: two conductors connected to the two terminals of the electric device; a timer switch having two terminals connected to the two conductors and the timer switch being suitable for being in the open state by default and, after a first predetermined duration following the triggering of the electric arc, switching to the closed state for a second predetermined duration, and an electric power supply of the timer switch, connected to the two conductors in order to derive its power only from the electric energy provided by the electric arc.

Abstract: A semiconductor device having a power source terminal, a ground terminal, an input terminal, an output terminal and a status output terminal. The semiconductor device includes a power semiconductor switch connected between the power source terminal and the output terminal, a logic circuit connected to the power semiconductor switch, and a ground terminal opening detection circuit connected to the ground terminal and the status output terminal. The logic circuit is configured to generate, according to a signal inputted to the input terminal, an output logic signal for turning on or off the power semiconductor switch. The ground terminal opening detection circuit is configured to detect a state in which the ground terminal is opened, based on a rise in a potential of the ground terminal, and to output, via the status output terminal, a detection signal in response to the detection of the state.

Abstract: An apparatus includes a plurality of semiconductor switches. A first bus interconnects first terminals of the semiconductor switches in a first chain and provides a first impedance between the first terminals of switches of the first chain. A second bus interconnects second terminals of the semiconductor switches in a second chain and provides a second impedance greater that the first impedance between the second terminals of the switches of the second chain. The apparatus may be implemented as a laminated bus assembly including respective overlapping conductor plates, wherein the second bus includes a plate having subregions defined by features, such as slots or grooves, that provide the second impedance.

Abstract: A dual mode focal plane array having a readout integrated circuit (IC) is provided herein that is electrically switchable between a first mode (e.g., direction injection mode) and a second mode (e.g., buffered direction injection) based in part on a level of a detection current. The IC includes a switching network disposed between an operational amplifier and a switching element to transition the IC between the first and second mode responsive to a control signal. The control signal can include instructions to open or close the one or more switches of the switching network and thus transition the IC between the different modes.

Abstract: An apparatus can include: a drive circuit for a floating switch having first and second transistors coupled in series, where gate terminals of the first and second transistors are coupled together, and source terminals of the first and second transistors are coupled together; a control circuit coupled to the gate terminals of the first and second transistors, and being configured to control on and off states of the first and second transistors; and a clamp circuit configured to clamp gate-source voltages of the first and second transistors to maintain current switching states of the first and second transistors.

Abstract: A transistor arrangement and an electronic circuit with a transistor arrangement are disclosed. The transistor arrangement includes: drift and drain regions arranged in a semiconductor body and connected to a drain node; at least one load transistor cell having a source region integrated in a first active region of the semiconductor body; at least one sense transistor cell having a source region integrated in a second active region of the semiconductor body; a first source node electrically coupled to the source region of the at least one load transistor cell; a second source node electrically coupled to the source region of the at least one sense transistor cell; and a compensation resistor connected between the source region of the at least one sense transistor cell and the second source node. The compensation resistor is integrated in the semiconductor body and has a resistive conductor which includes a doped semiconductor material.

Abstract: A front-end circuit includes a first filter on a path connecting a common terminal and a first input/output terminal, a second filter on a path connecting the common terminal and a second input/output terminal, and a first switch on the path connecting the common terminal and the first input/output terminal. The first switch receives at least one of a first control signal and a second control signal. The first control signal increases a difference between a first voltage applied to the first switch to turn the first switch to a non-conductive state and a threshold voltage determining whether or not the first switch is turned to a conductive state. The second control signal increases a difference between a second voltage applied to the first switch to turn the first switch to the conductive state and the threshold voltage.

Abstract: A gate drive circuit has a capacitor and a gate drive voltage source connected in series with a gate terminal of a voltage-driven switching device. The gate drive source voltage feeds, as a gate drive voltage, a voltage higher than the sum of the voltage applied to a gate-source parasitic capacitance of the switching device when the switching device is in a steady ON state and the voltage applied to, of any circuit component interposed between the gate drive voltage source and the gate terminal of the switching device, a circuit component other than the capacitor (such as an upper transistor forming the output stage of the driver). No other circuit component (such as a resistor connected in parallel with the capacitor) is essential but the capacitor as the sole circuit component to be directly connected to the gate terminal of the switching device.

Abstract: An apparatus comprises one or more metal-oxide-semiconductor field effect transistors, a charge pump, and a driver circuit. The one or more metal-oxide-semiconductor field effect transistors are generally connected in series between a supply voltage and an output terminal. The charge pump may be configured to generate a voltage of sufficient magnitude relative to the supply voltage to switch the one or more metal-oxide-semiconductor field effect transistors into a conductive state. The driver circuit is generally coupled between the charge pump and the one or more metal-oxide-semiconductor field effect transistors. The driver circuit may be configured to drive the one or more metal-oxide-semiconductor field effect transistors to provide at least one of power switching, reverse polarity protection, power switching with reverse polarity protection, or over voltage inhibition.

Abstract: This application relates to methods and apparatus for voltage control, and in particular to maintain safe voltages for components of audio driving circuits that are operable in a high voltage mode. An audio driving circuit (100) may include a power supply module (106) and may be operable such that, in use, a voltage magnitude at a source terminal of at least a first transistor (306, 309, 603, 605) of the audio driving circuit can exceed its gate-source voltage tolerance. A voltage generator (111P) is configured to output a first intermediate voltage (VSAFEP) to an intermediate voltage path for use as a gate control voltage for at least the first transistor, to maintain its gate-source voltage below tolerance. An intermediate path voltage clamp (114P) is provided for selectively clamping the intermediate voltage path to a voltage level, so as to maintain the magnitude of the gate-source voltage of the first transistor below tolerance.

Abstract: The present disclosure describes aspects of a sub-device field-effect transistor architecture for integrated circuits. In some aspects, an integrated field-effect transistor (FET) is implemented with multiple FET sub-devices. During operation, source-side FET sub-devices of the integrated FET may operate in the linear region instead of in saturation. Operating in the linear region, the source-side FET sub-devices of the integrated FET may exhibit less threshold voltage or current sensitivity than other drain-side FET sub-devices that operate in saturation. A device layout of the integrated FET may be designed such that the less sensitive source-side FET sub-devices surround or protect the other more sensitive drain-side FET sub-devices from random variations or density issues at edges of the device layout. By so doing, a threshold voltage or current sensitivity of the integrated FET may be reduced, resulting in improved matching between integrated FET devices.

Abstract: An IGBT modeling method includes creating piece-wise line functions describing a collector-emitter voltage vce, a collector current ic and a gate-emitter voltage vge of the IGBT during a switching-on transient based on an internal structure of the IGBT and transient processes of the IGBT. The IGBT modeling method further includes creating piece-wise line functions describing the collector-emitter voltage vce, the collector current ic and the gate-emitter voltage vge of the IGBT during a switching-off transient based on the internal structure of the IGBT and the transient processes.

Abstract: A high throw-count multiple-pole FET-based RF switch architecture that provides good RF performance in terms of insertion loss, return loss, isolation, linearity, and power handling. A common port RFC is coupled along a common path to multiple ports RFn. Embodiments introduce additional common RF path branch isolation switches which are controlled by state dependent logic. The branch isolation switches help to isolate the unused branch ports RFn and the unused portion of the common path from the active portion of the common path, and thereby reduce the reactive load attributable to such branches that degrades RF performance of the ports RFn “closer” to the common port RFC. The branch isolation switches can also be used to reconfigure the switch architecture for a multiplex function as well as separate switch path banks for re-configurability of purpose, tuning, or varying switch throw counts and packaging options.

Abstract: Devices and methods are provided where a control terminal resistance of a transistor device is set depending on operating conditions within a specified range of operating conditions.

Abstract: A light emitting device and an element substrate which are capable of suppressing variations in luminance intensity of a light emitting element among pixels due to characteristic variations of a driving transistor without suppressing off-current of a switching transistor low and increasing storage capacity of a capacitor. A gate potential of a driving transistor is connected to a first scan line or a second scan line, and the driving transistor operates in a saturation region. A current controlling transistor which operates in a linear region is connected in series to the driving transistor. A video signal which transmits a light emission or non-emission of a pixel is input to the gate of the current controlling transistor through a switching transistor.

Abstract: In a power module that has a carrier substrate with at least one unipolar semiconductor component as a power switch, the unipolar semiconductor component is configured such that a temperature rise of the semiconductor component, from a first temperature up to which the semiconductor component heats in operation at 50% full load, to a second temperature up to which the semiconductor component heats in operation at full load, is less than a temperature rise of the semiconductor component from an initial temperature at zero load to the first temperature. As a result of the reduced temperature rise between 50% and 100% full load the service life of the power module can be lengthened.

Abstract: A power circuit switching device includes two switching terminals; a high voltage depletion mode transistor and a low voltage enhancement mode transistor arranged in series between the two switching terminals; a control circuit having a first input for receiving a switching signal and a second input for receiving a signal for activating the device, the control circuit being configured to put the switching device into an inactive state or an active state; a driver circuit for applying the switching signal to the gate of the high voltage transistor, the driver circuit being supplied with a first voltage from a first voltage source (VDR+) and with a second voltage from a second voltage source (VDR?), the first and second voltages being respectively higher and lower than the threshold voltage of the high voltage transistor; and at least one programming module associated with the driver circuit, configured to program the incoming current which is to be injected at the gate of the high voltage transistor, and the o

Abstract: A radio frequency switching device includes a switching circuit including first and second transistors; a gate resistor circuit including a first gate resistor and a second gate resistor, the first gate resistor connected to a gate of the first transistor and the second gate resistor connected to a gate of the second transistor; a gate buffer circuit including a first gate buffer and a second gate buffer, the first gate buffer being connected to the first gate resistor to provide a first gate signal to the first transistor through the first gate resistor, the second gate buffer being connected to the second gate resistor to provide a second gate signal to the second transistor through the second gate resistor; and a delay circuit to generate the first gate signal having a first switching time and the second gate signal having a second switching time different than the first switching time.

Abstract: A clock gating circuit is disclosed. The clock gating circuit includes an input circuit configured to receive an enable signal and clock enable circuitry configured to receive an input clock signal. The clock gating circuit also includes a latch that captures and stores an enabled state of the enable signal when the enable signal is asserted. An output circuit is coupled to the latch, and provides an output signal corresponding to a state of the clock signal when the latch is storing the enabled state. The clock gating circuit is arranged such that, when the latch is not storing the enabled state, no dynamic power is consumed responsive to state changes of the input clock signal.

Abstract: Certain aspects of the present disclosure relate to multi-band filter architectures and methods for filtering signals using the multi-band filter architectures. One example multi-band filter generally includes a transconductance-capacitance (gm-C) filter and a reconfigurable load impedance coupled to an output of the gm-C filter, the reconfigurable load impedance comprising a first gyrator circuit coupled to a second gyrator circuit.

Abstract: A vehicle powertrain has a power inverter that includes a load switch with a main emitter and a current mirror emitter, a variable resistor coupled between the current mirror emitter and the main emitter, and a controller. The controller may be configured to adjust a gate voltage based on a voltage across the variable resistor, and responsive to the gate voltage exceeding a Miller plateau gate voltage, increase a variable resistor resistance such that feedback increases as the load switch saturates.

Abstract: An electronic device includes: a clock booster including a doubler capacitor, the clock booster configured to precharge the doubler capacitor to store a boosted intermediate voltage greater than an input voltage; a secondary booster including a booster capacitor, the secondary booster configured to use charges stored on the doubler capacitor to generate a stage output greater than the boosted intermediate voltage; and a connecting switch connected to the clock booster and the secondary booster, the connecting switch configured to electrically connect the doubler capacitor and the booster capacitor during a recycling duration for discharging a recycled charge from the booster capacitor to the doubler capacitor through the connecting switch, wherein the recycling duration is after generating the stage output.

Abstract: A switched-capacitor circuit, a radio frequency device and a switched-capacitor circuit manufacturing method, relating to discrete capacitance design. The switched-capacitor circuit comprises a first capacitor branch and a second capacitor branch, wherein each of the first capacitor branch and the second capacitor branch has at least one high-resistance resistor; and a transistor connecting the first capacitor branch and the second capacitor branch. This inventive concept effectively reduces the parasitic capacitance when the transistor is in an “OFF” state without affecting the quality factor when the transistor is in an “ON” state.

Abstract: A single-pole double-throw switch. In some embodiments, the switch includes a first switching transistor connected between a common terminal of the single-pole double-throw switch and a first switched terminal of the single-pole double-throw switch, a second switching transistor connected between the common terminal of the single-pole double-throw switch and a second switched terminal of the single-pole double-throw switch, a first auxiliary transistor connected between the common terminal of the single-pole double-throw switch and a gate of the first switching transistor, and a second auxiliary transistor connected between the common terminal of the single-pole double-throw switch and a gate of the second switching transistor.

Abstract: A radio frequency (RF) switch apparatus includes a first series switch circuit including a first series switch disposed between a first terminal and a second terminal and operating in response to a first gate signal, and a first capacitor circuit and a second capacitor circuit connected across the first series switch; a first shunt-bias circuit disposed between a first connection node between the first terminal and the first series switch, and a ground, and providing a power voltage or a ground potential to the first connection node in response to a second gate signal; and a first shunt-impedance circuit connected between the first connection node and the first shunt-bias circuit and adjusting path impedance in response to a third gate signal. Each of the first capacitor circuit and the second capacitor circuit passes an alternating current (AC) signal or blocks a direct current (DC) voltage.