Abstract: An autonomous power supply switch with a main supply input and a backup supply input and a supply output to supply the power provided at the main supply input and to switch to the backup supply input, if the power at the main supply input is below a switch threshold. The switch includes a first switch transistor connected between the main supply input and the supply output with its gate/base connected to a first steering point of the switch and a second switch transistor connected between the backup supply input and the supply output with its gate/base connected to a second steering point of the switch; an inverter or Schmitt trigger with its input connected to the second steering point and its output connected to the first steering point and its power supply connected to the backup supply input of the switch.

Abstract: Switching device includes a first terminal, a second terminal, a first transistor, a second transistor, a third transistor, a fourth transistor, and a control circuit. The control circuit is configured to control the first transistor, the second transistor, the third transistor, and the fourth transistor. The control circuit is configured to, when supply of the first voltage to the third node is stopped, turn the second transistor from an off state to an on state, turn the third transistor and the fourth transistor from an on state to an off state, and after a first period passes, turn the first transistor from an off state to an on state.

Abstract: A control unit has an input with a positive and negative connectors. The control unit also includes an output and with an electronic switch. The switch has a first connector, a second connector and a control connector, and has an on-state resistance between its first and second connector that depends on a control voltage at the control connector of the switch. The first connector is connected to the connector for the positive potential of the input, the second connector is connected to the connector for the positive potential of the output, and the control connector is connected to a trigger circuit. A second controllable switch is also included with a first connector connected to the second connector of the first switch, a second connector connected to the control connector of the first switch, and a control connector connected to the connector for the negative potential of the input.

Abstract: A gate drive circuit is used in a dynamic characteristic test on a power semiconductor, the gate drive circuit includes a voltage source configured to change a gate voltage of a gate of the power semiconductor, a plurality of resistance setting circuits connected in parallel with the voltage source and the gate, and a switching circuit connecting at least one resistance setting circuit of the resistance setting circuits to the voltage source and the gate.

Abstract: A signal output circuit including a first transistor coupled to a power supply line to receive a power supply voltage, a diode provided between the power supply line and a gate electrode of the first transistor, and a current generation circuit provided on a ground side with respect to the diode, the current generation circuit being configured to generate a current for the diode, upon turning on of the first transistor, and to increase the current, upon the power supply voltage dropping below a predetermined level.

Abstract: An electronic circuit is disclosed. The electronic circuit includes: a half-bridge with a first transistor device (1) and a second transistor device (1a); a first biasing circuit (3) connected in parallel with a load path of the first transistor device (1) and comprising a first electronic switch (31); a second biasing circuit (3a) connected in parallel with a load path of the second transistor device (1a) and comprising a second electronic switch (31a); and a drive circuit arrangement (DRVC). The drive circuit arrangement (DRVC) is configured to receive a first half-bridge input signal (Sin) and a second half-bridge input signal (Sina), drive the first transistor device (1) and the second electronic switch (31a) based on the first half-bridge input signal (Sin), and drive the second transistor device (1a) and the first electronic switch (31) based on the second half-bridge input signal (Sina).

Abstract: A power module including a plurality of drive devices. Each drive device includes a high-side drive element and a low-side drive element that drive a load, a high-side control circuit that controls the high-side drive element, and a low-side control circuit that controls the low-side drive element. Each of the high-side and low-side control circuits includes an abnormality detection circuit that detects an abnormal state of the high-side or low-side drive element, a capability-switch-function-equipped drive circuit that switches a drive capability of the high-side or low-side drive element, responsive to the detection of the abnormal state by any one of the abnormality detection circuits in the plurality of drive devices, and a drive capability switch circuit that switches a drive capability of the capability-switch-function-equipped drive circuit, responsive to the detection of the abnormal state by the abnormality detection circuit.

Abstract: Provided herein may be a test circuit of an electronic device, the electronic device including the test circuit, and an operating method thereof. The electronic device may include analog circuits, a control circuit configured to connect, to an output terminal, each of a plurality of nodes respectively included in the analog circuits to an output terminal, a control signal generator configured to generate a control signal for controlling the control circuit based on an input signal received from an external device, and a switching circuit disposed on an electrical path for connecting the plurality of nodes and the control circuit to each other and configured to be electrically open during a preset time amount from a time point at which a voltage from an external power source starts to be applied to the control circuit.

Abstract: A display substrate, a manufacturing method thereof, a display panel and a display device are provided. The display substrate includes: an array layer on a base substrate and a light shielding layer on a side of the array layer away from the base substrate, wherein the array layer includes a driving transistor and a switching transistor, the switching transistor is a transistor connected to a gate electrode of the driving transistor, a plurality of imaging pinholes are formed in the light shielding layer, and a first orthographic projection of the imaging pinholes onto the base substrate and a second orthographic projection of an active layer pattern of the switching transistor in the array layer onto the base substrate do not overlap at least in part.

Abstract: A stacked voltage regulator (VR) that pre-charges inductor switching node to mitigate EOS. The stacked VR comprises at least three n-type devices (low-side) and three p-type devices (high-side) coupled in series. The three p-type stacked devices are part of a high-side of the VR. Node Vx coupling one of the n-type devices and one of the p-type devices is coupled to an inductor, which is also coupled to a load capacitor. During the inductor charging phase, in the low-to-high transition, a small p-type device is added to pre-charge the inductor switching node (Vx) from “0” to “VDD?Vth” through the low-side by connecting a generated mid-rail “Vdd” to the internal node of the n-type stack for a short period (e.g., about 50 ps). A controlled conductance modulation (CCM) scheme on the high-side top switch during the inductor charging phase is used to mitigate the ringing without controlling the gate drive strength.

Abstract: A semiconductor device includes: a first transistor having a first electrode, a second electrode, and a third electrode coupled to a load; a second semiconductor having a first electrode, a second electrode, and a third electrode configured to output a second current corresponding to a first current that flows through the load; and a third transistor coupled in series with the second transistor, to thereby receive the second current; an output circuit configured to output a second voltage by amplifying a difference between a first voltage at the third electrode of the first transistor and a reference voltage, and a fourth voltage by amplifying a difference between a third voltage at the third electrode of the second transistor and the reference voltage; and an operational amplifier configured to control the third transistor, based on the second and fourth voltages such that the first voltage and the third voltage match.

Abstract: Aspects of the present disclosure are directed to a circuit and methods of operating the same to provide an off-state circuit path with a programmable impedance in combination with a negative gate-to-source voltage Vgs for power transistors in an inverter configuration to prevent gate voltage glitches. Gate voltage glitch may occur due to Miller current generation across the gate path of a power transistor in the off state during rapid voltage transient dV/dt when the other, complementary power transistor is switched on or off. According to one aspect, using a negative gate-to-source voltage to turn-off a power transistor may mitigate gate voltage spikes caused by a large voltage transient when the complimentary power transistor is turned on, thus preventing parasitic turn-on of the power transistor.

Abstract: A processing device identifies clock phases of a multiphase clock system. The processing device selects a first clock phase and a second clock phase of the clock phases. The processing device determines an aggregate phase distance between the first clock phase and the second clock phase over multiple clock periods. The processing device determines, based on the aggregate phase distance, an aggregate time duration between the first clock phase and the second clock phase over the multiple clock periods of the multiphase clock system.

Abstract: A shunt switch. In some embodiments, the shunt switch includes a transistor stack including a first transistor and a capacitor. The transistor stack may have a first end terminal and a second end terminal, the first transistor being connected to the first end terminal, the first end terminal being connected to a switching terminal of the shunt switch. The capacitor may have a first terminal connected to the second end terminal of the transistor stack, and a second terminal connected to a low-impedance node.

Abstract: In an example, a method includes providing a signal to a driver for a switching voltage regulator to turn off a high-side field effect transistor (FET) of the switching voltage regulator. The method also includes reducing a voltage at a source of the high-side FET. The method includes responsive to the signal, turning off a pull-down FET coupled to a gate of the high-side FET. The method also includes commutating current from the high-side FET to a low-side FET.

Abstract: A semiconductor device for driving an inductive load. The semiconductor device includes an output-stage switch connected to the inductive load for operating the inductive load; a voltage detection circuit configured to output a detection signal responsive to an overvoltage being higher than or equal to a clamp voltage; a drive circuit configured to apply a drive signal having a first threshold voltage to a gate of the output-stage switch, responsive to the overvoltage being lower than the clamp voltage, to turn on the output-stage switch; and a voltage application circuit configured to apply a voltage signal having a second threshold voltage higher than the first threshold voltage to the gate of the output-stage switch, responsive to the overvoltage being higher than or equal to the clamp voltage and upon receiving the detection signal from the voltage detection circuit, to turn on the output-stage switch.

Abstract: To provide a power converter which can detect occurrence of excess current in early stage without providing a blanking time when the detection of excess current is not performed after the turn on of the switching device, and which can protect the power converter. A power converter includes a time change detection circuit that outputs a detection signal according to a time change rate of a main voltage; an excess current determination circuit that generates an excess current occurrence signal of normal current state when the detection signal is less than a first threshold value, and generates the excess current occurrence signal of excess current state when the detection signal is not less than the first threshold value; and a driving circuit that generates the driving voltage of OFF state when the drive command signal is ON state and the excess current occurrence signal is excess current state.

Abstract: An electronic module is provided including a circuit board defining a longitudinal axis and having a first surface and a second surface. A module housing is provided having a bottom surface and side walls extending from the bottom surface to form an open face through which the circuit board is received. Power switches configured as an inverter circuit to drive an electric motor are mounted on the second surface of the circuit board facing the bottom surface of the module housing, and a series of heat sinks are discretely mounted on the first surface of the circuit board facing the open face opposite the power switches. Potting material is disposed in the distance between the circuit board and the bottom surface of the module housing to cover the power switches. Thermal vias are disposed through the circuit board between corresponding ones of the heat sinks and the power switches.

Abstract: The present invention provides a drive module for a GaN transistor, including: a first pull-down transistor and a gate ringing and overshoot suppression unit, where the gate ringing and overshoot suppression unit and a first end of the first pull-down transistor are directly or indirectly connected to a gate of the GaN transistor, the gate ringing and overshoot suppression unit is connected between a second end of the first pull-down transistor and the ground; the gate ringing and overshoot suppression unit is configured to: when a gate voltage of the GaN transistor drops, control the release of a gate charge of the GaN transistor with a first impedance if the gate voltage is higher than a specified threshold; and control the release of the gate charge of the GaN transistor with a second impedance if the gate voltage is less than the specified threshold, where the first impedance is less than the second impedance.

Abstract: A switch circuit electrically connected to a power source and a first control source and including a plurality of switch bridge arms is provided. Each of the plurality of switch bridge arms includes a first switch and a second switch electrically connected in series. A loop formed by the first switch, the second switch and the power source is defined as a power loop. A loop formed by the first control source and the first switch is defined as a first control loop. A first mutual inductance is formed between the power loop and the first control loop. Among all the first switches, the first switch with the longer power loop has the smaller first mutual inductance.

Abstract: A rectifier circuit includes: a first input line to which a first alternating-current voltage is supplied and that is wired along a first direction; a second input line to which a second alternating-current voltage is supplied and that is wired along the first direction on a second direction side of the first input line; a first output line that is configured to output a first rectified voltage and is wired along the second direction; a second output line that is configured to output a second rectified voltage and is wired along the second direction on a first direction side of the first output line; a first rectifier element that is arranged corresponding to an intersection of the first input line and the first output line; a second rectifier element that is arranged corresponding to an intersection of the second input line and the first output line; a third rectifier element that is arranged corresponding to an intersection of the first input line and the second output line; and a fourth rectifier element t

Abstract: A passive sensor for detecting the operation of a light source includes a photosensor which, when illuminated by the light source, delivers a voltage to a field effect transistor (FET) which can switch a circuit to control a device at a remote location. The FET transitions rapidly between very low resistance (short circuit) and very high resistance (open circuit), allowing a binary indication to be given in the circuit. The circuit can be used to charge an electrical storage device to allow later download of recent status of the lamp by detecting the charge stored in the device.

Abstract: An actuation device for actuating a circuit breaker, has a circuit arrangement and a plurality of resistor devices, wherein a plurality of first switching elements of the circuit arrangement are connected to a respectively assigned first voltage source and a respectively assigned resistor device and have a switching input that is connected to an actuation logic unit, wherein this actuation logic unit furthermore has a superordinate actuation input and a plurality of sensor inputs. A method for operating such an actuation device is also presented, wherein, during the switching-on or the switching-off process of the circuit breaker, the plurality of first switching elements are switched on in a clocked manner and therefore generate a target voltage profile at the control input of the circuit breaker.

Abstract: A gate driver device includes a first field effect transistor and a first driver circuit. The first field effect transistor includes a first gate electrode and a first backgate structure. The first driver circuit supplies a first backgate drive signal to the first backgate structure.

Abstract: Circuitry for an ultrasound device is described. The ultrasound device may include a symmetric switch positioned between a pulser and an ultrasound transducer. The pulser may produce bipolar pulses. The symmetric switch may selectively isolate a receiver from the pulser and the ultrasound transducer during a transmit mode of the device, when the bipolar pulses are provided by the pulser to the ultrasound transducer for transmission, and may selectively permit the receiver to receive signals from the ultrasound transducer during a receive mode. The symmetric switch may be provided with a well switch to remove well capacitances in a signal path of the device.

Abstract: A face-down mountable chip-size package semiconductor device includes a semiconductor layer and N (N is an integer greater than or equal to three) vertical MOS transistors in the semiconductor layer. Each of the N vertical MOS transistors includes, on an upper surface of the semiconductor layer, a gate pad electrically connected to a gate electrode of the vertical MOS transistor and one or more source pads electrically connected to a source electrode of the vertical MOS transistor. The semiconductor layer includes a semiconductor substrate. The semiconductor substrate functions as a common drain region for the N vertical MOS transistors. For each of the N vertical MOS transistors, a surface area of the vertical MOS transistor in a plan view of the semiconductor layer increases with an increase in a maximum specified current of the vertical MOS transistor.

Abstract: According to one embodiment, electronic circuitry includes: a detection circuit including a diode, a cathode side of the diode being connected to one end of a semiconductor switching element and an anode side of the diode being connected to a first node; a comparator circuit configured to compare a voltage of the first node and a threshold voltage and generate a first signal; a first filter connected between the first node and another end of the semiconductor switching element and configured to suppress the voltage of the first node in a first period based on a control signal indicating turn-on of the semiconductor switching element; and a control circuit configured to determine at least one of the threshold voltage and the first period based on the first signal.

Abstract: A driving apparatus drives a load. An N-channel MOSFET is disposed downstream of the load on a current path of a current that flows via the load. A circuit resistor is connected between a direct current power source and the gate of the MOSFET. A first switch is connected between the gate and the source of the MOSFET. A microcomputer outputs a voltage relative to a potential at an output terminal of a second switch to a control terminal of the second switch. As a result, the second switch is turned ON or OFF. A switching circuit turns the first switch ON when the second switch is turned ON and turns the first switch OFF when the second switch is turned OFF.

Abstract: The present disclosure provides a voltage fluctuation detection circuit, which includes a voltage adjustment circuit and a comparator. The voltage adjustment circuit includes an adjustment circuit input terminal to receive the operating voltage, a first adjustment circuit output terminal to output a first voltage, and a second adjustment circuit output terminal to output a second voltage that is step-shaped, the second voltage differs from the first voltage by a bias voltage at the beginning of a preset clock period and falls within a first amplitude within the preset clock period, the magnitude of the bias voltage is related to the first voltage. The comparator includes: a first comparator input terminal to receive the first voltage, a second comparator input terminal to receive the second voltage, and a comparator output terminal to output a comparison result of the first voltage and the second voltage.

Abstract: An apparatus comprises an energy transfer device configured to supply power from a primary side of an isolation barrier through the isolation barrier to a secondary side of the of the isolation barrier for driving a gate of a switch for controlling output of the switch at the secondary side. The apparatus comprises a monitoring component. The monitoring component is configured to monitor an operating state of the switch. The monitoring component is configured to evaluate the operating state to determine whether a fault has occurred, perform a countermeasure, and/or provide a signal of the fault.

Abstract: A circuit to multiplex supply voltages may include a set of chains of transistors. Each chain of transistors may correspond to a voltage supply that is desired to be multiplexed and may include a set of transistors coupled in series. A first end terminal of each chain of transistors may be coupled to a corresponding voltage supply, and a second end terminal of each chain of transistors may be coupled to an output terminal of the circuit. A given supply voltage may be selected by turning on transistors in a chain of transistors that corresponds to the given supply voltage and turning off transistors in other chains of transistors.

Abstract: A gate driver for a panel, wherein the gate driver comprises at least an output channel unit, each of the output channel unit includes a first driving unit; a second driving unit; a first current limit circuit, coupled to the first driving unit, configured to control an output current according to an output voltage of the gate driver to limit an output current slew rate of the gate driver; and a second current limit circuit, coupled to the second driving unit, configured to control the output current according to the output voltage of the gate driver to limit the output current slew rate of the gate driver.

Abstract: A circuit comprising a NMOS having a gate coupled to a first node and a source terminal coupled to a second node, a second NMOS having a gate coupled to the second node and a source terminal coupled to an output node, a PMOS having a gate coupled to a third node, a drain terminal coupled to a fourth node, and a source terminal coupled to a fifth node, and a second PMOS having a gate coupled to the fourth node, a drain terminal coupled to the output node, and a source terminal coupled to the fifth node. The circuit also includes a voltage protection sub-circuit coupled to the first node, a fast turn-off sub-circuit coupled to the output node, a fast turn-on sub-circuit coupled to the third and fourth nodes, and a node initialization sub-circuit coupled to the first, second, and fourth nodes and the fast turn-on sub-circuit.

Abstract: Disclosed are a gate-on voltage generation circuit, a display panel driving device and a display device. The gate-on voltage generation circuit includes an on/off voltage output terminal, a power management integrated circuit and a voltage switching circuit. The power management integrated circuit includes a detection terminal connected to the on/off voltage output terminal, is configured for detecting a voltage output by the on/off voltage output terminal, and outputting first switch control signal or second switch control signal according to the voltage output from the on/off voltage output terminal. The voltage switching circuit includes a first input terminal for inputting a first voltage value and a second input terminal for inputting a second voltage value larger than the first voltage value. The voltage switching circuit outputs the first voltage value upon receiving the first switch control signal, and outputs the second voltage value upon receiving the second switch control signal.

Abstract: A communication device includes a first client group in a first region; a second client group in a second region different from the first region; a first data hub configured to generate first burst data and a first control packet based on first client data received from the first client group; a second data hub configured to generate second burst data and a second control packet based on second client data received from the second client group; and a data transfer unit connected to the first data hub and the second data hub via a control protocol, the data transfer unit configured to, store the first burst data in a target memory based on the first control packet, and store the second burst data in the target memory based on the second control packet.

Abstract: A microcontroller unit for controlling a three-level inverter including delayed fault protection is provided. The microcontroller unit includes an input port configured to receive a trip signal from a fault detection module, and a plurality of EPWM modules, each configured to control a power switch within the three-level inverter. The microcontroller unit includes an auxiliary EPWM module configured to receive the trip signal and produce a delayed trip signal, and processing circuitry coupled with the input port, the plurality of EPWM modules, and the auxiliary EPWM module. The processing circuitry is configured to, in response to activation of the trip signal, direct one of the plurality of EPWM modules to shut off its corresponding power switch upon activation of the trip signal, and to direct a different one of the plurality of EPWM modules to shut off its corresponding power switch upon activation of the delayed trip signal.

Abstract: A driver circuit may be configured to control a power switch. The driver circuit may comprise an output pin configured to deliver signals to a gate of the power switch to control an ON/OFF state of the power switch, and a comparator configured to compare a gate-to-source voltage of the power switch to a first threshold when the power switch is ON and to compare the gate-to-source voltage of the power switch to a second threshold when the power switch is OFF.

Abstract: Techniques are provided for writing a high-level state to a memory cell capable of storing three or more logic states. After a sense operation performed by a first sense component and a second sense component, a digit line may be isolated from the first sense component and the second sense component. The high-level state may be stored in the memory cell, then a second state may be stored in the memory cell, in which the second state may be a mid-level state or a low-level state. The second state may be stored based on a write-back component identifying that the second state was stored in the memory cell before the write back procedure.

Abstract: Provided are a semiconductor device and a sensor system capable of achieving improvement of noise resistance. Thus, an output circuit 106a in the semiconductor device includes: input terminals 207n, 207p; and an output terminal 208; an output amplifier 201 connecting the input terminals 207n, 207p to the output terminal 208; a feedback element 203 returning the output terminal 208 to the input terminal 207n; a switching transistor 204; and a resistance element 206. A drain of the switching transistor 204 is connected to the input terminal 207n. The resistance element 206 is provided between a back gate of the switching transistor 204 and a power source Vdd and has impedance of a predetermined value or more for suppressing noise of a predetermined frequency generated at the input terminal 207n.

Abstract: A drive circuit drives a power semiconductor element including a control terminal, a first main electrode, and a second main electrode. The drive circuit includes a first switching-off circuit and a second switching-off circuit each for turning off the power semiconductor element. The second switching-off circuit is lower in impedance than the first switching-off circuit. In a case where the power semiconductor element is turned off, only the first switching-off circuit operates when the power semiconductor element is in an unusual state, and the first switching-off circuit and the second switching-off circuit complementarily operate when the power semiconductor element is in a normal state.

Abstract: A switch comprising: a channel path comprising first and second MOS transistors with common source and gate terminals and drain terminals defining first and second terminals of the channel path; and control circuitry comprising: a third MOS transistor comprising: a gate coupled to the common source terminal; a source coupled to the common gate terminal by a resistor; and a drain coupled to a first reference terminal; a first current source coupled between the first reference terminal and the common gate terminal for providing a first current; a second current source coupled between the source terminal of the third MOS transistor and a second reference terminal for providing a second current greater than the first current; and a first switching arrangement configured to selectively enable and disable the first current source; and a second switching arrangement configured to selectively couple the common source terminal to the second reference terminal.

Abstract: Provided is a gate drive device, including: a gate drive unit for driving a gate of a switching element; a measurement unit for measuring a parameter that changes according to a current flowing through the switching element; and a switching unit for switching a changing speed of a gate voltage of the switching element by the gate driving unit after a first reference period from a start of turning off the switching element based on the parameter.

Abstract: Time folding power combining circuits convert a continuous wave into a pulsed wave of greater peak power.

Abstract: A switching circuit includes a first transmission terminal, a second transmission terminal, a third transmission terminal, and a variable impedance circuit. The first and the second transmission terminals coupled to a common node form a first transmission path. The third transmission terminal coupled to the common node forms a second transmission path with the first transmission terminal. The variable impedance circuit has a first terminal coupled between the common node and the third transmission terminal, and a second terminal coupled to a first reference potential terminal. When the first transmission path transmits a first signal, a first frequency bandwidth range provided by the variable impedance circuit is determined according to a first frequency of the first signal so that the variable impedance circuit provides low impedance in the first frequency bandwidth range, and the first frequency bandwidth range covers the first frequency.

Abstract: An apparatus is provided which comprises: a power gate device coupled to a gated power supply node and an ungated power supply node; and a control circuitry coupled to the power gate device, wherein the control circuitry is to turn on the power gate device by providing at least two bias voltages separated in time to gradually turn on the power gate device.

Abstract: A hybridization system for an electric device having two terminals and two states including a closed state allowing an electric current to circulate between the two terminals and an open state blocking the circulation of the electric current between the terminals, the device being suitable for an electric arc to be generated during the switching from the closed state to the open state. The hybridization system includes: two conductors connected to the two terminals of the electric device; a timer switch having two terminals connected to the two conductors and the timer switch being suitable for being in the open state by default and, after a first predetermined duration following the triggering of the electric arc, switching to the closed state for a second predetermined duration, and an electric power supply of the timer switch, connected to the two conductors in order to derive its power only from the electric energy provided by the electric arc.

Abstract: A semiconductor device having a power source terminal, a ground terminal, an input terminal, an output terminal and a status output terminal. The semiconductor device includes a power semiconductor switch connected between the power source terminal and the output terminal, a logic circuit connected to the power semiconductor switch, and a ground terminal opening detection circuit connected to the ground terminal and the status output terminal. The logic circuit is configured to generate, according to a signal inputted to the input terminal, an output logic signal for turning on or off the power semiconductor switch. The ground terminal opening detection circuit is configured to detect a state in which the ground terminal is opened, based on a rise in a potential of the ground terminal, and to output, via the status output terminal, a detection signal in response to the detection of the state.

Abstract: An apparatus includes a plurality of semiconductor switches. A first bus interconnects first terminals of the semiconductor switches in a first chain and provides a first impedance between the first terminals of switches of the first chain. A second bus interconnects second terminals of the semiconductor switches in a second chain and provides a second impedance greater that the first impedance between the second terminals of the switches of the second chain. The apparatus may be implemented as a laminated bus assembly including respective overlapping conductor plates, wherein the second bus includes a plate having subregions defined by features, such as slots or grooves, that provide the second impedance.

Abstract: A dual mode focal plane array having a readout integrated circuit (IC) is provided herein that is electrically switchable between a first mode (e.g., direction injection mode) and a second mode (e.g., buffered direction injection) based in part on a level of a detection current. The IC includes a switching network disposed between an operational amplifier and a switching element to transition the IC between the first and second mode responsive to a control signal. The control signal can include instructions to open or close the one or more switches of the switching network and thus transition the IC between the different modes.

Abstract: An apparatus can include: a drive circuit for a floating switch having first and second transistors coupled in series, where gate terminals of the first and second transistors are coupled together, and source terminals of the first and second transistors are coupled together; a control circuit coupled to the gate terminals of the first and second transistors, and being configured to control on and off states of the first and second transistors; and a clamp circuit configured to clamp gate-source voltages of the first and second transistors to maintain current switching states of the first and second transistors.