Abstract: A capacitive driving system (100) comprises: a supply device (10) comprising a power generator (13), capacitive transmission electrodes (11, 12) and preferably at least one inductor (16) connected in series between the power generator and at least one of said transmission electrodes; at least one load device (20) comprising two capacitive receiver electrodes (21, 22) and at least one load member (23) coupled to said receiver electrodes. For resonant energy transfer, the supply device and the load device have an energy transfer position in which a first one of said transmission electrodes together with a first one of said receiver electrodes defines a first transfer capacitor (31) while simultaneously a second one of said transmission electrodes together with a second one of said receiver electrodes defines a second transfer capacitor (32). At least one auxiliary capacitor (111; 112; 121; 122) is connected in series with inductor and load.

Abstract: A NAND EEPROM is disclosed which is capable of variously setting, for each chip, the voltage to be applied to the control gates of memory cells. The semiconductor chip includes a NAND memory cell array and a high-voltage generating circuit for generating data writing internal voltage VPP required when data is written on the memory cell array. Moreover, the semiconductor chip includes a set voltage selection circuit for arbitrarily setting the level of the voltage VPP generated by the high-voltage generating circuit for each chip and a multiplexer for extracting, to the outside of the chip, setting signal LTF which is a signal for enabling the level of the voltage VPP set arbitrarily.

Abstract: A NAND EEPROM is disclosed which is capable of variously setting, for each chip, the voltage to be applied to the control gates of memory cells. The semiconductor chip includes a NAND memory cell array and a high-voltage generating circuit for generating data writing internal voltage VPP required when data is written on the memory cell array. Moreover, the semiconductor chip includes a set voltage selection circuit for arbitrarily setting the level of the voltage VPP generated by the high-voltage generating circuit for each chip and a multiplexer for extracting, to the outside of the chip, setting signal LTF which is a signal for enabling the level of the voltage VPP set arbitrarily.