Abstract: A server system includes a common power bus, a power supply to provide direct current (DC) power through the common power bus, at least one node including a processor to receive the DC power through the common power bus, a transmitter capacitive coupled to the common power bus to transmit a power information signal from the power supply through the common power bus, and at least one receiver capacitive coupled to the common power bus to receive the power information signal transmitted by the transmitter and to provide the received power information signal to the at least one node. A plurality of buffers respectively coupled between the common power bus and each of the power supply and the at least one node provide path separation for high frequency and low frequency currents.

Abstract: A power converter which converts electrical power at an input voltage into electrical power at an output voltage is presented. It has a power stage with a high side switching element, a low side switching element and an inductor. The power converter has a voltage-to-current converter coupled to the power stage to convert a voltage indicative of a current flowing into the inductor into an indicator current. A peak current detector receives the indicator current to determine a pedestal component of the indicator current in a first time interval during which the high side switching element is open, and to generate a calibrated indicator current by subtracting the pedestal component from the indicator current. The peak current detector compares the calibrated indicator current with a threshold value for detecting a more precise peak current flowing into the inductor, taking into account the effects of temperature or circuit aging.

Abstract: A device may be for protection against overvoltages in a power supply line. The device may include a breakover diode, an avalanche diode coupled in series with the breakover diode, and a switch coupled in parallel with the breakover diode and the avalanche diode. The device may also include a circuit coupled across the avalanche diode and configured to control the switch.

Abstract: One embodiment is a uninterruptable power supply (UPS) system including a utility disconnect switch (UDS) coupled with an input line and an output line and structured to selectably connect and disconnect the input line and the output line. The UDS includes a semiconductor switching device connected between the input line and the output line, a surge arrester coupled in parallel with the semiconductor switching device, a dynamic voltage balancing device and a static voltage balancing device which are coupled in parallel with the semiconductor switching device.

Abstract: A power converter for operation from an AC power source may include a bridge rectifier having an input to receive an AC input voltage and an output to provide a DC voltage, the AC input voltage received from the AC power source through a fuse. An AC input overvoltage protection circuit may be configured to cause a short circuit across the AC input voltage in response to the DC voltage output from the bridge rectifier exceeding a predetermined voltage value for a predetermined period of time.

Abstract: A method and apparatus for detecting a missing phase in a 3-phase twelve-pulse autotransformer rectifier unit (ATRU) which, in use, receives a 3-phase input and delivers a nominal DC output on which a common-mode voltage is impressed. At least one of the frequency and amplitude of the common-mode voltage are monitored thereby to determine whether there is a missing phase in the input. The frequency and/or amplitude of the common-mode voltage may also be monitored thereby to determine whether there is a loss of input voltage.

Abstract: A server system includes a common power bus, a power supply to provide direct current (DC) power through the common power bus, at least one node including a processor to receive the DC power through the common power bus, a transmitter capacitive coupled to the common power bus to transmit a power information signal from the power supply through the common power bus, and at least one receiver capacitive coupled to the common power bus to receive the power information signal transmitted by the transmitter and to provide the received power information signal to the at least one node. A plurality of buffers respectively coupled between the common power bus and each of the power supply and the at least one node provide path separation for high frequency and low frequency currents.

Abstract: A rapid cutoff device includes a thyristor DC switch, a switch and a capacitor. An operation method includes: connecting the thyristor DC switch between a first DC circuit and a second DC circuit; serially connecting the switch and the capacitor which further parallel connects the first DC circuit; when the thyristor DC switch is conducted, supplying a DC current via the thyristor DC switch; when a drive signal of the thyristor DC switch stops, operating the switch to conduct the capacitor which is charged by the first DC circuit to rapidly lower a current of the thyristor DC switch approaching a zero value, thereby rapidly cutting of the thyristor DC switch.

Abstract: A circuit for controlling a thyristor (V1) into conducting state, the thyristor (V1) being in a rectifier, which rectifier is adapted to supply DC voltage to a DC voltage circuit. The circuit comprises a pulse transformer (T1), means for generating voltage pulses on the primary winding of the pulse transformer (T1), a trigger capacitor (C2) adapted to be charged from the voltage pulses in the secondary winding of the pulse transformer, a zener diode (V5) adapted to be triggered with the voltage of the trigger capacitor (C2) when the voltage of the trigger capacitor (C2) exceeds the breakdown voltage of the zener diode (V5), and an auxiliary thyristor (V3) adapted to be triggered with the current from the trigger capacitor (C2) flowing via the zener diode (V5), wherein the cathode of the auxiliary thyristor (V3) is connected to the gate of the thyristor (V1) for triggering the thyristor (V1) with the current from the trigger capacitor (C2) flowing via the auxiliary thyristor (V3).

Abstract: A method and a circuit for controlling a thyristor (V1) into conducting state, the thyristor (V1) being in a rectifier, which rectifier supplies DC voltage to a DC voltage circuit. The circuit comprising a trigger capacitor (C2) adapted to be charged from the voltage difference across the thyristor (V1) when the anode-to-cathode voltage of the thyristor is positive, a zener diode (V5) adapted to be triggered with the voltage of the trigger capacitor (C2), when the voltage of the trigger capacitor (C2) exceeds the breakdown voltage of the zener diode (V5), and an auxiliary thyristor (V3) adapted to be triggered with the current from the trigger capacitor (C2) flowing via the zener diode (V5), wherein the cathode of the auxiliary thyristor (V3) is connected to the gate of the thyristor (V1) for triggering the thyristor (V1) with the current from the trigger capacitor (C2) flowing via the auxiliary thyristor (V3) for using the thyristor (V1) in a diode mode.

Abstract: A method and a circuit for controlling at least one thyristor constitutive of a rectifying bridge with a filtered output, consisting of closing the thyristor when the voltage thereacross becomes greater than zero, and making the gate current of the thyristor disappear when the current therein exceeds its latching current.

Abstract: Systems consistent with this invention comprise a trigger circuit for triggering a silicon device having a control terminal, where the silicon device is subject to variations in the intrinsic control requirements. The trigger circuit comprises a source of direct current (DC) supply voltage, and a DC-to-DC current mode Buck converter for converting the supply voltage into an output DC current not subject to undesired variations due to variations in the supply voltage, the Buck converter supplying to the control terminal a minimum current to turn on the silicon device despite the variations in the intrinsic control requirements. The silicon device may comprise a silicon controlled rectifier (SCR) with a gate terminal, an anode terminal, and a cathode terminal, and wherein the control terminal is the gate terminal, and wherein the variations in the intrinsic control requirements are variations in the intrinsic gate-to-cathode control current and voltage requirements.

Abstract: A NAND EEPROM is disclosed which is capable of variously setting, for each chip, the voltage to be applied to the control gates of memory cells. The semiconductor chip includes a NAND memory cell array and a high-voltage generating circuit for generating data writing internal voltage VPP required when data is written on the memory cell array. Moreover, the semiconductor chip includes a set voltage selection circuit for arbitrarily setting the level of the voltage VPP generated by the high-voltage generating circuit for each chip and a multiplexer for extracting, to the outside of the chip, setting signal LTF which is a signal for enabling the level of the voltage VPP set arbitrarily.

Abstract: A NAND EEPROM is disclosed which is capable of variously setting, for each chip, the voltage to be applied to the control gates of memory cells. The semiconductor chip includes a NAND memory cell array and a high-voltage generating circuit for generating data writing internal voltage VPP required when data is written on the memory cell array. Moreover, the semiconductor chip includes a set voltage selection circuit for arbitrarily setting the level of the voltage VPP generated by the high-voltage generating circuit for each chip and a multiplexer for extracting, to the outside of the chip, setting signal LTF which is a signal for enabling the level of the voltage VPP set arbitrarily.

Abstract: An integrated circuit having an adjusting component and an adjustable thyristor allows an especially small chip surface to be used. The integrated circuit has a control unit, by means of which the adjusting component is irreversibly switched. The thyristor is designed as a planar component.