Abstract: A clock frequency limiting circuit is disclosed. The clock frequency limiting circuit allows a semiconductor device to be fabricated, packaged and tested before the maximum clock frequency is set. The maximum clock frequency is set by burning a bank of on-chip fuses. The clock frequency limiting circuit counts clock cycles of an applied clock signal for a predetermined amount of time. A comparator compares the maximum clock frequency in the fuse bank and the counted clock cycles. A violation "kill" signal is asserted if the counted clock cycles exceeds the set maximum clock frequency.

Abstract: A low cost and easily implemented apparatus and method for synchronizing serially connected clock circuits is ideally suited to audio applications. The circuit takes data from a bitstream clock source and from the local source and counts the number of pulses received from each. A desired clock count is calculated based as a multiple of the ratio of the bitstream clock source frequency to the local clock signal frequency. Based on the samples received from the bitstream clock relative to the local clock at a later point in time, samples are either repeated or dropped to correct any error in the bitstream signal.

Abstract: The command input of a high frequency switch is gated with the output of a power dissipation limiter. The limiter includes a counter that counts pulses of the command input. Between regularly occurring reset pulses, if a pulse count is obtained that indicates a burst period above a normal threshold level, the limiter generates a fault signal that inhibits further operation of the high frequency switch until the next regularly occurring reset pulse.

Abstract: A detector circuit for detecting abnormalities in the oscillation frequency of a clock signal, includes a counter and a comparator. The counter is supplied with a reference clock signal, and counts the number of pulses of the reference clock signal to output a signal indicative of the count value. In response to the clock signal, the counter clears the count value. The comparator compares the count value of the counter with a specified value stored in its register, and generates a detection signal indicating whether the frequency of the clock signal is within expected limits, based on the comparison result.

Abstract: A time window detection portion 3a outputs a time window detection pulse from a time window signal generated in a time window generating portion 2a and a zero-cross detection pulse detected in a zero-cross detection portion 1a. First and second phase storage portions 4a and 5a store output phase values of a phase counter 22 for different times as first and second phase values, respectively. A center phase computing portion 6a computes a first center phase value from the first and second phase values and a center phase storage portion 7a stores the first center phase value of the last time as a second center phase value. An approximation detection portion 8a determines whether the first and second center phase values are approximate or not and outputs an approximation detection pulse when they approximate.

Abstract: The invention discloses a method and an apparatus for implementing an L phase clock in conjuction with L counters, where L is an integer, to count at a frequency scalable by L.

Abstract: A speed governor for an integrated circuit which prevents the operation of the integrated circuit above a selected frequency. The speed governor generates a frequency reference and compares the frequency reference to the frequency of the external clock signal that clocks the integrated circuit. As a result of the comparison, if the frequency of the input clock signal is greater than the frequency reference then operation of the integrated circuit is disrupted.

Abstract: An adaptive threshold circuit for use with a magnetic type of sensor that has a pick-up coil. The pick-up coil has an alternating voltage induced therein when a slot or tooth formed in a wheel rotates past the sensor. The circuit produces a square wave pulse voltage during positive half-cycles of the voltage generated in the pick-up coil. The circuit includes a digital to analog converter the input of which is connected to a selectable pulse counter. The pulse counter has a decrement function that allows for the count to be varied so as to accommodate sudden wheel decelerations. According to one embodiment, the counter may down count to reduce the count number. In accordance with a second embodiment, the counter may shift out one bit to perform a divide-by-two operation on the count number.

Abstract: A rotary speed measurement device includes an oscillator including a resonant circuit with a coil which conducts a resonant current to develop a magnetic field therearound. A wheel is connected to rotate together with a rotating member and is provided along circumference with alternately arranged first and second marks which causes different magnetic effect on the magnetic field. The coil is disposed adjacent the wheel so as to sense the magnetic effect and provide a corresponding voltage Vs. An analyzer is provided to give a parameter Vsub based upon voltage Vs and to compare the parameter with a predetermined threshold V.sub.TH to give a pulse when the parameter exceeds the threshold as indicative of that the wheel rotates by an increment corresponding to an angular distance between the first mark and the adjacent second mark. The pulse is counted by a counter within a unit time to obtain a rotary speed of the wheel.

Abstract: A low cost and easily implemented apparatus and method for synchronizing serially connected clock circuits is ideally suited to audio applications. The circuit takes data from a bitstream clock source and from the local source and counts the number of pulses received from each. A desired clock count is calculated based as a multiple of the ratio of the bitstream clock source frequency to the local clock signal frequency. Based on the samples received from the bitstream clock relative to the local clock at a late point in time, samples are either repeated or dropped to correct any error in the bitstream signal.

Abstract: A phase angle difference between two alternating electrical signals is determined as a function of a ratio of a differential combination of two different numbers of pulse counts to an additive combination of the two different numbers of pulse counts, wherein the first of the two different numbers of pulse counts is obtained by counting a series of electric pulses generated by an electrical pulse generator in a time interval between an occurrence of zero value of the leading signal of the two alternating electrical signal and (i-1)th occurrence of zero value of the trailing signal of the two alternating electrical signals occurring after the occurrence of zero value of the leading signal, and the second of the two different numbers of pulse counts is obtained by counting the pulses in an time interval between an occurrence of zero value of the trailing signal and the (j)th occurrence of zero value of the leading signal occurring after the occurrence of zero value of the trailing signal, wherein (i) and (j) are

Abstract: A harmonic filter for active or adaptive noise attenuation control systems for obtaining the complex amplitude of a single harmonic component from a signal which contains one or more harmonic components.

Abstract: A frequency synthesizer provides a synthesized signal. The synthesizer includes an oscillator that supplies a fast clock signal to a divider programmable by a digital data. The most significant bits of the digital data are provided to the programmable divider, and the least significant bits are provided to an accumulator that cooperates with the programmable divider to increment by one unit its division rank when the accumulator overflows. The synthesizer further includes a generator for generating n increasing delay phases of the synthesized signal; a comparator for comparing the content of the accumulator with n ranges of possible increasing values; and circuits for selecting, as the synthesized signal, the phase whose rank corresponds to the rank of the range within which the content of the accumulator is comprised.

Abstract: The state machine with hysteresis provided in the invention includes a current state circuit and a next state control circuit. The current state circuit, in response to a clock signal and a control signal, generates a current state signal and a frequency detection signal. The current state signal has a plurality of bits. The next state control circuit, in response to the current state signal and the input signal, generates the control signal. A hysteresis is observed with regard to the relation of the frequency detection signal with respect to the frequency of the input signal.

Abstract: An object of the present invention is enhancing a capability of integration of a frequency finding circuit for finding a frequency of an input signal. A signal sampling circuit (21), sampling the input signal, utilizes a sampling signal (G) to convert the input signal into a sampled input signal (S) and inputs it to the frequency finding circuit. A resultant signal (K) from the frequency detecting circuit represents a specific frequency component contained in the input signal and is compared with a specified threshold value by a voltage comparator (25). Although a deciding signal (P) is produced as a result of the comparing, it contains unrequired components other than a sampling period. In order to eliminate the needless components, after sampling the deciding signal (P) in accordance with the sampling signal (G) again, an output circuit (50) latches it. The output circuit (50) includes a latch circuit (26) operating in accordance with the sampling signal G.

Abstract: Apparatus for determining the number of cycles occurring in a frequency modulated signal during a sample period, including not only the number of full cycles but any portion of a cycle, by determining the number of whole cycles and adding to this a value obtained by counting the number of high frequency clock cycles occurring between the time of the last rising edge of a full cycle and the end of the sample period, and the number of high frequency clock cycles occurring from the last rising edge prior to the start of the sample period and the start of the sample period and the number of high frequency clock cycles in a whole cycle.