Abstract: A time-differential analog comparator is disclosed. An example apparatus according to aspects of the present invention includes a source of a variable frequency signal having a frequency responsive to an analog input. A counting circuit is coupled to count cycles of the variable frequency signal. The counting circuit is coupled to count in a first direction for a first time interval and is coupled to count in a second direction opposite to the first direction for a second time interval that occurs after an end of the first time interval. An evaluation circuit is coupled to the counting circuit. The evaluation circuit is responsive to the count of the cycles of the variable frequency signal after an end of the second time interval.

Abstract: A frequency coincidence detection circuit for detecting frequency edges for each of a plurality of periodic digital signals. The circuit generates count indicators for each of the periodic digital signals and compares each of the count indicators to a programmable sensitivity input to determine a coincidence window for the corresponding one of each of the periodic digital signals. The circuit determines a signal coincidence of the coincidence windows. In another embodiment, a frequency coincidence detection method is provided. The method detects frequency edges for each of a plurality of periodic digital signals, generates count indicators for each of the periodic digital signals and compares each of the count indicators to a programmable sensitivity input to determine a coincidence window for the corresponding one of each of the periodic digital signals. The method determines a signal coincidence of the coincidence windows.

Abstract: A frequency sensor includes at least one a resistor element and a capacitor. A frequency is detected according to a charging/discharging time to/from the capacitor, thereby realizing a frequency sensor with reduced power consumption and reduced circuit scale. Further, plural resistors and plural capacitors can be provided, along with switches connected to the respective resistors and capacitors. Additionally, a time constant can be adjusted after production, whereby variations in production can be reduced. Furthermore, a self-diagnosis circuit can be included for determining whether the frequency sensor itself operates normally or not. Thus, a highly-reliable frequency sensor can be realized.

Abstract: The invention concerns counting circuitry for providing a corrected count value based on the number of rising and falling edges of an input signal occurring during a reference time period, the counting circuitry comprising a counter (22) arranged to provide a first count value based on one of the number of said rising edges of said input signal occurring during said reference time period, and the number of said falling edges of said input signal occurring during said reference time period; characterized in that said counting circuitry further comprises adjustment circuitry (24-26) arranged to generate a corrected count value by determining the state of said input signal at the start time (70) and end time (72) of said reference time period, and adjusting said first count value if the state of said input signal at the start of said reference time period is different from the state of said input signal at the end of said reference time period.

Abstract: A circuit and method are provided herein for monitoring the status of a clock signal. In general, the method may include supplying a pair of clock signals to a clock monitor circuit, which is configured for monitoring a status of one clock signal relative to the other. The status indicates whether the frequency of the one clock signal is faster, slower or substantially equal to the frequency of the other clock signal. Once determined, the status may be stored as a bit pattern within a status register, which is operatively coupled to the clock monitor circuit. This enables the status to be read by detecting a logic state of one or more bits within the status register.

Abstract: A system and a method are presented for detecting the presence of at least one clock signal of a defined clock frequency applied to at least one input port of an integrated circuit system, wherein the a first number M of clock pulses related to the at least one clock signal within a predefined cycle period is counted and the counted first number M of clock pulses is compared with a reference number. Depending on the result of the comparison the presence of the at least one clock signal is detected or not.

Abstract: A clock detection and selection circuit (100) can include a first counter (102-0) that generates a first count value CNT1 according to a first clock signal CLK1 and a second counter (102-1) that generates a second count value CNT2 according to a second clock signal CLK2. First separation-detect logic (102-0) and second separation-detect logic (102-1) determine if a pre-specified difference exists between a first count value (CNT1/CNT1?) and second count value (CNT2/CNT2?). According to such determinations, separation information (INF—1 and INF—2) can be generated indicating which clock signal (CLK1 or CLK2) is faster. Selection logic (106) can select a faster of the clock signals (CLK1 or CLK2) if the separation information values confirm one another.

Abstract: Systems and methods for controlling clock rates of circuits are provided. The systems and methods, collectively referred to as clock rate control, generate a clock rate control parameter from data of one or more fuses. The clock rate control detects any overclocked signal of received clock signals by determining a clock signal is running faster than a threshold represented by the clock rate control parameter. The clock rate control controls a circuit clock rate using a selected signal of the clock signals that is not an overclocked signal.

Abstract: A device such as a programmable logic device (“PLD”) includes circuitry for detecting the PPM frequency difference between two input clock signals. For example, this circuitry may accept a user-programmable PPM threshold value and output a signal when this threshold value is met.

Abstract: A frequency monitor circuit (FMC) that is part of an integrated circuit chip for monitoring the frequency of one or more clocks present on the chip is disclosed. The FMC includes a reference window generator, operative to output a reference window signal of a given duration, and a clock counter, operative to count all pulses, in any one of the clocks, that occur within the duration of the reference window and to output a corresponding pulse count. The FMC further includes two or more comparators, each operative to compare the pulse count with a respective given threshold value and to output a corresponding indication of frequency deviation. In one configuration, in which the clock is generated on the chip by a frequency multiplier, the reference window generator and the clock counter are shared between the frequency monitor circuit and the frequency multiplier.

Abstract: A device and method are disclosed, whereby the normally complicated and difficult frequency determination is achieved by simply arranged and executed measures, namely by means of larger, smaller and/or equal comparisons and a counting of certain events. The invention further relates to arrangements whereby the noise signal level, or the influence thereof on the verification to be carried out is reduced.

Abstract: Systems and methods for monitoring frequencies of periodic electrical signals are disclosed. According to one technique, a first and second counters are respectively clocked by a first periodic electrical signal to be monitored and a second periodic electrical, and a threshold detector resets one of the counters when a count of the other counter crosses a reset threshold and determines whether a frequency error has occurred based on whether a count of the one of the counters crosses an alarm threshold. Another technique according to an embodiment of the invention also involves clocking counters with respective periodic electrical signals, although error detection is based on whether the counts of the counters cross respective associated thresholds in other than a particular sequence with respect to each other.

Abstract: A system and method that can be utilized to implement voltage adjustment (e.g., for an integrated circuit). In one embodiment, the system comprises a frequency generator that provides a clock signal having a frequency that varies based on an operating voltage. The system also includes a controller that provides a control signal to adjust the operating voltage based on adjustments to the frequency of the clock signal.

Abstract: A method which provides a very simple way of forming a control signal if the frequencies differ too greatly from one another between a useful signal and a reference signal. A control signal is produced which indicates that the frequency error between the frequencies of a useful signal and the frequency of a reference signal exceeds a prescribed error limit value, where the useful signal and the reference signal are used to produce a pulsed signal whose pulse length is proportional to the frequency difference between the useful signal and the reference signal. The pulse length is then compared with a prescribed maximum pulse length, and the control signal is produced if the pulse length exceeds the prescribed maximum pulse length.

Abstract: A technique of processing an input signal having an input signal phase is disclosed. The technique includes determining a number of transitions of the input signal within a period having a start and an end. The technique includes determining a relative beginning phase of the input signal at the start of the period, which includes generating a first reference signal having a first reference signal frequency and a first reference signal phase synchronized with the start of the period, and detecting a first time interval required for the input signal phase to have a first specified relationship to the first reference signal phase. The technique includes similarly determining a relative ending phase of the input signal at the end of the period. The technique includes determining an input signal temporal characteristic from the number of transitions and the relative beginning phase and the relative ending phase.

Abstract: A method and apparatus provide for monitoring radio frequency signals and, in conjunction with the monitoring, determining frequency of a received dominant radio frequency signal. Zero amplitude transitions of the signal are counted in primary and secondary sampling periods to determine frequency and frequency stability. The method and apparatus can be used to tune to radio frequency signals having frequencies in a list of frequencies to be monitored and detecting signals in the radio frequency spectrum on other frequencies. The monitoring and scanning may occur simultaneously, sequentially, or in any order or sequence. The frequencies of dominant signals received are determined and added to the list for monitoring. The receiver may be tuned to a frequency determined immediately upon determination of the frequency determined, after storage of the frequency determined, only after a signal on the currently monitored frequency terminates, or upon other conditions.

Abstract: A detection circuit which can reliably detect an out-of-synchronism state of a clock signal with respect to data even if jitter is present in a data signal. A delayed clock signal obtained by delaying a clock signal by 90° through a delay circuit is input to a data input (D) of a flip flop, and the clock signal is read in at the point of change of the data. A logic product of the inverted output of the flip flop and the data signal is obtained by an AND circuit. Then, a logic product output is counted by a counter circuit, and an out-of-synchronism state of the clock with respect to the data is detected based on the output of the counter circuit.

Abstract: A method of adjusting a control signal that includes generating a control signal at an unknown frequency and automatically adjusting the unknown frequency of the control signal based on the unknown frequency.

Abstract: A frequency comparator circuit is configured to compare whether the frequency of two input signals are within a tolerance of each other. The frequency comparator circuit includes two counter circuits, an AND gate, and a frequency detector circuit that is configured to provide two reset signals. The two counter circuits are arranged to be clocked by a respective one of the two input signals, and further arranged to be reset by a respective one of the two reset signals. Further, the AND gate is arranged to perform an AND function on the overflow outputs of the first and second counter circuits to provide an status signal. If the status signal is high, the difference in frequency between the two input signals is less than the tolerance. If the status signal is low, the difference in frequency between the two input signals exceeds the tolerance.

Abstract: A circuit and method is disclosed for self trimming in frequency acquisition and clock recovery. The circuit can be simplified as having a VCO in communication with three loops including a trimming loop, a frequency loop and a phase loop. The trimming loop includes a ramp generator for supplying a steady increase of bias current to the VCO causing the frequency of the VCO to increase. At each step, the averaged output of the frequency detector is measured by a comparator. A decision circuit included in the trimming loop registers the output of the comparator in digital format. The trimming loop continues until the decision circuit detects a long string of positives followed by a long string of negatives and at this point, the trimming loop is shut off and the frequency loop is in operation. The frequency loop drives the VCO frequency to within a small difference of the incoming data frequency. The phase loop cleans up the data and locks the phase.

Abstract: A frequency change measuring device includes frequency divider for frequency dividing a measuring signal to produce frequency-divided signals, first counter for counting the frequency-divides signals to calculate frequency-division numbers, frequency division numbers transmitter for transmitting the frequency division numbers in synchronism with the frequency-divided signals, frequency division numbers receiver for receiving the frequency division numbers transmitted from the frequency division numbers transmitter, second counter for counting outputs of a reference clock generator synchronized with a timekeeping device that keeps the standard time, latch unit for latching a count of frequency outputs of the reference clock generator synchronous for generating reference clocks on the basis of signals synchronous with the frequency division numbers, and operations unit for determining a frequency change on the basis of the count and the frequency division numbers.

Abstract: A system for improving the duty cycle output of a vehicle speed sensor circuit is disclosed. The vehicle speed sensor circuit can be configured, for example as a binary counter, to provide a particular number of pulses per distance of vehicle travel. An output of the vehicle speed sensor circuit is generally divided by placing varying values on particular load pins of an associated counter circuit, thereby providing a substantially improved duty cycle output from the vehicle speed sensor circuit, which is independent of an associated sensor duty cycle. The output of the vehicle speed sensor circuit can be divided utilizing a toggle flip-flop circuit integrated with the vehicle speed sensor circuit. The toggle flip-flop can be configured as an edge-triggered toggle flip-flop. The vehicle speed sensor can be utilized to sense rotating members present in a vehicle. The vehicle speed sensor thus provides a digital pulse output for every tooth that passes in front of the vehicle speed sensor.

Abstract: An apparatus for detecting a difference between frequencies includes a beat waveform generator which generates a beat waveform signal having a frequency which is equal to a difference between frequencies of a reference clock signal and a target clock signal. A frequency divider divides the reference clock signal by N, where N is an integer, to generate a divided reference-clock signal. A frequency comparator compares frequencies of the beat waveform signal and the divided reference-clock signal, and generates a step out alarm signal which is a binary signal depending upon a polarity of a difference between the frequencies of the beat waveform signal and the divided reference-clock signal.

Abstract: A latch for detecting a state transition of an input signal and generating a self-clearing reset signal on an output. The latch comprises: 1) a transfer gate for passing the input signal to a first node when the input transfer gate is enabled; 2) a transition detector for detecting a transition of the first node from a first to a second state, wherein the transition detector, in response to the transition, disables the transfer gate and enables the reset signal; and 3) a feedback loop circuit for detecting enabling of the reset signal. The feedback loop circuit, in response to the enabling, changes the first node from the second state back to the first state. The transition detector, in response to the changing of the first node back to the first state, disables the reset signal.

Abstract: In general, a built-in self test circuit and method is provided that measures error in any periodic signal and, particularly, a Phase Lock Loop (PLL) output clock signal. The circuit includes a short-pulse generator that generates a short-pulse signal having the same frequency as the phase lock loop output clock signal. Accordingly, a delay chain, including a plurality of delay elements, generates N delayed pulses from the short-pulse signal. A hit-pulse generator receives the N delayed pulses and compares each delayed pulse with the phase lock loop output clock signal 2K times, such that the hit-pulse generator also generates a hit-pulse when both signals are high. It also generates a hit count which represents the number of hit-pulses. After each of the N delayed pulses are compared with the clock signal 2k times, a comparator compares a predetermined set of threshold values corresponding to the cumulative distribution of jitter for a PLL clock signal with the hit count.

Abstract: A method and system for determining the frequency of a pulse input signal is disclosed. A pulse count and a timer count can be captured at a start and end of a predetermined measurement interval to thereby obtain a start pulse count and an end pulse count and a start pulse time and an end pulse time thereof. A pulse frequency can then be determined, the pulse frequency comprises the end pulse count minus the start pulse count divided by the end pulse time minus the start pulse time, thereby permitting a highly accurate frequency measurement of the pulse input signal to be obtained over a wide frequency range. The pulse count and the timer count can be captured respectively utilizing a pulse counter and a timer. The pulse frequency generally comprises a frequency of an input pulse signal, such that the pulse frequency is determined based on an accuracy dependent only upon a reference timer clock.

Abstract: A method and system for determining the frequency of a pulse input signal is disclosed. A pulse count and a timer count can be captured at a start and end of a predetermined measurement interval to thereby obtain a start pulse count and an end pulse count and a start pulse time and an end pulse time thereof. A pulse frequency can then be determined, the pulse frequency comprises the end pulse count minus the start pulse count divided by the end pulse time minus the start pulse time, thereby permitting a highly accurate frequency measurement of the pulse input signal to be obtained over a wide frequency range. The pulse count and the timer count can be captured respectively utilizing a pulse counter and a timer. The pulse frequency generally comprises a frequency of an input pulse signal, such that the pulse frequency is determined based on an accuracy dependent only upon a reference timer clock.

Abstract: A method and circuit for comparing the frequencies of two clocks (clock—1 and clock—2), without taking into account their phase, is disclosed. Each clock is associated to a circular counter (100-1 and 100-2) which are initialized to different values, and the contents of the circular counters are compared. When the frequencies of the two clocks (clock—1 and clock—2) are equal, both counters (100-1 and 100-2) are incremented at a common frequency and thus, due to the initialization conditions, the contents of both counters can never be equal. Conversely, when the frequencies of the two clocks are different, the counters (100-1 and 100-2) are not increased at a common frequency and thus, after several clock pulses, the contents of the counters are equal, indicating different clock frequencies. In a preferred embodiment, the circular counters (100-1 and 100-2) are 2-bit circular counters.

Abstract: The PLL (Phase Lock Loop) circuit generates a sampling clock for sampling an analog image signal and a second clock having a frequency equal to that of the sampling clock and a phase different from that of the sampling clock based on the horizontal synchronizing signal supplied together with the analog image signal. The measuring circuit counts the number of pulses of the sampling clock and the number of pulses of the second clock for a predetermined time period. The MPU (Micro Processing Unit) determines whether or not the numbers of pulses of the sampling clock and second clock have been counted correctly based on the number of pulses of the sampling clock and the number of pulses of the second clock. Then, the MPU adjusts the frequency and phase of the sampling clock, when it is determined that the numbers have been counted correctly.

Abstract: A method and circuit for comparing the frequencies of two clocks (clock—1and clock—2), without taking into account their phase, is disclosed. Each clock is associated to a circular counter (100-1 and 100-2) which are initialized to different values, and the contents of the circular counters are compared. When the frequencies of the two clocks (clock—1 and clock—2) are equal, both counters (100-1 and 100-2) are incremented at a common frequency and thus, due to the initialization conditions, the contents of both counters can never be equal. Conversely, when the frequencies of the two clocks are different, the counters (100-1 and 100-2) are not increased at a common frequency and thus, after several clock pulses, the contents of the counters are equal, indicating different clock frequencies. In a preferred embodiment, the circular counters (100-1 and 100-2) are 2-bit circular counters.

Abstract: In a frequency detection method for adjusting a clock signal frequency to the data rate of a received data signal, the clock signal which is predivided by a factor of 4. The predivided clock signal and the received data signal are each frequency-divided by the same division factor. The frequencies of the two frequency-divided signals are then determined by counting processes and are compared by a subtractor. The frequency difference that is determined is then converted into an analog output signal for controlling the clock signal frequency. This method can be applied in the transmission of data.

Abstract: An improved frequency detector circuit and method is disclosed for frequency acquisition. The frequency detector is particularly useful as part of a frequency loop in a standard two loop clock and data recovery (CDR) circuit because, for among other reasons, the frequency detector is not limited in frequency range. Typically a CDR circuit includes a phase loop and a frequency loop. The frequency loop includes an improved frequency detector which can be simplified as having two parts; a frequency too low detector (FTLD) and a dynamic leakage circuit (DLC). The FTLD monitors the incoming NRZ data and the VCO frequency looking for a rising edge of the VCO between two edges of the data. In one embodiment, the FTLD includes one or more flip-flops to detect the rise and fall of the data and to count the data and clock edges. The DLC is essentially a too high detector and includes a double edge sampler. The DLC monitors the beat frequency between the incoming NRZ data and the VCO.

Abstract: In a frequency detection method for adjusting a clock signal frequency to the data rate of a received data signal, the clock signal which is predivided by a factor of 4. The predivided clock signal and the received data signal are each frequency-divided by the same division factor. The frequencies of the two frequency-divided signals are then determined counting processes and are compared by a subtractor. The frequency difference that is determined is then converted into an analog output signal for controlling the clock signal frequency. This method can be applied in the transmission of data.

Abstract: A delay-locked loop (DLL), including frequency detection logic and a phase detector, is described having an operating range as wide as a conventional charge pump phase locked loop. The frequency detector logic counts the number of rising edges of the multi-phase clocks generated from a reference clock during one period of the reference clock. A loop filter is used to adjust the frequency of each multi-phase clock until frequency lock is obtained by comparing the number of rising edges. After frequency lock, phase detection logic is used to finely tune out the remaining phase error.

Abstract: A frequency comparator includes a circuit comparing, independently of a phase relationship between first and second clocks, frequencies of the first and second clocks and outputting first and second detection signals when the first clock has frequencies higher and lower than those of the second clock, respectively. The first and second detection signals are output for respective times based on a difference between the frequencies of the first and second clocks.

Abstract: A digital phase detector utilizes a digital compartor and a plurality of delay elements. The comparator compares two signals and generates an output signal with a duration corresponding to the time delay between the arrival times of two signals. The output signal propagates through the plurality of delay elements. The number of delay elements that cover the duration of the output signal determine a time value for the duration of the output signal.

Abstract: A circuit for detecting the disappearing of a periodic input signal, the circuit including a frequency divider receiving the input signal, the frequency divider having two complementary outputs combined with a same reference signal of same frequency as the input signal by means of two respective similar logic gates, the output of a first one of the logic gates being connected to increment a first counter and to reset a second counter similar to the first one, and the output of the second logic gate being connected to increment the second counter and to reset the first counter, and a logic circuit generating a disappearing detection signal when any one of the two counters reaches a predetermined value.

Abstract: In a clock control circuit there are provided a counter for dividing a reference clock signal so as to generate a plurality of divided clock signals and selectors for selectively outputting one of the plurality of divided clock signals and the reference clock signal as an operation clock signal relative to a CPU or as an operation clock signal relative to a peripheral circuit.

Abstract: A counting apparatus having excellent fail-safe characteristics can be used in a rotation-stopped detection apparatus. As a first feature, timing of a high-frequency signal P.sub.2 is carried out by a counter 1 after completion of a counting of pulse signals P.sub.1. When the frequency of the timing output for the high-frequency signal is a predetermined value, a judgment signal, indicating that the counting is normal, is generated by a frequency discriminating circuit 30. As a second feature, a counter 100 is preset using a preset signal. Then, after verifying by an output from a self hold circuit 102 that the counter 100 has been reset, a counting output is generated from a self hold circuit 104. As a third feature, the counting apparatus is used as timer circuits 203, 300, 400, and the generation frequency of a rotation detection pulse signal I.sub.P based on a sensor signal, is obtained to thereby detect a rotation-stopped condition of a rotating body.

Abstract: An apparatus for monitoring a reference clock signal having a clock pulse train comprises a detecting block for counting pluses of a count clock signal to produce a count value and generate a count failure signal when the count value reaches a predetermined value, wherein the frequency of the count clock signal is larger than that of the reference clock signal; and a controlling block for generating a clear signal at every clock pulse of the reference clock signal to cleat the detecting block when the clear signal is inputted thereto.

Abstract: A circuit for detecting a predefined reoccurring phase point an periodic electrical signal has an input stage which rectifies the signal into first and second complementary signals. A Schmitt circuit has an input connected to the rectifier stage and produces a first intermediate signal in response to the voltage of the first complementary signal. A complementary Schmitt circuit is connected to the rectifier stage and produces a second intermediate signal in response to the voltage of the second complementary signal. An output stage that is connected to the Schmitt circuit and the complementary Schmitt circuit, responds to the first and second intermediate signals by producing an indication of each occurrence of the reoccurring phase point in the periodic electrical signal.

Abstract: A frequency gain display apparatus for an L/C band frequency up unit which is capable of generating a pulse for adjusting the gain of an L/C band frequency up unit used in a satellite system and a pulse for selecting a band width of a SAW (surface acoustic wave) filter and is capable of displaying a gain step of the same.

Abstract: A counter circuit and a frame control circuit receive a reference clock signal and one or more external clock signals. The counter circuit in combination with the frame control circuit measures the frequency of the external clock signal using either a high frequency measurement mode or a low frequency measurement mode. In the high frequency mode, the number of clocks in the external clock signal are counted for a known time period determined by a high frequency reference clock signal. In the low frequency mode, reference clocks are counted by the counter circuit for a second time period determined by the external clock signal frequency. The measurement circuit automatically switches between the high and low frequency measurement modes according to a minimum clock count value. If the number of external clocks counted during the frequency measurement mode is less than the minimum clock count value, the measurement circuit switches to the alternate frequency measurement mode.

Abstract: A method for improving the precision of a signal generator utilizing counters. The difference between an external standard signal frequency and an internal standard frequency is measured by digital counters. The signal of this internal standard frequency signal source is counted by a first counter and the frequency of an external standard frequency signal source is counted by a second counter. A calculating and control part determines the accurate frequency of internal standard frequency signal source from count values of both counters. The measurement frequency signal source generates a signal with the desired frequency. The circuit is digitally implemented.

Abstract: A circuit for measuring the frequency of an electrical signal includes a detector that senses a reoccurring phase point the electrical signal. A divide-by-M counter is connected to the detector and produces a control signal upon every Mth occurrence of the indication, where M is a positive number greater than one. A clock signal generator is provided. An output counter counts cycles of the clock signal between occurrences of the control signal and divides the count by M to produce an output count that corresponds to the frequency of the electrical signal.

Abstract: One or more detection circuits are provided for determining the operation of a motherboard prior to placing a microprocessor upon that motherboard. The detection circuit determines a particular way in which the motherboard is configured by ascertaining, for example, a power supply voltage and a clocking frequency output from the motherboard. A probe is used, in combination with the detector circuits, to determine motherboard operation at a socket to which, for example, a microprocessor can be coupled. Jumpers or switches upon the motherboard can be readily found by activating a switch and looking for a response upon the detection circuit output. If a response is not found, the jumper or switch is returned, and another jumper or switch is activated. Once the jumper or switch used for changing system clock speed and/or processor voltage is located, then a display is read as to those parameters to ensure the parameters match the processor specification.

Abstract: In a timer apparatus, the clock controlling circuit thereof outputs a clock signal during a period in which an input signal is significant. The counter thereof counts the number of pulses of the clock signal to generate a count-up signal when the value of count reaches a prescribed value. The initialization circuit thereof outputs an initialization signal when the input is not significant. The clock controlling circuit stops the output of the clock signal when the count-up signal is generated. Thereby, it is prevented to misjudge the detection of an effective pulse width to achieve the effective pulse width though the pulse width of the pulse does not actually reach the effective pulse width actually.

Abstract: An oscillator that has a substantially-constant voltage source configured such that it does not require the voltage source to be tuned to a particular voltage to oscillate a particular frequency. The oscillator has greater precision and reliability since the inputs of the comparator are periodically switched to reduce the effects of comparator bias and to equalize the voltage stresses on the inputs of the comparator. Greater precision is also achieved through the use of a discrete resistor and a discrete capacitor to define the frequency of the oscillator. The present invention provides an oscillator and method to generate a periodic signal that is tamperproof because the circuitry that defines the period is either integrated onto the integrated circuit or contained within the package containing the integrated circuit.

Abstract: A phase frequency detection circuit and method in a phase lock loop circuit uses delay circuits to limit the period of expression of up and down signals which adjust the output frequency of a voltage controlled oscillator. The pulse frequency detection circuit includes cross-linked latches to drive logic gates which produce output signals for adjusting the output frequency of a voltage controlled oscillator and delay circuitry connected to the outputs of particular logic gates for selective nullification of up and down control signals to a voltage controlled oscillator.

Abstract: A power control circuit of a monitor capable of being applied to all kinds of monitors is constructed to supply a control signal in accordance with the state of the monitor among On, Stand-by, Suspend and Off states by considering the input of vertical and horizontal sync signals after checking the current input state of the horizontal and vertical sync signals of the monitor, thereby facilitating the embodiment of the circuit that provides the control signal according to the current power supply state of the monitor by an ASIC.