Having Feedback Patents (Class 327/54)
  • Patent number: 10166876
    Abstract: A vehicle accumulator connected to a charging device is charged by controlling a configurable charge program executed by a control unit of the charge device. The configurable charge program is obtained from a charge program memory, so that the vehicle accumulator can be charged in an optimal manner with an individual charging characteristic.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: January 1, 2019
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventors: Rainer Falk, Steffen Fries
  • Patent number: 10122392
    Abstract: Systems, apparatuses, and methods for implementing a negative resistance circuit for bandwidth extension are disclosed. Within a feedback path of a differential signal path, capacitors are placed on the inputs and outputs of a fully differential amplifier connecting to the differential signal path. In one embodiment, a circuit includes a fully differential amplifier and four capacitors. A first capacitor is coupled between a first signal path and a non-inverting input terminal of the amplifier and a second capacitor is coupled between the first signal path and a non-inverting output terminal of the amplifier. A third capacitor is coupled between a second signal path and an inverting input terminal of the amplifier and a fourth capacitor is coupled between the second signal path and an inverting output terminal of the amplifier. The first and second signal paths carry a differential signal.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: November 6, 2018
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Milam Paraschou, Gerald R. Talbot, Dean E. Gonzales
  • Patent number: 9847116
    Abstract: A cell bias control circuit maximizes the performance of devices in the read/write path of memory cells (magnetic tunnel junction device+transistor) without exceeding leakage current or reliability limits by automatically adjusting multiple control inputs of the read/write path at the memory array according to predefined profiles over supply voltage, temperature, and process corner variations by applying any specific reference parameter profiles to the memory array.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: December 19, 2017
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Dietmar Gogl, Syed M. Alam, Thomas Andre
  • Patent number: 9679654
    Abstract: Aspects of a continuous-time memory cell circuit are described. In various embodiments, the memory cell circuit may comprise a memory cell, a current source coupled to the memory cell, and circuitry for programming the memory cell at an adaptive rate, based on a target voltage for programming, using a feedback loop between a gate terminal of the memory cell and a reference control input. Based on the circuitry for programming, the memory cell may be programmed according to various voltage and/or current references, by linear injection and/or tunneling mechanisms. According to various aspects, the circuitry for programming drives a memory cell to converge to a voltage target for programming within a short period of time and to a suitable level of accuracy.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: June 13, 2017
    Assignee: WEST VIRGINIA UNIVERSITY
    Inventors: Brandon David Rumberg, David W. Graham
  • Patent number: 9473710
    Abstract: A video signal termination detection system includes an input configured to connect to a video driver that produces a video signal, an output configured to connect to a video receiver that operates with a signal type, a detection circuit connected between the input and the output and configured to detect the signal type of the video receiver and to output a detection signal, and a conversion circuit configured to receive the video signal from the video driver and to convert the video signal to the signal type if the video signal is different than the signal type.
    Type: Grant
    Filed: February 4, 2014
    Date of Patent: October 18, 2016
    Assignee: Rosemount Aerospace Inc.
    Inventors: John C. Bartholomew, Nathan D. Evans, James W. Swenson
  • Publication number: 20150138411
    Abstract: An object of the present invention is to provide a comparator which has an input voltage range larger than the case where a conventional offset cancel technique is used, while reducing an offset voltage. A comparator circuit includes: a comparator having an inverting input terminal, a non-inverting input terminal and an output terminal; a first switch having one terminal connected to the inverting input terminal and having the other terminal connected to the output terminal; a first capacitor which has one end connected with the inverting input terminal; a first signal input terminal which is another end of the first capacitor; and a second signal input terminal which selectively inputs either one of a fixed voltage and a comparing signal into the non-inverting input terminal.
    Type: Application
    Filed: October 17, 2014
    Publication date: May 21, 2015
    Inventors: Kohichi Nakamura, Hideo Kobayashi, Hiroki Hiyama, Kazuo Yamazaki
  • Patent number: 9035680
    Abstract: Embodiments of the present invention provide a comparator and an analog-to-digital converter. A sampling module, a pre-amplifying module, and a coupling module in the comparator obtain a third differential voltage signal according to a positive input signal and a negative reference signal, and obtain a fourth differential voltage signal according to a negative input signal and a positive reference signal. A latch that is in the comparator and formed by a first P-type field effect transistor, a second P-type field effect transistor, a third field effect transistor, a fourth field effect transistor, a first switch, and a second switch is directly cross-coupled through gates, and directly collects the third differential voltage signal and the fourth differential voltage signal to the gates, so as to drive the latch to start positive feedback.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: May 19, 2015
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Jinda Yang, Liren Zhou, Jun Xiong
  • Patent number: 8988959
    Abstract: A circuit and method for dynamically changing trip point voltage in a sensing inverter circuit. In one embodiment, the sensing inverter circuit includes: (1) a base inverter circuit couplable to logic-high and logic-low voltage sources at respective inputs thereof and configured to transition an output thereof from a previous logic-level voltage to a present logic-level voltage based on a logic value of an input voltage received by the base inverter circuit, and (2) a feedback circuit associated with the base inverter circuit and configured to employ the previous logic-level voltage to decouple one of the logic-high and logic-low voltage sources from one of the inputs and thereby shift a trip voltage of the base inverter circuit toward the input voltage.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: March 24, 2015
    Assignee: LSI Corporation
    Inventor: Rajiv Roy
  • Patent number: 8952728
    Abstract: An object of the invention is to reduce the power consumption of a semiconductor device that requires a plurality of reference potentials and a method of driving the semiconductor device. Disclosed is a semiconductor device having a potential divider circuit in which a potential supplied to a power supply line is resistively divided by resistors connected in series to the power supply line so that a desired potential is output through a switch transistor electrically connected to the power supply line. A drain terminal of the switch transistor is electrically connected to a gate terminal of a transistor provided in a circuit on the output side (or to one terminal of a capacitor) to form a node. The switch transistor has an off current low enough to hold the desired voltage in the node even when the potential is no more supplied to the power supply line.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: February 10, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiya Takewaki, Yutaka Shionoiri, Koichiro Kamata
  • Patent number: 8901966
    Abstract: Provided is a sensor circuit which can amplify a sensor signal at high speed and with a high amplification factor without increasing the current consumption. The sensor circuit includes a primary amplifier for amplifying in advance a differential output signal which is a current signal of a sensor element, a secondary amplifier for amplifying the amplified differential output signal, a constant voltage generating circuit for maintaining a sensor element driving current to be constant, and a feedback circuit for feeding back a feedback signal to adjust an amplification factor. Most of the currents which pass through the primary amplifier are bias currents of the sensor element.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: December 2, 2014
    Assignee: Seiko Instruments Inc.
    Inventor: Kiyoshi Yoshikawa
  • Patent number: 8884653
    Abstract: Disclosed is a comparator including a switching element, a differential pair, and a positive feedback part, the positive feedback part including a first CMOS inverter and a second CMOS inverter, the first CMOS inverter including a first element for providing a potential difference between a first PMOS transistor and a first NMOS transistor, the second CMOS inverter including a second element for providing a potential difference between a second PMOS transistor and a second NMOS transistor, a higher potential side of the first element being connected to a gate of the second NMOS transistor, a lower potential side of the first element being connected to a gate of the second PMOS transistor, a higher potential side of the second element being connected to a gate of the first NMOS transistor, and a lower potential side of the second element being connected to a gate of the first PMOS transistor.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: November 11, 2014
    Assignee: Mitsumi Electric Co., Ltd.
    Inventor: Fumihiro Inoue
  • Patent number: 8836374
    Abstract: According to one embodiment, a high performance buffer for use in a communications system includes first and second differential blocks. Each of the first and second differential blocks comprise one or more driving transistors for generating a driving current for a load of the high performance buffer, and a feedback path for adjusting the operation of the one or more driving transistors. The feedback path includes a feedback transistor for receiving a common mode bias voltage, wherein the common mode bias voltage depends at least in part on a threshold voltage of the feedback transistor. The feedback path includes a programmable resistor and capacitor to reduce out of band loop gain and the noise. The high performance buffer is configured to achieve a high linearity, low output impedance, and low noise, and is suitable for use as a pre-mixer buffer in a wireless communications system.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: September 16, 2014
    Assignee: Broadcom Corporation
    Inventors: Amir Hadji-Abdolhamid, Ahmad Mirzaei, Hooman Darabi
  • Patent number: 8810282
    Abstract: Apparatus and methods for voltage comparison are provided. In one embodiment, a comparator includes a first input transistor having a gate configured to receive a first input voltage and a second input transistor having a gate configured to receive a second input voltage. The first and second input transistors can be used to compare the first input voltage to the second input voltage. Additionally, the comparator further includes a first Miller capacitor electrically connected to a drain of the first input transistor and a second Miller capacitor electrically connected to a drain of the second input transistor. Furthermore, first and second inverting amplification circuits are electrically connected across the first and second Miller capacitors, respectively, so as to increase the effective capacitance of the capacitors. The first and second Miller capacitors can be used to extend the comparator's integration time, thereby enhancing the performance of the comparator.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: August 19, 2014
    Assignee: Analog Devices Inc.
    Inventor: Hongxing Li
  • Patent number: 8717083
    Abstract: A method including receiving an input signal; amplifying the input signal to generate an output signal using a cascade of a plurality of amplifier stages including a first amplifier stage and a last amplifier stage; generating a voltage signal by sensing the output signal in a noninvasive manner so that the sensing results in substantially no change to the output signal; generating a current signal from the voltage signal using a transconductance amplifier; and injecting the current signal into an output node of the first amplifier stage in a noninvasive manner so that the injecting results in substantially no change to an amplification function of the first amplifier stage.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: May 6, 2014
    Assignee: Realtek Semiconductor Corp.
    Inventor: Chia-Liang Lin
  • Patent number: 8710867
    Abstract: An auto-mute control circuit is disclosed. The auto-mute control circuit includes an analog amplifier, a detecting circuit and a direct-current (DC) level adjusting circuit. The analog amplifier receives an input signal and outputs a sensing voltage signal accordingly. The detecting circuit compares a common-mode voltage received with the sensing voltage signal received and outputs a comparison signal accordingly. The DC adjusting circuit receives the comparison signal and outputs an Up-Down digital signal, a fine tune digital signal and a rough tune digital signal, so that a sensing DC level is equal to the common-mode voltage.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: April 29, 2014
    Assignee: Anpec Electronics Corporation
    Inventor: Ming-Huang Chang
  • Publication number: 20140035623
    Abstract: A comparator is provided having a voltage generator, having an output terminal for providing a reference voltage. The comparator also has a buffer unit, providing an output signal according to a first input signal and the reference voltage; wherein the voltage generator provides the reference voltage according to a second input signal, and the output signal represents a compare result of the first and second input signals.
    Type: Application
    Filed: October 15, 2013
    Publication date: February 6, 2014
    Applicant: MediaTek Inc.
    Inventor: Keng-Jan HSIAO
  • Patent number: 8604838
    Abstract: An apparatus for comparing differential input signal inputs is provided. The apparatus comprises a CMOS sense amplifier (which has having a first input terminal, a second input terminal, a first output terminal, and a second output terminal), a first output circuit (which has a first load capacitance), a second output circuit (which has a second load capacitance), and an isolation circuit. The isolation circuit is coupled between the first output terminal of the CMOS sense amplifier and the first output circuit and is coupled between the second output terminal of the CMOS sense amplifier and the second output terminal of the CMOS sense amplifier. The isolation circuit isolates the first and second load capacitances from the CMOS sense amplifier.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: December 10, 2013
    Assignee: Texas Instruments Incorporated
    Inventor: Robert F. Payne
  • Patent number: 8598913
    Abstract: This document discusses, among other things, apparatus and methods for controlling a hysteresis range of a voltage comparator. In an example, an apparatus can include an amplifier having a temperature dependency, a comparator configured to receive first and second currents and to provide an output voltage indicative of a hysteretic comparison of the first and second input voltages, wherein a range of hysteresis of the apparatus is controlled over a range of temperatures. In an example, the amplifier can be configured to receive first and second input voltages and to provide the first and second currents.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: December 3, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Tyler Daigle, Andrew M. Jordan
  • Patent number: 8581632
    Abstract: A comparator is provided. The comparator includes a voltage generator, a buffer unit and a threshold control loop. The voltage generator has an output terminal for providing a reference voltage according to a constant current. The buffer unit provides an output signal according to a first input signal and a bias signal. The threshold control loop provides the bias signal to the buffer unit according to a second input signal, so as to regulate a transition threshold of the buffer unit to close to the second input signal. The output signal represents a compare result of the first and second input signals. The buffer unit and the threshold control loop are powered by the reference voltage.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: November 12, 2013
    Assignee: Mediatek Inc.
    Inventor: Keng-Jan Hsiao
  • Patent number: 8581631
    Abstract: A sense amplifier according to the present invention for detecting a potential difference of signals input to a first input terminal and a second input terminal, includes a first means for applying voltages corresponding to threshold voltages of first and second transistors to gate-source voltages of the first and second transistors, and a second means for transferring signals input to the first and second input terminals to gates of the first and second transistors. In this case, a threshold variation of the first and second transistors is corrected.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: November 12, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yutaka Shionoiri, Kiyoshi Kato, Munehiro Azami
  • Patent number: 8525554
    Abstract: The present invention provides a high-side signal sensing circuit. The high-side signal sensing circuit comprises a signal-to-current converter, a second transistor and a resistor. The signal-to-current converter has a first transistor generating a mirror current in response to an input signal. The second transistor cascaded with the first transistor is coupled to receive the mirror current. The resistor generates an output signal in response to the mirror current. Wherein, the level of the output signal is corrected to the level of the input signal.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: September 3, 2013
    Assignee: System General Corporation
    Inventors: Ta-Yung Yang, Kai-Fang Wei, Yen-Ting Chen
  • Publication number: 20130214948
    Abstract: A single-ended to differential buffer circuit is is disclosed, adapted to couple at least an input analog signal to a receiving circuit. The buffer circuit comprises an output section comprising a differential amplifier having a first and a second input, a first and a second output. The buffer circuit further comprises an input section comprising a first and a second switched capacitor, each adapted to sample said input analog signal and having a first side and a second side, the first sides of the first and second switched capacitors being controllably connectable/disconnectable to/from said first and second outputs respectively. In the buffer circuit the second sides of said first and second switched capacitors are controllably connectable/disconnectable to/from said first and second inputs of the differential amplifier respectively.
    Type: Application
    Filed: September 8, 2011
    Publication date: August 22, 2013
    Applicant: ST-ERICSSON SA
    Inventors: Germano Nicollini, Alberto Minuti, Marco Zamprogno
  • Patent number: 8514631
    Abstract: Determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a plurality of NAND strings and a buffer are formed.
    Type: Grant
    Filed: June 7, 2011
    Date of Patent: August 20, 2013
    Assignee: Spansion LLC
    Inventors: Bruce Lee Morton, Michael VanBuskirk
  • Publication number: 20130200924
    Abstract: A comparator is provided. The comparator includes a voltage generator, a buffer unit and a threshold control loop. The voltage generator has an output terminal for providing a reference voltage according to a constant current. The buffer unit provides an output signal according to a first input signal and a bias signal. The threshold control loop provides the bias signal to the buffer unit according to a second input signal, so as to regulate a transition threshold of the buffer unit to close to the second input signal. The output signal represents a compare result of the first and second input signals. The buffer unit and the threshold control loop are powered by the reference voltage.
    Type: Application
    Filed: September 12, 2012
    Publication date: August 8, 2013
    Applicant: MEDIATEK INC.
    Inventor: Keng-Jan HSIAO
  • Patent number: 8482317
    Abstract: A comparator (10) includes a first input transistor (M0) having a drain coupled to a gate and drain of a first diode-connected transistor (M2) and a gate of a first current mirror output transistor (M4), and a second input transistor (M1) having a drain coupled to a gate and drain of a second diode-connected transistor (M3) and a gate of a second current mirror output transistor (M5). Sources of the first and second current mirror output transistors are connected to a supply voltage (VDD). Gates of the first and second input transistors are coupled to first (VIN?) and second (VIN+) input signals, respectively. Sources of the first and second diode-connected transistors are coupled to drains of the first and second current mirror output transistors, respectively. A latch circuit (M8,M9) is coupled to the drains of the first and second current mirror output transistors.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: July 9, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Vadim V. Ivanov, Harish Venkataraman, Daniel A. King
  • Patent number: 8483001
    Abstract: A level detector, an internal voltage generator including the level detector, and a semiconductor memory device including the internal voltage generator are provided. The internal voltage generator includes a level detector that compares a threshold voltage that varies with temperature with an internal voltage to output a comparative voltage, and an internal voltage driver that adjusts an external supply voltage in response to the comparative voltage and that outputs an internal voltage.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: July 9, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Heung Kim, Yong-Ho Cho, Ji-Hoon Lim, Seong-Jin Jang, Tae-Yoon Lee
  • Patent number: 8456215
    Abstract: A limiting amplifier and method are provided. In one implementation an apparatus includes a plurality of amplifier stages including a first amplifier stage and a last amplifier stage configured in a cascade arrangement, and a transconductance amplifier, wherein the first amplifier stage is configured to receive an input signal; the last amplifier stage outputs an output signal; the transconductance amplifier is configured receive a voltage signal from the last amplifier stage via a first resistor; and the transconductance amplifier is configured to output a current signal to an output node of the first amplifier stage via a second resistor in a negative feedback manner.
    Type: Grant
    Filed: September 25, 2011
    Date of Patent: June 4, 2013
    Assignee: Realtek Semiconductor Corp.
    Inventor: Chia-Liang Lin
  • Patent number: 8378716
    Abstract: A bulk-driven current-sense amplifier and an amplifier operating method are disclosed. The bulk-driven current-sense amplifier includes a differential amplifier, a first driver, and a second driver. The first driver is coupled to the differential amplifier, and a first node is formed at a connectivity segment of the first driver. The second drive is coupled to the differential amplifier, and a second node is formed at a connectivity segment of the second driver. When a first switch of the first driver and a second switch of the second driver are turned on, the differential amplifier charges the first node and the second node. When the charging is completed, the first node and the second node respectively have a different stabilized potential according to currents separately flowing through a first memory unit of the first driver and a second memory unit of the second drive, and the differential amplifier generates a voltage.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: February 19, 2013
    Assignee: National Tsing Hua University
    Inventors: Che-Wei Wu, Meng-Fan Chang, Ku-Feng Lin
  • Patent number: 8330498
    Abstract: A sense amplifier according to the present invention for detecting a potential difference of signals input to a first input terminal and a second input terminal, includes a first means for applying voltages corresponding to threshold voltages of first and second transistors to gate-source voltages of the first and second transistors, and a second means for transferring signals input to the first and second input terminals to gates of the first and second transistors. In this case, a threshold variation of the first and second transistors is corrected.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: December 11, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yutaka Shionoiri, Kiyoshi Kato, Munehiro Azami
  • Patent number: 8284624
    Abstract: A level detector, an internal voltage generator including the level detector, and a semiconductor memory device including the internal voltage generator are provided. The internal voltage generator includes a level detector that compares a threshold voltage that varies with temperature with an internal voltage to output a comparative voltage, and an internal voltage driver that adjusts an external supply voltage in response to the comparative voltage and that outputs an internal voltage.
    Type: Grant
    Filed: January 22, 2010
    Date of Patent: October 9, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Heung Kim, Yong-Ho Cho, Ji-Hoon Lim, Seong-Jin Jang, Tae-Yoon Lee
  • Patent number: 8232828
    Abstract: There is provided an analog circuit having improved response time. An analog circuit having improved response time may include: a low level limiter converting a signal having a lower level than a predetermined reference level into a signal having a predetermined non-low level higher than the predetermined reference level; and an analog circuit section amplifying the signal from the low level limiter into a signal having a predetermined level.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: July 31, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Shinichi Iizuka, Sang Hee Kim, Jun Kyung Na, Sang Hoon Ha
  • Patent number: 8230281
    Abstract: A test driver transmitter drives a test signal through a resistive termination circuit to a first pin to test components on a board during a boundary scan test operation. A test receiver receives the test signal through a second pin and a pass gate coupled to the second pin during the boundary scan test operation. A test signal is transmitted to the test receiver during loopback operation through a loopback circuit.
    Type: Grant
    Filed: April 13, 2009
    Date of Patent: July 24, 2012
    Assignee: Altera Corporation
    Inventors: Sriram Narayan, Xiaoyan Su, Wilson Wong
  • Patent number: 8081015
    Abstract: A differential amplifier includes an amplification unit and a feedback unit. The amplification unit amplifies a voltage difference between a first input signal and a second input signal and outputs a first output signal and a second output signal. The feedback unit amplifies a voltage difference between a first feedback signal based on the first output signal and a second feedback signal based on the second output signal.
    Type: Grant
    Filed: March 17, 2010
    Date of Patent: December 20, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sung-Joo Ha
  • Patent number: 8031547
    Abstract: A differential sense amplifier can perform data sensing using a very low supply voltage.
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: October 4, 2011
    Assignee: Atmel Corporation
    Inventors: Jimmy Fort, Renaud Dura, Thierry Soude
  • Patent number: 8030972
    Abstract: A latched comparator circuit. The latched comparator circuit comprises a first and a second output terminal for outputting a first and a second output voltage, respectively, of the latched comparator circuit. Furthermore, the latched comparator circuit comprises a cross-coupled pair of transistors operatively connected between the first and the second output terminal for providing a positive feedback in the latched comparator circuit. In addition, the latched comparator circuit comprises a reset terminal for receiving a reset signal and reset circuitry arranged to balance the first and the second output voltage during a first phase of the reset signal and allow a voltage difference to develop between the first and the second output voltage during a second phase of the reset signal.
    Type: Grant
    Filed: November 17, 2009
    Date of Patent: October 4, 2011
    Assignee: Zoran Corporation
    Inventor: Christer Jansson
  • Patent number: 8018253
    Abstract: A sense amplifier circuit is provided with a first transistor arrangement comprising a first n-type field effect transistor (NFET) having a respective body node, and a second transistor arrangement comprising a second NFET having a respective body node. The second transistor arrangement is electrically coupled to the first transistor arrangement, and the body node of the first NFET is electrically coupled to the body node of the second NFET. The sense amplifier circuit also includes or cooperates with a voltage condition selector that is electrically coupled to the body node of the first NFET and to the body node of the second NFET. The voltage condition selector is configured to assert one of a plurality of voltage conditions at the body node of the first NFET and at the body node of the second NFET.
    Type: Grant
    Filed: August 28, 2009
    Date of Patent: September 13, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Russell Schreiber, Keith Kasprak
  • Patent number: 7983089
    Abstract: During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a plurality of NAND strings and a buffer are formed.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: July 19, 2011
    Assignee: Spansion LLC
    Inventors: Bruce Lee Morton, Michael VanBuskirk
  • Patent number: 7965118
    Abstract: Described herein are methods and apparatuses for achieving a desired duty cycle on an output of a PLL. According to one embodiment, a method is described, including generating a single ended clock signal from a differential common mode clock signal using a limiting differential amplifier, wherein the single ended clock signal has a duty cycle, generating a differential bias current signal in response to the duty cycle of the single ended clock signal, and correcting the duty cycle of the single ended clock signal to a desired duty cycle by applying the differential bias current signal to the limiting differential amplifier.
    Type: Grant
    Filed: July 11, 2008
    Date of Patent: June 21, 2011
    Assignee: Honeywell International Inc.
    Inventor: James Douglas Seefeldt
  • Publication number: 20110133782
    Abstract: A method and circuit arrangement is provided for controlling switching transistors of an integrated circuit, with a bridge circuit and with a control unit, which is designed and/or has a program so that the control unit is designed as a measuring device and measures a bridge voltage of the bridge circuit, outputs an adjusting signal for adjusting a component of a bridge circuit, and outputs a control signal for activating the switching transistors. When the bridge circuit) has a branch with a resistor network and a transistor connected in series, and the control unit is designed and/or has a program so that the adjusting signal for adjusting a resistance value of the resistor network is switchable as the component dependent on the bridge voltage.
    Type: Application
    Filed: December 6, 2010
    Publication date: June 9, 2011
    Applicant: Micronas GmbH
    Inventors: Martin Czech, Ulrich Theus
  • Publication number: 20110001515
    Abstract: A method and circuit for attenuating positive feedback in a comparator in one embodiment includes an amplifier configured to compare a first input signal with a second input signal and to provide an output based upon the comparison, a non-linear function with a first input operably connected to an output of the amplifier, and a feedback loop operably connected to the output of the non-linear function and to a second input of the non-linear function, the feedback loop including a feedback limiting circuit configured to attenuate a feedback signal to the second input of the non-linear function.
    Type: Application
    Filed: July 2, 2009
    Publication date: January 6, 2011
    Applicant: Robert Bosch GmbH
    Inventors: Robert Wolf, Christoph Lang, Xinyu Xing, Sam Kavusi
  • Patent number: 7847598
    Abstract: A sense amplifier according to the present invention for detecting a potential difference of signals input to a first input terminal and a second input terminal, includes a first means for applying voltages corresponding to threshold voltages of first and second transistors to gate-source voltages of the first and second transistors, and a second means for transferring signals input to the first and second input terminals to gates of the first and second transistors. In this case, a threshold variation of the first and second transistors is corrected.
    Type: Grant
    Filed: May 21, 2009
    Date of Patent: December 7, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yutaka Shionoiri, Kiyoshi Kato, Munehiro Azami
  • Patent number: 7825733
    Abstract: The present invention discloses a circuit providing a power for a sense amplifier that stabilizes a power voltage supplied to the sense amplifier by compensating a noise generated in the power voltage when the sense amplifier operates with an selectively generated decoupling noise. The circuit providing a power for a sense amplifier includes a sense amplifying circuit sensing and amplifying data loaded on a bit line with a first power. A power supplying unit provides the first power to the sense amplifying circuit. A decoupling unit generates a decoupling noise with a second power and provides the decoupling noise to the first power voltage. The decoupling noise is maintained for a period including a time point of an operation of the sense amplifying circuit and a predetermined time thereafter.
    Type: Grant
    Filed: June 10, 2008
    Date of Patent: November 2, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jun Gi Choi
  • Patent number: 7813201
    Abstract: A differential sense amplifier can perform data sensing using a very low supply voltage.
    Type: Grant
    Filed: July 8, 2008
    Date of Patent: October 12, 2010
    Assignee: ATMEL Corporation
    Inventors: Jimmy Fort, Renaud Dura, Thierry Soude
  • Patent number: 7782126
    Abstract: A mechanism is provided for a one card to filter false signals due to a another card being hot-plugged. A discriminator circuit in the card receives a low-state signal via an input and, responsive to receiving the low-state signal, the discriminator circuit compares the low-state signal to a static signal. Responsive to the low-state signal being greater than the static signal, the discriminator circuit outputs a high-voltage signal. The high-voltage signal output by the discriminator circuit indicates that the low-state signal is a false low signal. Responsive to the low-state signal being less than or equal to the static signal, the discriminator circuit outputs a low-voltage signal. The low-voltage signal output by the discriminator circuit indicates that the low-state signal is a valid low signal.
    Type: Grant
    Filed: January 29, 2008
    Date of Patent: August 24, 2010
    Assignee: International Business Machines Corporation
    Inventors: Brian James Cagno, Gregg Steven Lucas, Tohru Sumiyoshi
  • Patent number: 7778374
    Abstract: A dual reference input receiver, and a method of receiving, wherein the input receiver includes a first input buffer which is synchronized with and enabled by a clock signal, senses a difference between the input data signal and a first reference voltage, and amplifies the sensing result; a second input buffer which is synchronized with and enabled by the clock signal, senses a difference between a second reference voltage and the input data signal, and amplifies the sensing result; and a phase detector which detects a difference between a phase of output signals of the first and second input buffers, and outputs a signal corresponding to the detection result. The first and second reference voltages may respectively be higher and lower than a median voltage of the input data signal. Thus, a single input data signal is advantageously used and a wide input data eye is provided.
    Type: Grant
    Filed: August 9, 2006
    Date of Patent: August 17, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Young-jin Jeon
  • Patent number: 7768320
    Abstract: One embodiment of the present invention sets forth a sense amplifier flop design that is tolerant of process variation. Specific staging of signal transitions through the sense amplifier flop circuit eliminate operational phases involving short-circuit currents between n-channel field-effect transistors (N-FETs) and p-channel field effect transistors (P-FETs) in a complementary-symmetry metal-oxide semiconductor process. By eliminating short-circuit currents between N-FETs and P-FETs within the sense amplifier flop, a large variation in conductivity ratio between N-FETs and P-FETs may be tolerated by the sense amplifier flop. This tolerance to conductivity ratio translates to a tolerance for process variation by the sense amplifier flop circuit.
    Type: Grant
    Filed: November 20, 2007
    Date of Patent: August 3, 2010
    Assignee: NVIDIA Corporation
    Inventors: Ge Yang, Hwong-Kwo Lin, Charles Chew-Yuen Young
  • Patent number: 7759981
    Abstract: An amplifying circuit of a semiconductor integrated circuit includes a data amplifier that outputs an up-signal and a down-signal amplified according to a comparison result between an up-data signal and a down-data signal in response to a control signal. The data amplifier repeats an operation of amplifying the up-signal and the down-signal according to the comparison result between the up-signal and the down-signal to be fed back to the data amplifier.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: July 20, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sung-Joo Ha
  • Publication number: 20100164449
    Abstract: A controller and an output filter for a power converter, and a power converter employing at least one of the same. In one embodiment, the controller includes an error amplifier with first and second input terminals coupled to one of an operating characteristic and a reference voltage of the power converter, and a switch configured to couple the first and second input terminals to one of the operating characteristic and the reference voltage as a function of a power conversion mode of the power converter. In one embodiment, the output filter includes an output filter capacitor with a first terminal coupled to a first output terminal of a power converter, and an output filter inductor coupled between a second terminal of the output filter capacitor and a second output terminal of the power converter.
    Type: Application
    Filed: December 29, 2008
    Publication date: July 1, 2010
    Inventors: Mirmira Ramarao Dwarakanath, Jeffrey Demski, Ahmed Mohamed Abou-Alfotouh
  • Patent number: 7714622
    Abstract: An input stage of an integrated circuit, includes a comparator for comparing the voltage of an input signal of the input stage with a reference voltage, and supplying a binary output signal the value of which depends on the result of the comparison of the input signal with the reference voltage. The input stage comprises a feedback circuit measuring a parameter representative of the operation of the comparator, and raising the reference voltage while the measured parameter reveals a faulty operation of the comparator.
    Type: Grant
    Filed: January 17, 2007
    Date of Patent: May 11, 2010
    Assignee: STMicroelectronics SA
    Inventor: Francois Tailliet
  • Patent number: 7701256
    Abstract: A signal conditioning circuit for a latching comparator comprising first and second transistors arranged in a long tail pair, the long tail pair having an active load and configured to act as an integrator.
    Type: Grant
    Filed: September 17, 2007
    Date of Patent: April 20, 2010
    Assignee: Analog Devices, Inc.
    Inventors: Christopher Peter Hurrell, Colin Gerard Lyden