Cross-coupled Patents (Class 327/55)
  • Patent number: 11227651
    Abstract: A read path for reading data from a memory includes a sense amplifier having data (SAT) and data complement (SAC) output nodes and a latch. The latch includes an input tri-state inverter including first and second PMOS transistors connected between VDD and an intermediate node, and first and second NMOS transistors connected between VSS and the intermediate node. A gate connection of the first PMOS and NMOS transistors is connected to the SAT node; a gate connection of the second PMOS transistor is connected to a sense amplifier enable complement input; and a gate connection of the second NMOS transistor is connected to a sense amplifier enable input. The latch also includes an output driver with an input connected to the intermediate node and an output connected to a data output node. The latch thus has two gate delays between the SAT node and the data output node.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: January 18, 2022
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Arijit Banerjee, Russell Schreiber, Kyle Whittle
  • Patent number: 11206022
    Abstract: A skew compensation circuit includes a skew detection circuit configured to generate skew detection signals by detecting a skew characteristic of a basic logic element constituting a semiconductor apparatus, a skew compensation signal generation circuit configured to generate a skew compensation signal by comparing the skew detection signals and a plurality of reference voltages, a variable delay circuit configured to generate a compensation signal by delaying an input signal by a delay time varied according to the skew compensation signal, and a reference voltage generation circuit configured to generate the plurality of reference voltages of which offset components are compensated for according to variations of a temperature and an external voltage.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: December 21, 2021
    Assignee: SK hynix Inc.
    Inventors: Young Suk Seo, Seung Wook Oh, Da In Im
  • Patent number: 11195576
    Abstract: A sense amplifier enable signal and a tracking signal are generated in response to an indication that a sufficient voltage difference has developed across bit lines of a memory. The sense amplifier enable signal has a pulse width between a leading edge and a trailing edge. The sense amplifier enable signal is propagated along a first U-turn signal line that extends parallel to rows of the memory array and is coupled to sense amplifiers arranged in a row to generate a sense amplifier enable return signal. The tracking signal is propagated along a second U-turn signal line extending parallel to columns of the memory array to generate a tracking return signal. The sense amplifier enable return signal and the tracking return signal are logically combined to generate a reset signal. Timing of the trailing edge of the pulse width is controlled by the reset signal.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: December 7, 2021
    Assignee: STMicroelectronics International N.V.
    Inventors: Shishir Kumar, Bhupender Singh
  • Patent number: 11128326
    Abstract: A digital radio-frequency (RF) circuitry is disclosed. In one aspect, the circuitry includes a digitally controlled amplifier configured to receive an RF input signal and a digital control signal, and to output an amplitude controlled output signal. The digitally controlled amplifier includes one or more common-source amplifying unit cells. A respective common-source amplifying unit cell includes a sources node connected to a switching circuitry controllable by the digital control signal so as to activate or deactivate the common-source amplifying unit cell. The switching circuitry comprises a first switch configured to connect the source node with a first power supply node and a second switch configured to connect the source node with a second power supply node when activating and deactivating, respectively, the common-source amplifying unit cell.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: September 21, 2021
    Assignees: IMEC vzw, Vrije Universiteit Brassel
    Inventors: Johan Nguyen, Khaled Khalaf, Pierre Wambacq, Jan Craninckx
  • Patent number: 11057025
    Abstract: A level shifter includes: a first inverter configured to receive an input signal in a first voltage domain and shift the input signal from the first voltage domain to a first output signal at a first output terminal in a second voltage domain higher than the first voltage domain in response to a logical high state of a first clock signal in the first voltage domain; a second inverter configured to receive a complement of the input signal and shift the complement of the input signal from the first voltage domain to a second output signal at a second output terminal in the second voltage domain in response to the logical high state; a pair of NMOS sensing transistors; a PMOS transistor configured to equalize the first output signal and the second output signal in response to a logical low state of the first clock signal.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: July 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Yuan Chen, Cheng Hung Lee, Hung-Jen Liao, Hau-Tai Shieh
  • Patent number: 11025237
    Abstract: Described is a high speed, low power level shifter circuit which includes a level shifter coupled to a sensing circuit. The level shifter includes a pair of source transistors, a pair of input transistors, and a pair of switching circuits connected between the source transistors and the input transistors. The sensing circuit turns off a switching circuit on an active side of the level shifter based on detecting that an output voltage of the level shifter has completed a voltage level transition from a first logic level voltage to a second logic level voltage. An open circuit is established on the active side and turns off the pair of source transistors. The other switching circuit is turned on. Static current flow on the active side of the level shifter is stopped and the output voltage is latched to a voltage representative of the second logic level voltage.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: June 1, 2021
    Assignee: SiFive, Inc.
    Inventors: Santosh Mahadeo Narawade, Jithin K, Mohit Gupta
  • Patent number: 10978148
    Abstract: Various embodiments provide a hybrid sensing scheme that may compensate for cell resistance instability in semiconductor devices, such as multi-level cell (MLC) type phase-change random-access memory (PCRAM) structures. Various embodiments may achieve a stable resistance state supporting MLC applications in PCRAM cells.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: April 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventor: Jau-Yi Wu
  • Patent number: 10778198
    Abstract: A level shifter includes: an input terminal configured to receive an input signal in a first voltage domain; a first output terminal; a second output terminal; a first inverter configured to receive and shift the input signal to a first output signal at the first output terminal in a second voltage domain higher than the first voltage domain in response to a logical high state of an enable signal in the first voltage domain; a second inverter configured to receive and shift a complement of the input signal to a second output signal at the second output terminal in the second voltage domain in response to the logical high state; a pair of NMOS sensing transistors; a PMOS transistor configured to equalize the first output signal and the second output signal in response to a logical low state of the enable signal.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: September 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, LTD
    Inventors: Chien-Yuan Chen, Cheng Hung Lee, Hung-Jen Liao, Hau-Tai Shieh
  • Patent number: 10742202
    Abstract: Techniques for autozero to an offset value for a slope detector for voltage droop monitoring are described herein. An aspect includes generating a first offset voltage by a circuit. Another aspect includes generating a second offset voltage by the circuit, the second offset voltage being distinct from the first offset voltage. Another aspect includes, based on a first comparator of the circuit entering an autozero mode, connecting a first terminal of the first comparator to the first offset voltage. Another aspect includes connecting a second terminal of the first comparator to the second offset voltage. Yet another aspect includes performing an autozero operation in the first comparator, wherein a trip point of the first comparator is set to a difference between the first offset voltage and the second offset voltage by the autozero operation.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: August 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Erik English, Michael Sperling
  • Patent number: 10614893
    Abstract: A nonvolatile memory device includes: a first reference cell; a second reference cell; a circuit that generates a first mirror current proportional to a current flowing through the first reference cell; a circuit that generates a second mirror current proportional to a current flowing through the second reference cell; a sense amplifier that reads out data by comparing a current flowing through a memory cell with a reference current; and a selection circuit that sets a selection state of the first reference cell and the second reference cell such that, in a readout mode, the reference current is generated based on at least the first mirror current, and in a verify mode, the reference current is generated based on the second mirror current.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: April 7, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Takeshi Miyazaki
  • Patent number: 10566035
    Abstract: A sense amplifier includes a latch type sense unit that detects a voltage difference between a bit line and a bit line bar and causes a voltage difference between a first latch output node and a second latch output node. The sense amplifier further includes a first latch connection unit that electrically connects the bit line to and disconnects the bit line from the first latch output node.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: February 18, 2020
    Assignee: SK hynix Inc.
    Inventors: Seung Han Oak, Sang Hyun Ku
  • Patent number: 10566050
    Abstract: Embodiments herein describe a memory cell (e.g., a SRAM memory cell) that includes power selection logic for disconnecting storage inverters from a reference voltage source when writing data into the cell. In one embodiment, the memory cells may be disposed long distances (e.g., more than 100 microns) from the data drivers in the integrated circuit which can result in the data lines having large RC time constants. In one embodiment, disconnecting the memory cells from a power supply may counter (or mitigate) the large RC time constants of the data lines.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: February 18, 2020
    Assignee: XILINX, INC.
    Inventors: Shidong Zhou, Nui Chong, Jing Jing Chen
  • Patent number: 10559346
    Abstract: Embodiments include a method, memory system and a device for the operating a bit-line sensing circuit for bias-controlled bit-line sensing, the embodiments include an input for receiving a single-ended local bit-line signal, a pass device having a first terminal coupled to the input and a second terminal connected to a global bit-line node, The embodiments also include a first inverter having an input connected to the global bit-line node, a header circuit coupled to the first inverter and a first direct current (DC) bias circuit, and a footer circuit coupled to the first inverter and a second DC bias circuit. The embodiments include a second gated inverter having an input coupled to an output of the first inverter.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: February 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Abraham Mathews, Donald W Plass
  • Patent number: 10529388
    Abstract: A current sense amplifier is provided. The amplifier comprises a first cross coupled inverter, a second cross coupled inverter, and a transmission gate. The first cross coupled inverter has a first source coupled to sense current input. The second cross coupled inverter has a second source coupled to a reference current input. The transmission gate comprises a first transmission end, a second transmission end, and a gate input. The first transmission end is operatively coupled to a first input of the first cross coupled inverter. The second transmission end is operatively coupled to a second input of the second cross coupled inverter. The gate input is operatively coupled to the control line input. Each cross coupled inverter is configured for switching a coupling of the sense current input and the reference current input.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: January 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Alexander Fritsch, Michael Kugel, Juergen Pille, Dieter Wendel
  • Patent number: 10505519
    Abstract: A dynamic comparator includes two sets of input transistors of opposite conductivity types, where a control electrode of one transistor of each set is coupled to a first input of the comparator and a control input of a second transistor of each set is coupled to a second input of the comparator. The comparator includes bypass transistors for pulling current electrodes of either the first set or second set of input transistors to a power supply terminal depending which input voltage is higher as determined by the output.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: December 10, 2019
    Assignee: NXP USA, INC.
    Inventors: Tao Chen, Xiankun Jin, Jan-Peter Schat
  • Patent number: 10498989
    Abstract: A digital double-sampling (DDS) circuit includes a comparator with input nodes respectively connected to a ramp voltage and an image output node of a pixel circuit via a capacitor; a reset switch connected between the input nodes for resetting the capacitor; an analog-to-digital converter (ADC) coupled to receive a comparison output of the comparator, the ADC including a counter that counts while the ramp voltage is ramping, thereby generating a reset-ADC value in a reset phase and generating a signal-ADC value in a signal phase; a subtractor that subtracts the reset-ADC value from the signal-ADC value, thereby resulting in a difference value representing a sampled output; and a clamp circuit that generates a clamp voltage at the image output node. In the reset phase, the clamp circuit is disabled after the capacitor finishes resetting but before the ramp voltage begins ramping.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: December 3, 2019
    Assignee: Himax Imaging Limited
    Inventors: Hack Soo Oh, Youngchul Sohn, Kwangoh Kim
  • Patent number: 10192611
    Abstract: The present provides a sensing circuit, a set of pre-amplifiers, and an operating method thereof. The set of pre-amplifiers includes a first pre-amplifier and a second pre-amplifier. The first pre-amplifier is coupled to a first input terminal of the sense amplifier. The second pre-amplifier is coupled to a second input terminal of the sense amplifier. The first pre-amplifier and the second pre-amplifier respectively performs a discharging operation to discharge the first input terminal and the second input terminal of the sense amplifier after the first input terminal and the second input terminal of the sense amplifier are charged to a predetermined voltage. One of the first pre-amplifier and the second pre-amplifier amplifies a voltage difference between the first input terminal and the second input terminal of the sense amplifier by terminating the discharging operation of another of the first pre-amplifier and the second pre-amplifier.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: January 29, 2019
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Tzu-Hsien Yang, Meng-Fan Chang
  • Patent number: 10148414
    Abstract: Systems and methods for high speed communications are described herein. In certain aspects, the systems and methods include innovative transceiver architectures and techniques for re-timing, multiplexing, de-multiplexing and transmitting data. The systems and methods can be used to achieve reliable high-speed point-to-point communication between different electronic devices, computing devices, storage devices and peripheral devices.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: December 4, 2018
    Assignee: INPHI CORPORATION
    Inventors: Marcel Louis Lugthart, Jeffrey Zachan, Linghsiao Jerry Wang
  • Patent number: 10083970
    Abstract: An SRAM includes an SRAM array including a plurality of SRAM cells arranged in a matrix. Each of the SRAM cells includes six vertical field effect transistors. The SRAM array includes a plurality of groups of conductive regions extending in the column direction. Each of the plurality of groups of conductive regions includes a first to a fourth conductive region arranged in this order in the row direction, and the first to fourth conductive regions are separated by insulating regions from each other. The first, second and third conductive regions are coupled to sources of first conductive type VFETs, and the fourth conductive region is coupled to sources of second conductive type VFETs. The plurality of groups are arranged in the row direction such that the fourth conductive region of one group of conductive regions is adjacent to the first conductive region of adjacent one group of conductive regions.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: September 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Hao Pao, Chang-Ta Yang, Feng-Ming Chang, Ping-Wei Wang
  • Patent number: 9912338
    Abstract: A circuit to sample an input signal in an asynchronous clock domain. The apparatus includes a first latch configured to favor resolving to a logical high level and a second latch configured to favor resolving to a logical low level. The circuit includes a pullup pMOSFET, and first and second pMOSFETs. The first pMOSFET has a source terminal coupled to the drain terminal of the pullup pMOSFET, a gate coupled to a first input port of the first latch, and a drain terminal coupled to a second output port of the second latch. The second pMOSFET has a source terminal coupled to the drain terminal of the pullup pMOSFET, a gate coupled to the second output port of the second latch, and a drain terminal coupled to the first input port of the first latch.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: March 6, 2018
    Assignee: ARM Limited
    Inventors: James Dennis Dodrill, Paul Christopher de Dood
  • Patent number: 9780774
    Abstract: In accordance with an embodiment, an adjustable capacitance circuit comprising a first branch comprising plurality of transistors having load paths coupled in series with a first capacitor. A method of operating the adjustable capacitance circuit includes programming a capacitance by selectively turning-on and turning-off ones of the plurality of transistors, wherein the load path of each transistor of the plurality of transistors is resistive when the transistor is on and is capacitive when the transistor is off.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: October 3, 2017
    Assignee: Infineon Technologies AG
    Inventors: Anthony Thomas, Winfried Bakalski, Valentyn Solomko, Ruediger Bauder
  • Patent number: 9767871
    Abstract: A sense amplifier of a semiconductor device is disclosed. The sense amplifier of a semiconductor device may include a PMOS latch transistor and an NMOS latch transistor formed in a cross-coupled latch type, and may be configured to sense and amplify a signal of a pair of bit lines. The sense amplifier of a semiconductor device may include a Yi transistor configured to output a data signal amplified by the PMOS latch transistor and the NMOS latch transistor according to a column control signal, and may share a well region with the PMOS latch transistor.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: September 19, 2017
    Assignee: SK hynix Inc.
    Inventor: Bum Su Kim
  • Patent number: 9766827
    Abstract: An apparatus is provided which comprises: a first power gate transistor coupled to an ungated power supply node and a gated power supply node, the first power gate transistor having a gate terminal controllable by a first logic; and a second power gate coupled to the ungated power supply node and the gated power supply node, the second power gate transistor having a gate terminal controllable by a second logic, wherein the first power gate transistor is larger than the second power gate transistor, and wherein the second logic is operable to: weakly turn on the second power gate, fully turn on the second power gate, turn off the second power gate, and connecting the second power gate as diode.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: September 19, 2017
    Assignee: Intel Corporation
    Inventors: Pascal A. Meinerzhagen, Stephen T. Kim, Anupama A. Thaploo, Muhammad M. Khellah
  • Patent number: 9761286
    Abstract: A current sense amplifier is provided comprising a reference current input terminal, a control line input terminal, a sense current input terminal and a first output terminal. The amplifier further comprises a first NAND gate comprising first and second gate input terminals, and a second output terminal being coupled to the first output terminal of the amplifier. The amplifier also comprises two cross coupled inverters each comprising an n-FET, an n-FET input terminal, and each n-FET having a respective source. The amplifier further comprises a transmission gate comprising two transmission terminals and a gate terminal. The gate terminal is coupled to the control line terminal.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: September 12, 2017
    Assignee: International Business Machines Corporation
    Inventors: Alexander Fritsch, Michael Kugel, Juergen Pille, Dieter Wendel
  • Patent number: 9640231
    Abstract: A sense amplifier (SA) and a method for operating the SA are provided. The SA includes a first differential pair of transistors configured to receive a first differential input, a second differential pair of transistors configured to receive a second differential input, and a current source configured to source a current to flow through the first and second differential pairs of transistors. The method includes receiving by a first differential pair of transistors a first differential input, receiving by a second differential pair of transistors a second differential input, and flowing a current through the first and second differential pairs of transistors. A multi-bank memory is provided. The memory includes a first bank of memory cells and a second bank of memory cells sharing the disclosed SA.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: May 2, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Fahad Ahmed, Chulmin Jung
  • Patent number: 9467133
    Abstract: A comparator comprises a differential input stage comprising a first n-type transistor and a second n-type transistor, an output stage coupled to the differential input stage, a clock transistor coupled to the differential input stage and a pre-charge apparatus connected in parallel with the clock transistor.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: October 11, 2016
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Euhan Chong
  • Patent number: 9460760
    Abstract: A system and method of operating a twin-transistor single bit multi-time programmable memory cell to provide a high gain, sensing scheme for small signals. The memory cell includes a pair of a first transistor and a second transistor providing a differential signal output. The first transistor of the memory cell couples a first circuit leg having a first current source load transistor and the second transistor couples a second circuit leg having a second current source load transistor. A programmed value is represented by a voltage threshold shift in one of the first or second transistors. A feedback circuit receives one of: a first signal or a second signal of the differential signals, and generates, in response, a feedback signal which is simultaneously applied to bias each current source load transistor in each the first and second circuit legs to amplify a voltage differential between the differential signal outputs.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: October 4, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Balaji Jayaraman, Thejas Kempanna, Toshiaki Kirihata, Ramesh Raghavan, Krishnan S. Rengarajan, Rajesh R. Tummuru
  • Patent number: 9432006
    Abstract: A buffer circuit includes a power supply voltage detection block which may detect a voltage level of a power supply voltage, a bias generation block which may generate a constant bias signal and a plurality of enable bias signals based on the detection result of the power supply voltage, and an input buffer which may amplify an input signal in response to the constant bias signal and the plurality of enable bias signals.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: August 30, 2016
    Assignee: SK HYNIX INC.
    Inventor: Jin Ha Hwang
  • Patent number: 9431071
    Abstract: A bit-line sense amplifier may include a pull-up driving circuit, a pull-down driving circuit and a latch-type sense amplifier. The pull-up driving circuit including a plurality of PMOS transistors connected between a power supply voltage line and a first driving power supply line, and may be configured to provide a first driving current on the first driving power supply line in response to an up control signal. The pull-down driving circuit may be configured to provide a second driving current on a second driving power supply line in response to a down control signal. The latch-type sense amplifier may be connected between the first driving power supply line and the second driving power supply line, and may be configured to sense and amplify a voltage difference between a bit line and a complementary bit line.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: August 30, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-Ho Moon, Tai-Young Ko, Hyung-Sik You
  • Patent number: 9373388
    Abstract: A sense amplifier is provided with a pair of first pull-up transistors that are configured to charge a corresponding pair of output terminals while a delayed sense enable signal is not asserted and to stop charging the corresponding pair of output terminals while the delayed sense enable signal is asserted.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: June 21, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Fahad Ahmed, Chulmin Jung, Sei Seung Yoon
  • Patent number: 9294051
    Abstract: Embodiments of disclosed configurations include a circuit and system for a sense amplifier having a sensing circuit changing an output voltage at an output node based on a time that is defined by the output voltage reaching a threshold voltage level. The sensing circuit changes the output voltage at the output node before the time. In addition, a regeneration circuit amplifies the changed output voltage at the time. The sense amplifier offers sufficient voltage headroom to improve operation speed and power efficiency.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: March 22, 2016
    Assignee: Lattice Semiconductor Corporation
    Inventors: Mrunmay Talegaonkar, Srikanth Gondi
  • Patent number: 9287253
    Abstract: In one well bias arrangement, no well bias voltage is applied to the n-well, and no well bias voltage is applied to the p-well. Because no external well bias voltage is applied, the n-well and the p-well are floating, even during operation of the devices in the n-well and the p-well. In another well bias arrangement, the lowest available voltage is not applied to the p-well, such as a ground voltage, or the voltage applied to the n+-doped source region of the n-type transistor in the p-well. This occurs even during operation of the n-type transistor in the p-well. In yet another well bias arrangement, the highest available voltage is not applied to the n-well, such as a supply voltage, or the voltage applied to the p+-doped source region of the p-type transistor in the n-well. This occurs even during operation of the p-type transistor in the n-well.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: March 15, 2016
    Assignee: Synopsys, Inc.
    Inventors: Victor Moroz, Jamil Kawa, James D. Sproch, Robert B. Lefferts
  • Patent number: 9225320
    Abstract: A circuit includes a voltage-to-current converter receives a first voltage and a second voltage and outputs a first current and a second current in accordance with a clock signal. A first self-gated cascode circuit receives the first current and outputs a third current in accordance with the clock signal. A second self-gated cascode circuit receives the second current and outputs a fourth current in accordance with the clock signal. A latch circuit receives the third current and the fourth current and establishes a third voltage and a fourth voltage representing a resolution of a comparison between the third current and the fourth current, wherein the first self-gated cascode circuit is conditionally shut off based on a level of the third voltage, and the second self-gated cascode circuit is conditionally shut off based on a level of the fourth voltage.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: December 29, 2015
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Chia-Liang (Leon) Lin
  • Patent number: 9203381
    Abstract: A current mode logic latch may include a sample stage and a hold stage, the hold stage comprising first and second stage transistors, first and second hold stage current sources, and a hold stage switch. The first hold stage transistor may be coupled at its drain terminal to the drain terminal of a first sample stage transistor. The second hold stage transistor may be coupled at its drain terminal to the drain terminal of a second sample stage transistor, coupled at its gate terminal to the drain terminal of the first hold stage transistor, and coupled at its drain terminal to a gate terminal of the first hold stage transistor. The first hold stage current source may be coupled to a source terminal of the first hold stage transistor. The second hold stage current source may be coupled to a source terminal of the second hold stage transistor. The hold stage switch may be coupled between the source terminal of the first hold stage transistor and the source terminal of the second hold stage transistor.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: December 1, 2015
    Assignee: Fujitsu Limited
    Inventors: Shuo-Chun Kao, Nikola Nedovic
  • Patent number: 9178508
    Abstract: Embodiments relate to a single multi-output high-voltage (HV) switch configured to pass multiple HV signals in semiconductor integrated circuits, such as a memory device. By utilizing a single HV switch that shares multiple components, area is reduced and fewer numbers of transistor devices are used to reduce cost. The shared components are selected such that the HV switch configuration provides functionality similar to traditional multiple HV switch configurations. Specifically, common logic shared across different branches of the single HV switch enables the single HV switch to provide multiple HV signals.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: November 3, 2015
    Assignee: Synopsys, Inc.
    Inventor: Yanyi Liu Wong
  • Patent number: 9160320
    Abstract: Described herein are an apparatus, system, and method for compensating voltage swing and duty cycle of a signal on an input-output (I/O) pad of a processor by adjusting the voltage swing and duty cycle of the signal. The apparatus comprises a driver to transmit a signal on an I/O pad, the signal on the I/O pad having a voltage swing and a duty cycle; and an adjustment unit, coupled to the driver, to receive the signal from the I/O pad transmitted by the driver and to generate voltage swing and duty cycle control signals for adjusting the voltage swing and duty cycle of the signal on the I/O pad respectively. Described herein is also an analog-to-digital (A2D) converter for measuring and/or calibrating various signal attributes including current, voltage, and time.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: October 13, 2015
    Assignee: Intel Corporation
    Inventors: Eduard Roytman, Jian Xu, Rahul Shah, Kambiz R. Munshi, Ronald L. Bedard, Mahalingam Nagarajan
  • Patent number: 9136828
    Abstract: A current mode logic latch may include a sample stage and a hold stage, the hold stage comprising first and second stage transistors, first and second hold stage current sources, and a hold stage switch. The first hold stage transistor may be coupled at its drain terminal to the drain terminal of a first sample stage transistor. The second hold stage transistor may be coupled at its drain terminal to the drain terminal of a second sample stage transistor, coupled at its gate terminal to the drain terminal of the first hold stage transistor, and coupled at its drain terminal to a gate terminal of the first hold stage transistor. The first hold stage current source may be coupled to a source terminal of the first hold stage transistor. The second hold stage current source may be coupled to a source terminal of the second hold stage transistor. The hold stage switch may be coupled between the source terminal of the first hold stage transistor and the source terminal of the second hold stage transistor.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: September 15, 2015
    Assignee: Fujitsu Limited
    Inventors: Shuo-Chun Kao, Nikola Nedovic
  • Patent number: 9035680
    Abstract: Embodiments of the present invention provide a comparator and an analog-to-digital converter. A sampling module, a pre-amplifying module, and a coupling module in the comparator obtain a third differential voltage signal according to a positive input signal and a negative reference signal, and obtain a fourth differential voltage signal according to a negative input signal and a positive reference signal. A latch that is in the comparator and formed by a first P-type field effect transistor, a second P-type field effect transistor, a third field effect transistor, a fourth field effect transistor, a first switch, and a second switch is directly cross-coupled through gates, and directly collects the third differential voltage signal and the fourth differential voltage signal to the gates, so as to drive the latch to start positive feedback.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: May 19, 2015
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Jinda Yang, Liren Zhou, Jun Xiong
  • Patent number: 9024674
    Abstract: A level shifter including a differential input stage including first and second transistors having respective first terminals, respective control terminals configured to receive a differential input signal, and respective second terminals connected in common to a first voltage; a breakdown voltage controller including third and fourth transistors having respective first terminals, respective second terminals connected to respective first terminals of the first and second transistors, and respective control terminals configured to receive a bias signal, and a load stage comprising fifth and sixth transistors having respective first terminals connected to respective first terminals of the third and fourth transistors, respective control terminals that are cross coupled, and respective second terminals connected to a second voltage is disclosed. A bias voltage applied to bulks or bodies of the first through the fourth transistors equals or substantially equals the first voltage.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: May 5, 2015
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Jong Cheol Kim
  • Patent number: 8970256
    Abstract: The present disclosure relates to a differential sense amplifier comprising first and second cross-coupled inverters with first and second complimentary storage nodes. A first current control element changes a current through the first cross-coupled inverter based upon an output of a second cross-coupled inverter, and a second current control element changes a current through the second cross-coupled inverter based upon an output of the first cross-coupled inverter. Other devices and methods are also disclosed.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: March 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng Hung Lee, Hektor Huang, Chi-Kai Hsieh, Shi-Wei Chang, Hong-Chen Cheng
  • Patent number: 8957706
    Abstract: The present disclosure provides a dynamic comparator with equalization function including a preamplifier, switched latch and dynamic transconductance circuit. The preamplifier amplifies input signals of the dynamic comparator. The dynamic transconductance circuit is inserted between the preamplifier and the switched latch for operating in a reset mode or a comparison mode. When operating in the reset mode, the dynamic transconductance circuit in conjunction with the switched latch performs voltage equalization of output signals of the switched latch, or when operating in the comparison mode, the dynamic transconductance circuit in conjunction with the switched latch receives the output signals generated by the preamplifier and carries out signal transconductance. The switched latch generates output signals as a comparison result of the dynamic comparator based on the transconductance signals generated by the dynamic transconductance circuit.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: February 17, 2015
    Assignee: Industrial Technology Research Institute
    Inventor: Bo-Wei Chen
  • Patent number: 8928357
    Abstract: A sense amplifier is provided. The sense amplifier comprises a first and second cross-coupled transistor pairs, a first and second current sources, a first digital input transistor, and a second digital input transistor. The first and second ends of the first cross-coupled transistor pair are coupled to an operating voltage, the first and second back gate ends of the first cross-coupled transistor pair are coupled to a first and second output ends respectively. The first and second back gate ends of the first cross-coupled transistor pair are coupled to a first and second output ends respectively, and the first and second ends of the first cross-coupled transistor pair are coupled to a first digital input end and second digital input end respectively.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: January 6, 2015
    Assignee: Nanya Technology Corporation
    Inventors: Adam Saleh El-Mansouri, Adrian Jay Drexler, Hofstetter Martin Ryan
  • Patent number: 8890576
    Abstract: An input/output sense amplifier includes: a data input unit configured to amplify data using a driving voltage and to output the amplified data, and a latch unit configured to latch and output an output signal of the data input unit to an output terminal.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: November 18, 2014
    Assignee: SK Hynix Inc.
    Inventor: Jong Su Kim
  • Patent number: 8884653
    Abstract: Disclosed is a comparator including a switching element, a differential pair, and a positive feedback part, the positive feedback part including a first CMOS inverter and a second CMOS inverter, the first CMOS inverter including a first element for providing a potential difference between a first PMOS transistor and a first NMOS transistor, the second CMOS inverter including a second element for providing a potential difference between a second PMOS transistor and a second NMOS transistor, a higher potential side of the first element being connected to a gate of the second NMOS transistor, a lower potential side of the first element being connected to a gate of the second PMOS transistor, a higher potential side of the second element being connected to a gate of the first NMOS transistor, and a lower potential side of the second element being connected to a gate of the first PMOS transistor.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: November 11, 2014
    Assignee: Mitsumi Electric Co., Ltd.
    Inventor: Fumihiro Inoue
  • Publication number: 20140300388
    Abstract: A switching circuit includes a first input stage having an input for receiving a first input signal, an output, and a power terminal for receiving an increasing analog current, a second input stage having an input for receiving a second input signal, an output, and a power terminal for receiving a decreasing analog current, and an output node coupled to the outputs of the first input stage and the second input stage for providing a switched output signal. An output stage is coupled between the first and second input stages and the output node. The first and second input stages are operational amplifiers.
    Type: Application
    Filed: June 20, 2014
    Publication date: October 9, 2014
    Inventors: Min CHEN, Wen LIU, HongXia LI, XiaoWu DAI
  • Patent number: 8836376
    Abstract: A comparator includes: a differential amplifier of which operational state is switched in response to a clock-signal, and which outputs a first intermediate-output corresponding to a first input-signal and a second intermediate-output corresponding to a second input-signal; a differential latch circuit of which operational state is switched in response to the clock-signal, and a state of which is changed depending on the first intermediate-output and the second intermediate-output; a first adjuster configured to adjust a threshold of the differential latch circuit with respect to a change of a state of the first intermediate-output and a change of a state of the second intermediate-output; and a second adjuster configured to adjust a threshold variation of the differential latch circuit with respect to a change of a state of the first intermediate-output and a change of a state of the second intermediate-output.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: September 16, 2014
    Assignee: Fujitsu Limited
    Inventor: Takumi Danjo
  • Patent number: 8810281
    Abstract: Sense amplifiers including bias circuits are described. Examples include bias circuits having an adjustable width transistor. A loop gain of the bias circuit may be determined in part by the adjustable width of the transistor. Examples of sense amplifiers including amplifier stages configured to bias an input/output node to a reference voltage.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: August 19, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Seong-Hoon Lee
  • Patent number: 8810282
    Abstract: Apparatus and methods for voltage comparison are provided. In one embodiment, a comparator includes a first input transistor having a gate configured to receive a first input voltage and a second input transistor having a gate configured to receive a second input voltage. The first and second input transistors can be used to compare the first input voltage to the second input voltage. Additionally, the comparator further includes a first Miller capacitor electrically connected to a drain of the first input transistor and a second Miller capacitor electrically connected to a drain of the second input transistor. Furthermore, first and second inverting amplification circuits are electrically connected across the first and second Miller capacitors, respectively, so as to increase the effective capacitance of the capacitors. The first and second Miller capacitors can be used to extend the comparator's integration time, thereby enhancing the performance of the comparator.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: August 19, 2014
    Assignee: Analog Devices Inc.
    Inventor: Hongxing Li
  • Patent number: 8742796
    Abstract: Embodiments of the present technology are directed toward circuits for gating pre-charging sense nodes within a flip-flop when an input data signal changes and a clock signal is in a given state. Embodiments of the present technology are further directed toward circuits for maintaining a state of the sense nodes.
    Type: Grant
    Filed: January 18, 2011
    Date of Patent: June 3, 2014
    Assignee: Nvidia Corporation
    Inventors: William Dally, Jonah Alben
  • Patent number: 8705304
    Abstract: Memories, current mode sense amplifiers, and methods for operating the same are disclosed, including a current mode sense amplifier including cross-coupled p-channel transistors and a load circuit coupled to the cross-coupled p-channel transistors. The load circuit is configured to provide a resistance to control at least in part the loop gain of the current mode sense amplifier, the load circuit including at least passive resistance.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: April 22, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Seong-Hoon Lee, Onegyun Na, Jongtae Kwak