Abstract: A constant-current circuit includes a first transistor for supplying a current based on a control signal input to a gate of the first transistor so as to serve as a current source, a second transistor for supplying a current to a load based on the control signal input to a gate of the second transistor, a voltage regulation unit for controlling a drain voltage of the first transistor according to a drain voltage of the second transistor, a current detector for detecting a value of a current flowing through the first transistor and output a current according to the detected value, and a controller for controlling each gate voltage of the first and second transistors according to the value detected by the current detector so that the current flowing through the first transistor becomes a predetermined value. The first and second transistors are MOS transistors having the same conductivity.

Abstract: An improved bias generator incorporates a reference voltage and/or a reference current into the generation of bias voltages. In some cases, the output of a biased delay element has a constant voltage swing. A delay line of such constant output voltage swing delay elements may be shown to provide reduced power consumption compared to some known self-biased delay lines. Furthermore, in other cases, providing the reference current to a novel bias generator allows a delay line of delay elements biased by such a novel bias generator to show reduced sensitivity to operating conditions, reduced sensitivity to variation in process parameters and improved signal quality, thereby providing more robust operation.

Abstract: According to an aspect of the present invention, there is provided a reference voltage generation circuit including: a first transistor having a first gate, a first source and a first drain; a second transistor having a second gate connected to the first gate, a second source connected to the first source and a second drain; a first diode connected between a ground and a V? node; a first resistor connected between the V? node and the first drain; a second diode and a second resistor connected between the ground and a V+ node; a third resistor connected between the V+ node and the first drain; an operational amplifier including input ports connected to the V+ node and the V? node and an output port connected to the first gate and the second gate; and a fourth resistor connected between the ground and the second drain.

Abstract: A semiconductor device, has a main transistor that is a first-conductivity-type MOS transistor and has the drain connected to a first potential; a first switch circuit that is connected between the source of said main transistor and a second potential; a dummy transistor that is a first-conductivity-type MOS transistor whose source serves also as the source of said main transistor; and a second switch circuit that is connected between the drain of said dummy transistor and said first potential or said second potential.

Abstract: A gate-to-source voltage (Vgs) replication circuit includes a diode-connected NMOS transistor coupled to a current source to draw a drain-to-source current therethrough. The generated Vgs is imposed across a source-to-gate junction of a PMOS transistor. A second PMOS transistor is coupled in series with the first PMOS transistor such that the source-to-gate voltage (Vsg) of the second PMOS transistor replicates the Vgs of the NMOS circuit. The second PMOS transistor is coupled as a source follower to bias other NMOS transistors.

Abstract: The application provides a switching circuit for switchably connecting an input node and an output node. The switching circuit comprises a switch operable to switchably connect the input node to the output node in response to a switching signal. A sensor is provided for sensing the voltage between the input and output nodes and providing a sense signal in response thereto. A driver coupled to the sensor adjusts the switching signal in response to the sense signal.

Abstract: Provided is a reference current generating circuit capable of maintaining a constant output level regardless of a temperature variation by the use of a reference resistor having a constant resistance regardless of the temperature variation. The reference current generating circuit includes a reference voltage circuit supplying a reference voltage having a constant level regardless of a temperature variation, and a reference resistor circuit comprising a resistor having a positive temperature coefficient and a resistor having a negative temperature coefficient that are connected in series, the reference resistor circuit having a constant total resistance regardless of the temperature variation. Herein, a reference current having a constant level regardless of the temperature variation is generated by the reference voltage and the resistance of the reference resistor circuit.

Abstract: A system and method for voltage controlled oscillator (VCO) biasing in low voltage circuits including low resistance elements that are especially susceptible to noise. In one embodiment, a poly resistor and triode resistor is used to cancel or offset the effects that temperature variations have on the circuit. The triode resistor is powered by a voltage source that uses a pair of diodes coupled to a constant transconductance (gm) circuit to generate a reduced noise voltage that is independent of the power supply noise. The size of the triode resistor and poly resistors can be varied.

Abstract: A bias control system for the radio frequency power amplifiers that includes a current source, a mirror current, and a bias voltage.

Abstract: A circuit is provided that (in one implementation) includes a first transistor having a first drain terminal, first gate terminal, and a first source terminal. The first drain terminal is connected to the first gate terminal, the first source terminal is connected to a first voltage. The circuit further includes a second transistor having a second drain terminal, second gate terminal, and a second source terminal. The second gate terminal is connected to both the first gate terminal and the first drain terminal, and the second source terminal is connected to the first voltage. The circuit further includes a third transistor having a third drain terminal, a third gate terminal, and a third source terminal. The third drain terminal is connected to the first drain terminal, and the third source terminal is connected to both the third gate terminal and a second voltage that is lower than the first voltage.

Abstract: A DrMOS combines a high side power MOSFET, a low side power MOSFET and a driver circuit for driving the power MOSFETs with current balance and thermal balance mechanism and variable phase control circuit on a single chip.

Abstract: A circuit and method for producing an output voltage that replicates an input voltage. A circuit comprises an amplifier stage configured to amplify a difference between an input voltage and a feedback voltage. An output stage is configured to produce an output voltage equal to the input voltage. The output stage configured to be driven by the difference between the input voltage and the feedback voltage. The output stage further comprises a main supply current path configured to provide a first current from a main supply source, the first current providing at least a portion of the output voltage, and a current management circuit configured to provide a second current from an auxiliary supply source, the second current providing any remaining portion of the output voltage not provided by the first current.

Abstract: The buffer circuit includes a first transistor MP1 having a first end coupled to an output node N2 and a control node coupled to an input node N1; a second transistor MN2 coupled to a second end of the first transistor MP1; a third transistor MN1 coupled to the second transistor MN2 such that a current in the third transistor MN1 is mirrored to the second transistor MN2; a first sense device MP3 coupled to the output node N2; a first current source I2 coupled to the output node N2; a second current source I1 coupled to the third transistor MN1; a second sense device MP2 coupled to the third transistor MN1; and a bipolar device Q1 coupled to the output node N2 and having a base coupled to the second end of the first transistor MP1.

Abstract: A current mirror circuit has a first MOS transistor to which an input current is supplied. The first MOS transistor has a gate formed of polysilicon. A second MOS transistor has a gate formed of polysilicon and connected directly to the gate of the first MOS transistor via a polysilicon layer for producing an output current whose magnitude is a magnitude of the input current multiplied by a current mirror ratio. A fuse has one terminal connected to a gate portion between the gate of the first MOS transistor and the gate of the second MOS transistor and another terminal that is grounded.

Abstract: A current mirror circuit includes a reference current source that generates a reference current, a reference transistor, a mirror transistor and a ratioed body bias feedback unit. The reference transistor has a first node that is coupled to the output of the reference current source, a gate that is coupled to the first node and a second node coupled to a common voltage. The mirror transistor has a gate coupled to the first node. The ratioed body bias feedback unit generates a body bias voltage coupled to the body of the reference transistor and the body of the mirror transistor. The ratioed body bias feedback unit is configured to adjust the body bias voltage in relationship to the common voltage so that the reference transistor and the mirror transistor each have a threshold voltage within a predefined range.

Abstract: A high-voltage tolerant output driver for use in a switching regulator is provided herein. The driver allows the switching regulator to regulate supply voltages that exceed device breakdown limits for the process technology from which the high-voltage tolerant output driver is fabricated. Unregulated supply voltages can vary over a wide range. The regulator only needs two intermediate voltages.

Abstract: An internal voltage detection circuit and an internal voltage generation device using the same are disclosed. The internal voltage detection circuit includes a first detect signal generator for generating a first detect signal to detect a level of an internal voltage corresponding to an operating temperature of a memory cell, a second detect signal generator for generating a second detect signal to detect a specific level of the internal voltage corresponding to a preset temperature, and a detect signal clamp unit for comparing a level of the first detect signal and a level of the second detect signal with each other and clamping the first detect signal according to a result of the comparison.

Abstract: A programmable current generator includes a decoder unit to generate a first and a second set of control signals as a function of a current control word. The current generator further includes a first and a second array of current sources, wherein the current sources of the first array generate a first current and an auxiliary current, each depending on the first set of control signals and on a reference current. The second array of current sources generates a second current depending on a second set of control signals and on the auxiliary current. An output current is generated depending on the first and the second current.

Abstract: A reference voltage generating circuit comprises: a monitor circuit, including a low threshold voltage PMOS transistor, a low threshold voltage NMOS transistor, and a resistor having a predetermined resistance which are connected in series, for generating a reference voltage at one end; and an additional circuit for supplying a monitor current to the monitor circuit and for controlling the other end of the monitor circuit to be at a constant voltage, wherein a voltage value of the reference voltage is corrected within a range corresponding to a process fluctuation from a predetermined center value, based on the monitor current changing in response to the process fluctuation.

Abstract: A system and method is disclosed for providing communication of an over-current protection signal and current mode control signals between a controller chip and a power chip in an integrated circuit device that comprises a plurality of integrated circuit chips. The controller chip sends pulse width modulation signals and a reference current signal to the power chip. Current flow status detection circuitry in the power chip detects a current flow status in the power chip and provides a current flow status signal to the controller chip. The current flow status signal may comprise an over-current protection signal or current mode control signals. One advantageous embodiment of the invention comprises a switch mode power supply integrated circuit.

Abstract: A voltage-insensitive circuit includes a second circuit, and a biasing means for providing a constant bias current to the second circuit, the bias current being insensitive to power fluctuations of the voltage-insensitive circuit.

Abstract: Disclosed is a semiconductor including a component having a drift zone and a drift control zone. A first connection zone is adjacent to the drift zone and is doped more highly than the drift zone. A drift control zone is arranged adjacent to the drift zone and is coupled to the first connection zone. A drift control zone is dielectric arranged between the drift zone and the drift control zone. At least one rectifier element is arranged between the first connection zone and the drift control zone. A charging circuit is connected to the drift control zone.

Abstract: A current mirror circuit includes a first transistor, a plurality of second transistors whose bases are connected to a base of the first transistor, and a compensation transistor having a gate connected to a collector of the first transistor, a source and a back gate connected to the base of the first transistor and the bases of the plurality of second transistors, and a drain connected to a power source. The first transistor and the plurality of second transistors are bipolar transistors. The compensation transistor is a MOS-type transistor. A current corresponding to a current flowing in the first transistor is permitted to flow in the plurality of second transistors.

Abstract: A system includes a bandgap reference voltage circuit, a plurality of trimming resistors, a plurality of trimming switches to connect the bandgap reference voltage circuit to one or more of the plurality of trimming resistors, and an output terminal to connect to at least one of the bandgap reference voltage circuit and the plurality of trimming resistors. The system may provide a trimmed reference voltage independent of at least one of the resistance of any of the plurality of trimming switches and the voltage across any of the plurality of trimming switches.

Abstract: A bias circuit including: a first current source which generates a first current; a second current source which generates a second current having a temperature-to-output current characteristic that an output current characteristic increases or decreases with a change in temperature to intersect with that of the first current; a first current-voltage conversion circuit which converts the first current to a first voltage; a second current-voltage conversion circuit which has an input terminal and converts a current inputted into the input terminal to a second voltage; a comparison circuit which compares the first voltage and the second voltage and generates a third current according to a result of the comparison; an addition unit which adds the third current to the second current and inputs a resulting current to the input terminal; and a voltage-current conversion circuit which converts the second voltage to a fourth current for bias.

Abstract: A gm compensation current source controls current that runs through a current source transistor, source-grounded transistors that determine a gain so that mutual conductance gm of the source-grounded transistors is compensated and the gain is compensated. A 1/r current source runs current inversely proportional to variation of load resistors of an amplifier so that gate bias points of gate-grounded transistors that are connected to the source-grounded transistors remain constant, and deterioration of linearity at a drain terminal of a gate-grounded transistor is suppressed.

Abstract: A limiter circuit includes a differential amplifier circuit having a non-inverting and an inverting inputs, the inverting input fed with an input signal to the limiter circuit, a driving circuit fed with an output of the differential amplifier, a MOS transistor having a source, a drain and a gate, one of the source and the drain of the MOS transistor connected to an output of the driving circuit, the other of the source and the drain of the MOS transistor connected to the non-inverting input of the differential amplifier, the gate of the MOS transistor applied with a predetermined voltage, and a load circuit connected to the other of the source and the drain of the MOS transistor.

Abstract: Controlled voltage circuit for compensating the performance variations in integrate circuits caused by voltage supply, temperature, and process variations is proposed. The controlled voltage circuit includes several MOSFET transistors connected in series, a unity gain operational amplifier, and a constant current source with an input terminal and an output terminal. The input source terminal of the first MOSFET is connected to a constant current source and to the unity gain operational amplifier. The output terminal of the circuit is connected to the CMOS delay block. To compensate for the performance variation, the output voltage node at or before the unity gain operational amplifier is shifted higher as the operating process state is slowed down or as the temperature is increased. Conversely, the output voltage node is shifted lower as the process becomes faster or the temperature is reduced.

Abstract: A device includes an N-channel transistor for output, a voltage raising circuit, a voltage dropping circuit, and an amplifier. A power supply voltage that is a first voltage is supplied to one end of the output N-channel transistor, and the other end of the output N-channel transistor functions as an output terminal. The voltage raising circuit raises the first voltage to generate a second voltage higher than the first voltage. The voltage dropping circuit reduces the second voltage to generate a third voltage that is higher than the first voltage and is lower than the second voltage. The amplifier amplifies the difference between a reference voltage and a voltage generated at the output terminal, using the third voltage as a power supply voltage, to generate a fourth voltage, and supplies the fourth voltage to the gate of the N-channel transistor for output.

Abstract: A leakage current suppressing circuit includes a bias generating unit and a switch unit. The bias generating unit is adapted to be coupled to a power source and an output terminal, and generates a bias voltage substantially equal to a voltage at the power source when the power source is turned on, and substantially equal to a voltage at the output terminal when the power source is turned off. The switch unit includes a first P-type transistor having a first terminal adapted to be coupled to the power source, a second terminal adapted to be coupled to the output terminal, a gate terminal, and a body terminal coupled to the bias generating unit for receiving the bias voltage therefrom.

Abstract: A reference current circuit has an input configured to receive an input current, a first transistor, a second transistor, and an output configured to provide a reference current. The input is directly connected to a control input of the second transistor and a first terminal of the first transistor, and is connected via a first resistor to a control input of the first transistor. The output is connected to a first terminal of the second transistor. A reference node is connected via a second resistor to the control input of the first transistor, directly to a second terminal of the first transistor and via a third resistor to a second terminal of the second transistor.

Abstract: A temperature compensated voltage reference is created from an operational amplifier circuit having two substantially identical P-channel metal oxide semiconductor (P-MOS) transistors with each one having a different gate dopant. The different gate dopants result in different threshold voltages for each of the two otherwise substantially identical P-MOS transistors. The difference between these two threshold voltages is then used to create the voltage reference equal to the difference. The two P-MOS transistors are configured as a differential pair in the operational amplifier circuit and the output of the operational amplifier is used as the voltage reference. The transistor widths of two P-MOS transistors are adjusted to minimize voltage variation over a temperature range.

Abstract: A semiconductor integrated circuit apparatus and an electronic apparatus having a power control function configured from power control MOS transistors such that leakage current and on-resistance at the time of cut-off is sufficiently small in actual use. The semiconductor integrated circuit apparatus includes a CMOS logic circuit, a first pseudo power supply line connected to a high potential side power supply terminal of the CMOS logic circuit, a second pseudo power supply line connected to a low potential side power supply terminal of the CMOS logic circuit, and a power control NchMOS transistor connected across the second pseudo power supply line and a low potential side power supply line, with the substrate and gate of the power control NchMOS transistor being electrically connected. The gate and the substrate may also be connected via a current limiter utilizing a source follower of a depletion type NchMOS transistor.

Abstract: A digital temperature sensing device uses temperature depending characteristic of contact resistance of a MOS transistor and a self-refresh driving device adjusts its self-refresh period depending on temperature using the digital temperature sensing device. The self-refresh driving device includes a first reference voltage generating unit for generating a reference voltage robust to temperature, the first reference voltage generating means being formed with a plurality of MOS transistors, the number of source contacts of the MOS transistors being adjusted such that variation of saturation current through source-drain is compensated for; a second reference voltage generating unit for generating a second reference voltage sensitive to temperature; a level comparator for comparing the first reference voltage with the second reference voltage; and an oscillator for generating a clock signals having differing period depending on the output signal of the level comparator.

Abstract: A reference voltage generation circuit includes: a first field-effect transistor that is an n channel-type field-effect transistor of a depletion-type, wherein one terminal of the first field-effect transistor is connected to a predetermined power source voltage; a second field-effect transistor including a concentrated n-type gate, wherein one terminal of the second field-effect transistor is connected to another terminal of the first field-effect transistor; and a third field-effect transistor including a concentrated p-type gate, wherein one terminal of the third field-effect transistor is connected to another terminal of the second field-effect transistor; wherein a gate of the first field-effect transistor is connected to a part where the first and the second field-effect transistors are connected, each substrate gate of the first and the third field-effect transistors is connected to a ground voltage, a gate and a substrate gate of the second field-effect transistor and a gate of the third field-effect

Abstract: A circuit and a method for extending the lifetime of a semiconductor chip. The circuit including a voltage reference generator, a voltage switch, a threshold voltage regulator device and a threshold voltage monitor device tunes an automatic internal power supply. The voltage reference generator provides one or more reference voltage levels that are transmitted to the voltage switch. The threshold voltage monitor device monitors the threshold voltage of the device, triggering the voltage switch to select a reference level for use as a voltage reference for the regulator when the threshold voltage of the monitored device exceeds a predetermined value. The regulator then converts the external power supply to an internal supply and holds it at the predetermined reference level.

Abstract: Voltage regulator circuitry is provided. The voltage regulator circuitry is suitable for powering core logic on a programmable logic device. The voltage regulator circuitry receives an external power supply voltage and reduces the external power supply voltage to a core power supply voltage if needed. If the external power supply voltage is at the same level needed to power the core logic, the voltage regulator circuitry passes the power supply voltage to the core logic. The voltage regulator circuitry monitors the core power supply voltage using a feedback path. Overshoot and undershoot fluctuations are minimized. The external power supply voltage may be supplied to a first bus. The core power supply voltage may be distributed on a second bus. A ring of transistors may be used to convey power from the first bus to the second bus. Control circuitry may control the ring of transistors based on programmable setpoint voltages.

Abstract: A bias current source generates a constant current Iref by applying to a current-generating resistor a voltage proportional to a thermal voltage Vt. A first bipolar transistor and a second bipolar transistor are disposed in series on the path of the constant current which is generated by the bias current source. A third bipolar transistor forms a current mirror circuit with the second bipolar transistor. A fourth bipolar transistor has a base connected to the base of the first bipolar transistor and has an emitter connected to a temperature-compensating resistor. The constant current circuit outputs a sum of the collector currents of the third bipolar transistor and the fourth bipolar transistor.

Abstract: A power supply voltage controlling circuit has a voltage regulator circuit that supplies a current to an output terminal from at least any of a first power supply and a second power supply, and compares an output voltage at the output terminal with a first reference voltage to adjust the output voltage to approach the first reference voltage; and a controller circuit that supplies the first reference voltage to the voltage regulator circuit and controls the voltage regulator circuit by outputting, to the voltage regulator circuit, at least any of a first enable signal for enabling the first power supply to supply a current to the output terminal and a second enable signal for enabling the second power supply to supply a current to the output terminal.

Abstract: Structures, layouts and methods of forming integrated circuits are described. In various embodiments, the current invention includes an asymmetric segmented transistor. The asymmetric segmented transistor includes a source region and a drain region disposed within an active region, a floating source/drain region disposed within the active region, a first channel region disposed in the active region between the source region and the floating source/drain region, the first channel having a first length and a first width. A second channel region is disposed in the active region between the drain region and the floating source/drain region, the second channel having a second length and a second width. A first gate dielectric overlies the first channel region and a second gate dielectric overlies the second channel region. A gate line overlies the first gate dielectric and the second gate dielectric.

Abstract: Embodiments of the present invention are directed to provide an internal voltage generator of a semiconductor memory device for generating a predetermined stable level of an internal voltage. The semiconductor memory device includes a control signal generator, an internal voltage generator and an internal voltage compensator. The control signal generator generates a reference signal and a compensating signal which are corresponding to voltage level of the reference signal. The internal voltage generator generates an internal voltage in response to the reference signal. The internal voltage compensator compensates the internal voltage in response to the compensating signal.

Abstract: A method is provided for improving the performance of a circuit containing a three-terminal device. In the operation of a circuit containing three-terminal device 10, the influence of the Early effect pertaining to the three-terminal device of a FET is reduced. In order to reduce the influence, control unit 30 is set for reducing the Early effect component caused by a three-terminal device. As a result, by controlling the potential of the second terminal (such as drain) of the device as a response to a first signal pertaining to the input signal received by the first terminal (such as gate) of the device, it is possible for the potential difference between the second terminal (drain) and the third terminal (such as source) of the device to be essentially constant.

Abstract: A method and apparatus is taught for reducing drain-source leakage in MOS circuits. In an exemplary CMOS inverter, a first transistor causes the body of an affected transistor to be at a first body potential. A second transistor brings the body potential of the affected transistor to a second body potential by providing an accurate body voltage from a body voltage source. Exemplary body bias voltage sources are further described that can drive one or more gate transistors of different gate circuits.

Abstract: A first switched capacitor circuit is connected to the source of one MOS transistor of a current mirror pair configured by a pair of MOS transistors and a second switched capacitor circuit is connected to the source of the other MOS transistor. Each of the first and second switched capacitor circuits includes a capacitor and a switch connected in parallel with the capacitor and the switch is on/off-controlled based on a clock signal of a preset cycle. Each of the first and second switched capacitor circuits equivalently functions as a resistor with large resistance and a variation in the output current of the current mirror circuit based on a variation in the threshold voltages of the pair of MOS transistors can be reduced even if the power source voltage is reduced.

Abstract: A CMOS reference current source comprises two circuit branches connected in parallel between supply terminals. The first circuit branch includes a series connection of a bias current source (MP1) and a first MOS transistor (MN1) of a first conductivity type. The second circuit branch includes a series connection of a diode-connected MOS transistor (MP2) of a second conductivity type, a second MOS transistor (MN2) of the first conductivity type and a third MOS transistor (MN3) of the first conductivity type. The first MOS transistor (MN 1) of the first conductivity type has its gate connected to the drain of the third MOS transistor (MN3) of the first conductivity type. The second MOS transistor (MN2) of the first conductivity type has its gate connected to the drain of the first MOS transistor (MN1) of the first conductivity type. The third MOS transistor (MN3) the first conductivity type has its gate connected to a bias source (MN4).

Abstract: A reference current is generated by a current mirror circuit. An operational amplifier of a feedback circuit generates a control voltage for control of the feedback circuit transistor. The size of the feedback circuit transistor is trimmed, and the current through the feedback circuit transistor remains relatively constant via operation of the feedback circuit. The feedback circuit transistor is scaled in size relative to the size of current reference transistor(s) (e.g., current sources or sinks), which are tied to the same control voltage. The reference current of the current reference transistors thus varies with the size of the feedback circuit transistor. Further advantageously, transistors providing reference currents for resistor ladders can also be tied to the same control voltage, but scaled proportionally with changes in size to the feedback circuit transistor, thereby maintaining relatively constant voltage from taps of the resistor ladder, even when the feedback circuit transistor is trimmed.

Abstract: A reference buffer is disclosed. The reference buffer includes a main source follower stage, a replica source follower stage, and a low-pass filter. The main source follower stage provides a first main voltage according to a first driving voltage. The replica source follower stage duplicates the first main voltage to generate a first reference voltage. The low-pass filter is coupled between the main source follower stage and the replica source follower stage.

Abstract: A circuit for generating a reference voltage at an output node comprises a first branch, a second branch, and a main current source. The first branch is electrically connected between a first terminal and a second terminal of the circuit, and comprises at least one first semiconductor device. Each first semiconductor device comprises a first node and a second node. The second branch is electrically connected between the first terminal and the second terminal of the circuit, and comprises at least one second semiconductor device and a branch current source. Each second semiconductor device comprises a first node and a second node. The branch current source is serially connected to the second transistor. The main current source is electrically connected to one of the first terminal and the second terminal of the circuit. The output node is in the first branch or the second branch.

Abstract: In temperature sensing circuitry PTAT (Proportional to Absolute Temperature) Voltage References are typically used. By adding a feedback circuit and a source follower into the classic design, the circuit can guarantee that the current is mirrored identically regardless of the value of power supply voltage. This added circuitry is easy to implement and is low in both power and area. The essence of this invention is that the PTAT circuit allows a large range of operation including low voltage (1 Volt) and more accurate temperature readings.

Abstract: A method for waking up a circuit, comprising charging a voltage line of the circuit with a constant wake-up current until the voltage line reaches a predetermined voltage. Also, an apparatus, comprising a circuit portion, a switch configured to selectively couple an input of the circuit portion to a supply voltage, a current source configured to generate a first current, and a control circuit configured to control a state of the switch depending on the first current.