Abstract: A current source device that cuts off an output current when stopped and obtains a desired output current upon start-up includes a first circuit having a first FET and resistors in series, a second circuit having second and third FETs in series with a point between the second and third FETs and a gate of the third FET connected, a drive circuit supplying a common drive voltage to gates of the first and second FETs, and first and second current source circuits responsive to first and second drive voltages that are gate voltages of the second and third FETs. The first and second current source circuits respectively include first and second current source FETs having the first and second drive voltages as gate voltages, and a start-up circuit changing the first and second drive voltages forcedly when the first and second current source FETs are made conductive.

Abstract: An internal voltage generator of a semiconductor integrated circuit includes a comparison unit configured to compare a reference voltage with a feedback voltage, a driving unit configured to drive an internal voltage terminal in response to an output signal of the comparison unit, and a feedback unit configured to divide a voltage of the internal voltage terminal according to a division ratio adjustable in response to a control signal and output a division voltage as the feedback voltage.

Abstract: A current source generates a reference current. A first transistor is a depletion-type MOSFET arranged such that one terminal thereof is connected to the current source and its gate is connected to its source. A second transistor is an enhancement-type MOSFET arranged such that one terminal thereof is connected to the other terminal of the first transistor, the other terminal thereof is connected to a fixed voltage terminal, and its gate and drain are connected. A third MOSFET is an enhancement-type P-channel MOSFET arranged such that one terminal thereof is connected to the current source, the other terminal thereof is connected to the fixed voltage terminal, and its gate is connected to a connection node connecting the first and second transistors. A constant voltage circuit outputs at least a voltage that corresponds to the gate voltage of the third transistor or a voltage that corresponds to the gate voltage thereof.

Abstract: A current mirror circuit is provided with a first current mirror including first and second mirror transistors sharing a common control terminal; the first mirror transistor has a conduction terminal for receiving, during a first operating condition, a first reference current, and the second mirror transistor has a respective conduction terminal for providing, during the first operating condition, a mirrored current based on the first reference current. The current mirror circuit is provided with a switching stage operable to connect the control terminal to the conduction terminal of the first mirror transistor during the first operating condition, and to disconnect the control terminal from the same conduction terminal of the first mirror transistor, and either letting it substantially float or connecting it to a reference voltage, during a second operating condition, in particular a condition of stand-by.

Abstract: Methods and apparatus relating to very large scale FET arrays for analyte measurements. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes. In one example, chemFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis.

Abstract: Embodiments include a signal generator circuit for generating a time-varying signal, comprising capacitive element; FET to supply to or from the capacitive element a current matched to the FET drain current; a bias voltage generator to provide a bias voltage to the FET gate, wherein: the capacitances per unit area of the capacitive element and the FET gate are matched; the bias voltage is substantially equal to a sum of a first voltage substantially proportional to a reference voltage and a second voltage substantially proportional to temperature; the FET source-gate voltage substantially equal to the sum of the bias voltage and the gate threshold voltage, the bias voltage and a further voltage approximately equal to the gate threshold voltage summed to determine the FET source-gate voltage, the circuit to control a time period of the time-varying signal dependent on the current supply.

Abstract: A reference current generating circuit has: first and second current mirror circuits and first and second output terminals. The first current mirror circuit has: a first transistor of a first polarity being an input-side transistor; and a first resistor connected between a gate of the first transistor and a power supply terminal. The second current mirror circuit has a second transistor of a second polarity being an input-side transistor. An output node of the first current mirror circuit is connected to an input node of the second current mirror circuit, and an input node of the first current mirror circuit is connected to an output node of the second current mirror circuit. A control voltage applied to the gate of the first transistor is output from the first output terminal. A control voltage applied to a gate of the second transistor is output from the second output terminal.

Abstract: A leakage current control circuit includes a solid state switch that is operable to control a flow of AC to a load. The switch exhibits an AC leakage current in an OFF state. A capacitor is connected in parallel to the load, and is operable to repeatedly charge during a first half cycle of the leakage current and to discharge during a second half cycle of the leakage current. The capacitor charge includes a DC component in response to the leakage current through the solid state switch being greater in a first direction than in a second direction opposite the first direction. A first resistor is connected in parallel to the load. The capacitor and the first resistor prevent a voltage buildup across the load from exceeding a voltage threshold.

Abstract: Methods and apparatus for capacitive voltage division are provided, an example apparatus having an input and an output and including a first switched capacitor circuit. In some embodiments, the capacitive voltage divider includes first and second MOSFETs. A first capacitor is coupled between the drain of the first MOSFET and the input to the capacitive voltage divider. A first circuit coupled to the drain of the first MOSFET is configured to pull down the drain of the first MOSFET and thus apply a reverse bias to a first junction diode internal to the first MOSFET between the drain and the bulk of the first MOSFET. A second capacitor is coupled between the source of the first MOSFET and the drain of the second MOSFET. A second circuit is configured to reverse bias a second junction diode between the drain and bulk of the second MOSFET.

Abstract: These various embodiments pertain to an FET having a plurality of fingers as correspond to the FET's source and drain. A first conductive lead electrically couples to a given one of this plurality of fingers while a second conductive lead electrically couples as well to this same given finger. A measurement component connects to these first and second conductive leads to measure at least one electrical parameter (such as voltage). By one approach, the first and second conductive leads physically connect to opposing ends of the given finger. These teachings will also accommodate providing a control component that is responsive to the measurement component to facilitate automatically controlling at least one operating state of the FET as a function, at least in part, of the measured electrical parameter.

Abstract: An impedance transformation circuit utilizes two transistor circuits.

Abstract: Some embodiments regard a circuit comprising: a high voltage transistor providing a resistance; an amplifier configured to receive a current and to convert the current to a first voltage that is used in a loop creating the current; and an automatic level control circuit that, based on an AC amplitude of the first voltage, adjusts a second voltage at a gate of the high voltage transistor and thereby adjusts the resistance and the first voltage; wherein the automatic level control circuit is configured to adjust the first voltage toward the first reference voltage if the first voltage differs from a first reference voltage.

Abstract: A feedback mechanism to reduce current variation observed in a current reference branch circuit by using body voltage control to compensate process, temperature and supply voltage variations. The current reference output voltage, which is proportional to the reference current, is sampled into a feedback loop, which controls the field effect transistor body voltage. The method and mechanism uses Corner Robust Current Reference in order to keep the design simple and diminish variation between Process Voltage Temperature (PVT) corners. This method exhibits small variation in the reference current magnitude.

Abstract: First and second envelope detector circuits have, respectively, a resistance row, a capacitative element connected to the resistance row in parallel and a transistor connected between a connection point between the resistance row and the capacitative element and a predetermined voltage node. An output of a level shifter is supplied to a gate or a base of the transistor of the first envelope detector circuit. A predetermined voltage is supplied to a gate or a base of the transistor of the second envelope detector circuit. A detector detects an intermediate terminal voltage of the resistance row of the first envelope detector circuit with reference to a total voltage or an intermediate terminal voltage of the resistance row of the second envelope detector circuit.

Abstract: In an embodiment, a circuit includes a first transistor having a first current electrode, a control electrode, and a second current electrode coupled to a power supply terminal. The circuit further includes a resistive element having a first terminal coupled to the control electrode of the first transistor and a second terminal coupled to the power supply terminal. The circuit also includes a feedback circuit for providing a first current to the first control electrode of the first transistor and for preserving substantially the first current related to a voltage at the control electrode of the first transistor, through the resistive element. The feedback circuit includes an output terminal for providing an output signal in response to a voltage at the control electrode of the first transistor. In an embodiment, the first transistor is a floating-gate device with programmable threshold voltage.

Abstract: In a semiconductor integrated circuit device, a circuit block has a first MOS transistor, and a leakage current control circuit having a second MOS transistor and a current source, a source and drain circuit of the second MOS transistor is formed between the power supply line of the circuit block and a voltage point where operating voltage is supplied. This current source is connected to the power supply line and in a first state, the power supply line is driven to a first voltage by the second MOS transistor. In a second state, the power supply line is controlled at a second voltage by current flow in the current source and, the voltage applied across the source and drain of the first MOS transistor in the second state is smaller than the voltage applied across the source and drain of the first MOS transistor in the first state.

Abstract: An input voltage signal VIN to be inputted to a gate terminal of a PMOS transistor M1 is converted to a voltage value which was level shifted at the source terminal by an inter-terminal voltage between the gate and source of the PMOS transistor M1. This conversion is carried out in accordance with a bias current I1 flowing from the constant current source IS through the source terminal of the PMOS transistor M1. The voltage thus converted is outputted from a source follower circuit through a capacitative element C1. A low-pass filter is constituted of the impedance of the PMOS transistor M1 and the capacitative element C1 in a signal path extending from the input voltage signal VIN to the source follower circuit.

Abstract: Embodiments of the present invention are directed to provide an internal voltage generator of a semiconductor memory device for generating a predetermined stable level of an internal voltage. The semiconductor memory device includes a control signal generator, an internal voltage generator and an internal voltage compensator. The control signal generator generates a reference signal and a compensating signal which are corresponding to voltage level of the reference signal. The internal voltage generator generates an internal voltage in response to the reference signal. The internal voltage compensator compensates the internal voltage in response to the compensating signal.

Abstract: A voltage stabilization circuit of a semiconductor memory apparatus includes an operation speed detecting unit configured to detect an operation speed of the semiconductor memory apparatus to generate a detection signal, and a voltage line controlling unit configured to interconnect a first voltage line and a second voltage line in response to the detection signal.

Abstract: A reference voltage generating circuit for generating a reference voltage includes MOSFETs connected to each other. At least one of the MOSFETs includes a control gate and a floating gate that is made hole-rich or discharged by ultraviolet irradiation, and the reference voltage generating circuit is configured to output the difference between threshold voltages of a pair of the MOSFETs as the reference voltage.

Abstract: A linear relationship is established between a gain control signal and an amplification factor (value in dB). Described is a current generation circuit including a first current output section which outputs a first current, a second current output section which outputs a second current proportional to the first current, and a variable-current control section which generates a third current proportional to the first current, divides the third current into a fourth current and a fifth current according to a first control signal, and outputs the fourth and the fifth currents. The current generation circuit outputs a sum of the first and the fourth currents as a reference current, and a sum of the second and the fifth currents as an output current.

Abstract: Embodiments of the invention describe a core circuit for a reference current generator circuit that biases a first transistor to source a first current and a second transistor parallel to the first transistor, biased to source a second current controlled by the first current. A third transistor is coupled parallel to the second transistor and sources a third current controlled by the first current. The third transistor has a different threshold voltage than a threshold voltage of the second transistor. A resistive component coupled to conduct the second current has a resistive voltage that is substantially equal to a voltage differential between the first transistor and the second transistor. The conducting current through the resistive component is substantially independent of temperature variations.

Abstract: The present invention provides a regulator circuit that can fast-respond to a variation in load current and supply a sufficient drive current so as to be capable of generating a stable internal source voltage. The regulator circuit includes a preamplifier circuit that detects and amplifies a different between a reference voltage and an internal source voltage, a clamp circuit that limits the amplitude of an output of the preamplifier circuit, a main amplifier circuit that amplifies the amplitude-limited output of the preamplifier circuit, and a driver circuit that outputs the internal source voltage according to the output of the main amplifier. Even though the internal source voltage varies abruptly, the regulator circuit does not oscillate owing to the effect of the clamp circuit.

Abstract: An improved bias generator incorporates a reference voltage and/or a reference current into the generation of bias voltages. In some cases, the output of a biased delay element has a constant voltage swing. A delay line of such constant output voltage swing delay elements may be shown to provide reduced power consumption compared to some known self-biased delay lines. Furthermore, in other cases, providing the reference current to a novel bias generator allows a delay line of delay elements biased by such a novel bias generator to show reduced sensitivity to operating conditions, reduced sensitivity to variation in process parameters and improved signal quality, thereby providing more robust operation.

Abstract: A microprocessor according to one embodiment includes a supply node providing a core voltage, a functional block, a charge node, select logic, and substrate bias logic. The functional block has multiple power modes and includes one or more semiconductor devices and a substrate bias rail routed within the functional block and coupled to a substrate connection of at least one semiconductor device. The select logic couples the substrate bias rail to the charge node when the functional block is in a low power mode and clamps the substrate bias rail to the supply node when the functional block is in a full power mode. The substrate bias logic charges the charge node to a bias voltage at an offset voltage relative to the core voltage when the functional block is in the low power mode. Semiconductor devices may be provided to clamp or otherwise couple the bias rail.

Abstract: A power supply control circuit comprises an output transistor 32 which controls supply of electric power to a load and a gate driving circuit which generates control signals “a” and “b” for controlling on/off of the output transistor based on an external input signal. A first discharge path includes a first depletion-type N-channel MOS transistor provided between a gate and a source of the output transistor and discharges a gate charge of the output transistor based on the control signals, when turning off the output transistor. A second discharge path includes a first depletion-type N-channel MOS transistor discharges more slowly than the first discharge path. A diode is coupled to the first depletion-type N-channel MOS transistor in series and detects that a gate voltage of the output transistor has fallen to a prescribed voltage level, and cuts off a first discharge path.

Abstract: An internal voltage generation circuit includes a first voltage generation unit configured to be operated in response to a first power enable signal to generate a first voltage, a level detection unit configured to detect a level of the first voltage, and a second voltage generation unit configured to be operated in response to a level detection value outputted from the level detection unit to generate a second voltage lower than the first voltage.

Abstract: Embodiments of the invention describe a core circuit for a reference current generator circuit that biases a first transistor to source a first current and a second transistor parallel to the first transistor, biased to source a second current controlled by the first current. A third transistor is coupled parallel to the second transistor and sources a third current controlled by the first current. The third transistor has a different threshold voltage than a threshold voltage of the second transistor. A resistive component coupled to conduct the second current has a resistive voltage that is substantially equal to a voltage differential between the first transistor and the second transistor. The conducting current through the resistive component is substantially independent of temperature variations.

Abstract: A circuit for generating a reference electrical quantity, including: a first bipolar transistor and a second bipolar transistor having the base terminals connected to one another and to a common node; a first resistor connected to the emitter terminal of the second bipolar transistor; a first mirror circuit and a second mirror circuit connected to the first and second bipolar transistors, which receive, respectively, a first current and a second current and generate, respectively, a first mirrored current and a second mirrored current; a first output stage, which generates the reference electrical quantity as a function of the first and second mirrored currents; and a second resistor connected to the common node. The first current is a function of the current in the first resistor, whilst the second current is a function of the current in the second resistor.

Abstract: An internal voltage generator includes: a detection unit configured to detect a level of an internal voltage in comparison to a reference voltage; a first driving unit configured to discharge an internal voltage terminal, through which the internal voltage is outputted, in response to an output signal of the detection unit; a current detection unit configured to detect a discharge current flowing through the first driving unit; and a second driving unit configured to charge the internal voltage terminal in response to an output signal of the current detection unit.

Abstract: An electronic control module for a field effect transistor includes a gate, a drain and a source. The electronic control module includes: a control circuit including: a power supply able to provide a fixed potential to the gate of the field effect transistor; and an amplifier stage able to vary the potential of the source of the field effect transistor with relation to the potential of the gate of the field effect transistor; and a field effect transistor whose gate is connected to the fixed potential; and source is connected to the amplifier stage.

Abstract: A bias current is generated for an unbalanced differential pair that is proportional to the transconductance gain of the differential pair. When the transconductance gain varies (e.g., due to temperature variations), the bias current varies in proportion thereby maintaining a constant offset voltage. In some implementations, a voltage to current converter circuit generates the bias current from a constant reference voltage that is independent of temperature and voltage supply variations (e.g., a bandgap reference voltage).

Abstract: Disclosed are a high voltage pumping circuit and a VPP pumping method using the same. The high voltage pumping circuit includes an initializing unit for initializing a high voltage in response to a first enable signal, a first pump for pumping the high voltage in response to the first enable signal, a second pump for pumping the high voltage in response to a second enable signal and a first mode signal, and a mode signal transmitting unit for generating a second mode signal in response to the second enable signal and the first mode signal. The driving of the initializing unit and the first pump is controlled in response to the first pump and the second mode signal.

Abstract: A CMOS bias circuit includes a starter circuits and a started circuit part which supplies a current to the outside. The starter circuits has a connection node (first terminal) between it and the started circuit part. The starter circuits includes a first MOS transistor connected at its drain to the first terminal, a first current supply circuit which supplies a starter current to the started circuit via the first MOS transistor, and a circuit which supplies a second current in a direction that interrupts a current flowing through the first MOS transistor to a node between the first MOS transistor and the first current supply circuit in accordance with a potential at the first terminal. The starter circuits has a function of preventing a current flowing between the drain and source of the first MOS transistor in the opposite direction by increasing or decreasing a gate bias of the first MOS transistor in accordance with a value of the second current.

Abstract: A multi-channel current driver is provided. One of the channels includes a channel switch and a memory-type current mirror. A first end of the channel switch receives a reference current. A master current end of the memory-type current mirror is coupled to a second end of the channel switch. Wherein, a slave current end of the memory-type current mirror outputs a driving current according to the reference current when the channel switch provides the reference current to the memory-type current mirror, and the slave current end of the memory-type current mirror holds the driving current when the channel switch stops the reference current.

Abstract: In many applications, “dying gasp” periods following power down are used. Conventional circuits supply energy for the “dying gasp” periods generally by use of large external capacitors that are bulky and expensive. Here, a dying gasp charge controller is employed that allows for the use of smaller capacitors at higher voltages, which maintains or exceeds the energy storage capacities of conventional circuits.

Abstract: An internal voltage generating circuit includes an internal voltage generating unit configured to generate an internal voltage that corresponds to a target voltage level by driving an internal voltage terminal with an external power supply voltage, and current sinking unit configured to adjust leakage current introduced to the internal voltage terminal in response to the external power supply voltage.

Abstract: A method and circuit for providing a bias voltage to a MOS device is disclosed. The method and circuit comprise utilizing at least one diode connected circuit to provide a voltage that tracks process, voltage and temperature variations of a semiconductor device. The method and circuit includes utilizing a current mirror circuit coupled to the at least one diode connected circuit to generate a bias voltage for the body of the semiconductor device from the voltage. The bias voltage allows for compensation for the process, voltage and temperature variations.

Abstract: Described embodiments provide for protecting from DC and transient over-voltage conditions an input/output (“I/O”) buffer having first and second I/O transistors. The first I/O transistor is coupled to a first over-voltage protection circuit adapted to prevent an over-voltage condition on at least the first I/O transistor. The second I/O transistor is coupled to a second over-voltage protection circuit adapted to prevent an over-voltage condition on at least the second I/O transistor. First and second bias voltages are generated from an operating voltage of the buffer. A third bias voltage is generated from either i) the first bias voltage, or ii) an output signal voltage of the buffer and a fourth bias voltage is generated from either i) the second bias voltage, or ii) the output signal voltage of the buffer. The third and fourth bias voltages are provided to the first and second over-voltage protection circuits, respectively.

Abstract: In a cascode current-mirror circuit which reproduces a reference current generated by a current source and outputs the reproduced reference current: the control electrodes of first and second transistors are connected; a third transistor is cascode-connected to the first transistor through a current electrode; a fourth transistor is cascode-connected to the second transistor; the control electrodes of the third and fourth transistors are connected; the control electrode of a fifth transistor is connected to the control electrode of the first transistor and another current electrode of the third transistor, and is to be connected to the current source; and a bias-voltage generation circuit generates bias voltages for the third and fourth transistors on the basis of voltages of the control electrodes of the first and the fifth transistors.

Abstract: A reference buffer circuit with high driving capability is disclosed. In which, a buffering stage has a first NMOS transistor and a first PMOS transistor to provide high and low tracking voltages respectively based on a high input voltage and a low input voltage. A first driving stage is driven by the high and low tracking voltages to output a first high output voltage and a first low output voltage. A body of the first PMOS transistor is tied to a first bias voltage lower than a supply voltage for the buffering and first driving stages.

Abstract: A microprocessor including a substrate bias rail providing a bias voltage during a first operating mode, a supply node providing a core voltage, a clamp device coupled between the bias rail and the supply node, and control logic. The control logic turns on the clamp device to clamp the bias rail to the supply node during a second operating mode and turns off the clamp device during the first operating mode. The clamp devices may be implemented with P-channel and N-channel devices. Level shift and buffer circuits may be provided to control the clamp devices based on substrate bias voltage levels. The microprocessor may include a substrate with first and second areas each including separate substrate bias rails. The control logic separately turns on and off clamp devices to selectively clamp the substrate bias rails in the first and second areas based on various power modes.

Abstract: A suite of novel structures and methods is provided to reduce power consumption in a wide array of electronic devices and systems. Some of these structures and methods can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. As will be discussed, some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors.

Abstract: A dormant mode target semiconductor device within a leakage current target unit is identified for mitigating leakage current to prevent it from reaching catastrophic runaway. A leakage current shift monitor unit is electrically connected to the output node of the leakage current target unit and collects leakage current from the selected target semiconductor device for two consecutive predefined temporal periods and measures the difference between the collected leakage currents. A comparator receives and compares the outputs of the current shift monitor unit and a reference voltage generator. The comparator propagates an alert signal to the leakage current target unit when the leakage voltage output from the leakage current shift monitor unit exceeds the reference voltage, a condition that indicates that the leakage current is about to approach catastrophic runaway levels.

Abstract: A high linearity voltage-current converter able to compensate for mobility degradation comprises a first constant current source circuit, a first current mirror unit, a second constant current source circuit, a second current mirror unit, a seventh MOS transistor and an eighth MOS transistor. The first current mirror unit is coupled to the first constant current source circuit, and the second current mirror unit is coupled to the second constant current source circuit. The seventh MOS transistor, the first current mirror unit and the second current mirror unit are coupled to each other at a third joint point of a first conducting wire. The eighth MOS transistor is coupled to the seventh MOS transistor. Thereby, the electronic components used in the present invention can operate more efficiently.

Abstract: A circuit adapting pin output levels to a reference level in which a digital comparator compares an output voltage from an output pin of a device to a reference voltage level. The comparator, relying on the polarity of the comparator output as well as the registered polarity of the comparator output on the previous clock cycle, signals a state machine, which sends a clocked signal to a sense circuit and voltage regulator. The sense circuit may modify a resistance in a switched resistor network, such that the output level is incrementally stepped at clocked intervals towards the reference voltage until the polarity of the error signal reverses. When the output voltage crosses the reference voltage threshold, the comparator flips states and continues to regulate output pin voltage to the reference voltage level.

Abstract: A differential current-mode sigma-delta digital-to-analog converter (SD DAC) and a method for generating positive and negative reference voltages in a sigma-delta digital analog converter are described. The SD DAC includes a low pass filter (LPF) having a first and second input. The SD DAC further includes a first resistance and a second resistance coupled together at a common node. The first resistance may be coupled to the first input of the LPF and the second resistance may be coupled to the second input of the LPF. Additionally, the SD DAC includes a current supply and a switching network for supplying current from the current supply to the first and second resistances. The current supply and the resistances operate to generate a first voltage and a second voltage at the first and second inputs of the LPF.

Abstract: A high voltage current source and a voltage expander implemented in a low voltage semiconductor process. The voltage expander extends the operating voltage range of a stack of transistors to multiple times a supply voltage Vdd at the output node of the stack without exceeding the breakdown voltage of any of the transistors in the stack. The voltage expander uses a diode and a voltage divider to detect the output node voltage changes and generates a plurality of voltages that control the gate voltages for the stack of transistors. A high voltage wide swing current source utilizes a transistor to set the output current and the voltage expander to extend the output voltage range of the current setting transistor. An additional transistor and another current source ensure that the output current is constant throughout the entire output voltage range between about 0 V and multiple times the supply voltage Vdd.

Abstract: A driver is provided. The driver generally comprises a current source, a current mirror, an amplifier and a presetting circuit. The current source is generally adapted to provide a reference current to the current mirror. The transistor is coupled to the current mirror. The amplifier has the first input that is coupled to the current mirror, a second input that is coupled to a node between the transistor and the current mirror, and an output that is coupled to the control electrode of the transistor. The presetting circuit is coupled to the control electrode of the transistor so that it can preset the potential of the control electrode of the transistor to a potential that allows current driving of the transistor with a predetermined timing after a control signal is received.

Abstract: A voltage level shifting circuit (FIG. 4) has a plurality of PMOS transistors M1, M2, M3 connected in parallel for respectively driving a capacitive load CL with a selected different voltage level V1, V2 or V3. Transistors M1, M2, M3 are controlled so that one of them is placed in the ON condition, with the others in the OFF condition, to connect one of the voltages V1, V2 or V3 to charge the load CL. The largest voltage transistor M3 has its body connected to its source. The lower voltage transistors M1, M2 have their bodies respectively connected to switches S1, S2, which connect the bodies to the sources when the transistors are placed in the ON condition and connect the bodies to the highest voltage V3 when the transistors are placed in the OFF condition.