Abstract: A flow-volume detecting apparatus including a flow-volume detecting unit which measures a flow volume of a measured fluid, a flow-volume state determining unit which determines a flow-volume state of the measured fluid based on an output from the flow-volume detecting unit. The flow-volume detecting apparatus further including a plurality of filters which process a flow-volume signal, and a filter selecting unit which selects a filter that processes the flow-volume signal, wherein the filter selecting unit selects the filter that processes the flow-volume signal according to the flow-volume state determined by the flow-volume state determining unit.

Abstract: Provided is a current-to-voltage converter for converting a current signal into a voltage signal. The current-to-voltage converter may include: a trans-impedance amplifier including an input terminal and an output terminal; a resistor-capacitor (RC) circuit including a first end and a second end respectively connected to the input terminal and the output terminal of the trans-impedance amplifier, and a resistor and a capacitor connected to each other in parallel between the first end and the second end; and a plurality of switches configured to form at least one of a first converting circuit configured to convert the current signal via the trans-impedance amplifier and the RC circuit in a wide bandwidth mode, and a second converting circuit configured to convert the current signal via the RC circuit in a narrow bandwidth mode.

Abstract: A radio frequency tissue ablation system with a radio frequency generator, the generator comprising a radio frequency source, at least four independently controllable radio frequency outputs, a user interface and a controller configured to delivery radio frequency energy from the radio frequency source to the radio frequency outputs in one of at least two different output configurations in response to a configuration selection made through the user.

Abstract: A delay compensated comparator circuit is disclosed. The circuit includes an amplifier circuit having a first input terminal coupled to receive a reference signal and having a second input terminal and a first output terminal. A capacitor is arranged to couple an input signal to the second input terminal. A resistor is coupled between the first output terminal and the second input terminal. A comparator circuit has a third input terminal coupled to receive the input signal, a fourth input terminal coupled to the first output terminal, and a second output terminal.

Abstract: Methods and digital circuits providing frequency correction to frequency synthesizers are disclosed. An FLL digital circuit is provided that is configured to handle a reference frequency that is dynamic and ranges over a multi-decade range of frequencies. The FLL circuit includes a digital frequency iteration engine that allows for detection of disappearance of a reference frequency. When the digital frequency iteration engine detects that the reference frequency signal is not available, the oscillator generated frequency is not corrected, and the last value of the oscillator generated frequency is held until the reference frequency signal becomes available again. This FLL circuit is also preceded by a low-pass filter which is dynamically tuned to the frequency to which the FLL locks, eliminating harmonic components in the original signal which might otherwise cause errors in frequency estimation.

Abstract: A waveform shaping filter according to one embodiment includes a first resistor, a first transistor, a first capacitor, and a first amplifier. The first resistor includes one end to which a signal current is input and the other end. The first transistor includes a first terminal connected to the other end of the first resistor, a second terminal, and a control terminal. The first capacitor includes one end connected to the other end of the first resistor and the other end. The first amplifier includes an input terminal connected to the one end of the first resistor and an output terminal connected to the control terminal of the first transistor.

Abstract: An optical communication system, a circuit, and a method of operating an optical communication system are provided. The optical communication system is disclosed to include a photodiode configured to receive optical signals and convert the received optical signals into electrical signals, a Trans-Impedance Amplifier (TIA) electrically connected with the photodiode such that the TIA receives the electrical signals from the photodiode and is configured to convert the electrical signals received from the photodiode into amplified electrical signals, and a feedback loop connected between an input of the TIA and an output of the TIA that includes a switchable capacitor bank connected thereto which introduces at least one zero into a feedback factor transfer function of the TIA thereby tuning out poles or equalizing delay introduced by a TIA input network connected between the photodiode and the input of the TIA.

Abstract: A switched-mode power supply unit for a computer includes at least one switching element that switches a charging current to charge a storage element, at least one secondary output circuit that provides an output voltage (Vout+), at least one controllable oscillator circuit that provides a switching clock, and at least one control circuit that determines a switch-off time for the at least one switching element, wherein, in operation of the switched-mode power supply unit, a mean oscillator clock of the oscillator circuit is controlled in dependence on a controlled variable (Vcontrol) specifying the output voltage or power of the secondary output circuit such that the mean oscillator clock rises monotonously with the output power and a switch-on time for the at least one switching element is determined in dependence on the mean oscillator clock and a random deviation.

Abstract: Techniques for designing baseband processing circuitry for radio IC's. In an aspect, techniques for differential-to-single-ended conversion in a baseband portion of the IC are disclosed to reduce the pin count and package size for RF IC's. In another aspect, the converter includes selectable narrowband and wideband amplifiers, wherein the wideband amplifiers may be implemented using transistor devices having smaller area than corresponding transistor devices of narrowband amplifiers. Further techniques for bypassing one or more elements, and for implementing a low-pass filter of the converter using an R-C filter network, are described.

Abstract: A clock generator is disclosed for use with an oscillator device. The clock generator may include a signal conditioning pre-filter and a comparator. The signal conditioner may have an input for a signal from the oscillator device, and may include a high pass filter component and a low pass filter component. The high pass filter component may pass amplitude and frequency components of the input oscillator signal but reject a common mode component of the oscillator signal. Instead, the high pass filter component further may generate its own common mode component locally over which the high frequency components are superimposed. The low pass filter component may generate a second output signal that represents the locally-generated common mode component of the first output signal. The clock generator may have a comparator as an input stage which is coupled to first and second outputs of the filter structure.

Abstract: A method and apparatus for an adjustable filter system comprises a first integrated circuit generating a reference value that represents a corner frequency of a filter within the first integrated circuit; sending the reference value that represents the corner frequency of the filter across an interface to a second integrated circuit; receiving, across the interface from the second integrated circuit, a filter adjustment value; and changing the corner frequency of the filter using the filter adjustment value to adjust a passband and a stopband of the filter. The apparatus and method also comprises a second integrated circuit detecting a filter adjustment event, wherein the filter adjustment event comprises receipt of the reference value; calculating the filter adjustment value to change a corner frequency of the filter within a first integrated circuit; and sending the filter adjustment value across the interface to the first integrated circuit.

Abstract: A receiver includes an antenna interface, a frequency translation bandpass filter (FTBPF), a sample and hold module, and a down conversion module. The antenna interface is operable to receive a received wireless signal from an antenna structure and to isolate the received wireless signal from another wireless signal. The FTBPF is operable to filter the received wireless signal to produce an inbound wireless signal. The sample and hold module is operable to sample and hold the inbound wireless signal in accordance with an S&H clock signal to produce a frequency domain sample pulse train. The down conversion module is operable to convert the frequency domain sample pulse train into an inbound baseband signal.

Abstract: An RF signal reception device including: a transposition device of signals of frequency fRF to a first intermediate frequency IF1<fRF; a first bandpass filter centered on IF1; a sampler at a frequency fs<IF1; a second discrete-time filter centered on a second intermediate frequency IF2=?·fs/M+fs/(M·n); a decimation device of a factor M; an analog-digital convertor to operate at a frequency fs/M; where ?, n and M are strictly positive real numbers chosen such that: ?<fs/(2·BWch·M), and BWch/2<fs/M·n), with BWch: bandwidth of a channel of the received RF signals.

Abstract: One embodiment of an apparatus for cancelling supply noise includes an input circuit operable to receive an input from a charge pump and a drive circuit connected to an output of the input circuit. The drive circuit is operable to provide an output matching the input to the input circuit when a voltage source powering the input circuit and the drive circuit is stable, and to introduce a contrary voltage change on the buffered output when the voltage source is noisy, with the contrary voltage change being contrary to a voltage change on the voltage source due to noise.

Abstract: A filtering device, applicable in a transceiver, includes: a capacitive circuit coupled to an amplifying circuit by a first capacitive configuration or by a second capacitive configuration; and a resistive circuit coupled to the amplifying circuit by a first resistive configuration or by a second resistive configuration; wherein when the capacitive circuit is the first capacitive configuration, the filtering device is used to perform a first filtering process upon a receiving signal of the filtering device, and when the capacitive circuit is the second capacitive configuration, the filtering device is used to perform a second filtering process upon a transmitting signal of the filtering device.

Abstract: In one embodiment, a set of tracking filters to be coupled between an amplifier and a mixer is provided. The tracking filters may be differently configured depending on band of operation. For example, a first set of the filters can be configured to maintain a substantially constant Q value across their operating bandwidth while a second set of the filters can be configured to maintain a substantially constant bandwidth across their operating bandwidth.

Abstract: A relaxation oscillator for generating a first and a second oscillation signals, comprising: a reference-voltage providing circuit for providing a high and a low reference voltages; switches for directing the high and low reference voltages to inputs of a transconductance amplifier and a non-inverting input of a comparator; the transconductance amplifier for generating an output current with a value determined by its transconductance value, controlled by an input tuning voltage, and multiplied by its inputs' voltage difference; a capacitor connecting between the transconductance amplifier output and ground; and the comparator for generating a first and a second digital signals; wherein the first and second digital signals are digital control signals to the switches, and the first and second oscillation signal of the relaxation oscillator respectively; wherein the oscillation frequency of the relaxation oscillator is independent of the reference voltages, achieving accurate frequency turning, and simplifying t

Abstract: There is provided with a filter circuit, including: an input terminal configured to input signals; a band stop filter configured to have a center frequency of input signals from the input terminal in a stop band and configured to reflect signals in the stop band that is included in the input signals and pass signals outside the stop band; a band pass filter configured to have a pass band including the stop band, and configured to pass signals in the pass band out of the signals having passed through the band stop filter; a synthesis circuit configured to synthesize the signals reflected on the band stop filter and the signals having passed through the band pass filter to obtain synthesis signals; and an output terminal configured to output the synthesis signals.

Abstract: The joint (36) comprises a tubular body (37) having two connecting zones (38, 39) each connected by an end to a tubular element (40) of a fluid transport line, giving continuity to passage of fluid. The tubular body is made of a mixture of an electrically-conductive material such as PVC, with carbon black to give it electrical conductivity. The joint has an internal surface (41) which is destined to come into contact with the transported fluid, and an external surface which is destined to have a grounded galvanic contact. The joint is inserted in the discharge fluid drainage line of a dialyzer filter, in an apparatus for intensive treatment of acute renal insufficiency, for eliminating ECG artefacts due to functioning of peristaltic pumps in the apparatus.

Abstract: The present invention provides an equalizer and a semiconductor device, that can suppress a decrease in S/N ratio of a reception signal, can facilitate a disconnection test by a direct current signal, and are excellent in reproducibility of a transmission signal. A low-pass filter receives a reception signal supplied from a reception end to output a signal obtained by removing a high frequency component from the reception signal. A subtraction unit subtracts an output signal from the low-pass filter from the reception signal. An addition unit adds the reception signal from the reception end to an output signal from the subtraction unit. Thus, an output signal from the addition unit has a frequency characteristic of emphasizing the high frequency component. Then, an amplifier amplifies the output signal from the addition unit to transmit it to an output end.

Abstract: A pseudo-image signal producing section produces a pseudo-image signal imitating an actual image signal. An amplitude detection section detects the amplitude of the pseudo-image signal having passed through a complex filter circuit. A filter control section controls an element value control section in the complex filter circuit so as to decrease the detected amplitude. The element value control section performs an element value adjustment so that absolute element values of a pair of elements corresponding to each other in two filter circuits in the complex filter circuit increase/decrease in opposite directions.

Abstract: A transconductance filtering device with a flexible architecture that can selectively present a different topology and/or order beginning with the same initial structure is disclosed. For example, depending on the communications standard detected, the elementary cells of the filtering circuit required to form the adapted filter are selected and connected in such a manner as to obtain the configuration desired for the filtering means. As an example, the filter may be for use with a wireless communications system forming, in particular, a cellular mobile telephone. The filter is configurable by means of at least two elementary cells of the same structure and of controllable interconnection means each having an open or closed state.

Abstract: Control system for programmable filters, master-slave calibration system and fully programmable high precision filter for use in such control system, such filters being provided with a filter input and a filter output including a first, first order low pass filter section comprising first and second mutually identical operational transconductance amplifiers (OTAs), having a controllable transconductance Gm from a differential voltage input having first and second differential voltage input terminals to a single current output carrying a single phase current output signals, said first and second OTAs being provided with first and second control inputs, respectively, said filter input being coupled to the first differential voltage input terminal of said first OTA.

Abstract: A system which provides frequency conversion and continuously variable bandwidth control is implemented using first and second filter networks that exhibit a generalised Chebyshev transfer function. The first and second filter networks may comprise a pseudo-high-pass type filter in combination with a pseudo-low-pass type filter, or in a particularly efficient embodiment, a pseudo-high-pass type filter in combination with an elliptic low pass type filter. The effective frequency response overlap of first and second filter networks produces a composite band-pass filter response which is highly selective by nature and is determined only by the steep band edge transition region of the individual filter networks. The maximum pass-band of the first and second filter networks can be tailored to precisely fit the maximum band-pass bandwidth required by a channelised radio communications system.

Abstract: A tunable band pass filter is provided. The tunable band pass filter includes a band pass filter and a plurality of switches coupled to the band pass filter. The band pass filter includes a plurality of transconductors and a plurality of capacitors. The tunable band pass filter can be configured as a complex band pass filter or as a tuning device for tuning the center frequency of the complex band pass filter depending on the operation of the plurality of switches. The tuning device includes at least one tuning integrator and a comparator. The tuning integrator includes at least one transconductor and a capacitor. The transconductor is selected via the plurality of switches from the plurality of transconductors and the capacitor is selected via the plurality of switches from said plurality of capacitors. The selected transconductor and the selected capacitor determinines the center frequency of the band pass filter.

Abstract: In the framework of the method for minimizing the error of a measured variable, particularly a signal to be measured using filtering at variable bandwidth, the bandwidth is regulated on the basis of a physical criterion inherent to the method in such a ways that signal changes not caused by noise are recognized as early as possible.

Abstract: An integrated circuit formed on a semiconductor chip, comprising a low pass filter circuit having a first resistor of a first resistance value and a capacitor of a first capacitance value, wherein the first resistance value and the first capacitance value determine a corner frequency of the filter; and a tuning circuit having a second resistor of a second resistance value, a switched-capacitor of a third resistance value and a comparator that compares two voltage signals to produce a control signal, wherein the control signal adjusts the first and second resistance values as a function of the third resistance value. The corner frequency of the filter can be adjusted by varying one or more reference voltage signals. In combination, the corner frequency of the filter is adjusted by changing the frequency of a clock that controls the switched-capacitor to decrease the circuit sensitivity.

Abstract: Disclosed is apparatus for operating with an RC filter (26, 26A), and a corresponding method. The apparatus includes circuitry (32) for use in measuring an actual value of at least one filter component and a controller (34), coupled to the measurement circuitry, for determining at least one adaptive filter (36, 46) coefficient using the measured actual value to so as to compensate for a deviation of at least one filter component value from an ideal value. Where the filter is embodied as an RC network, the circuitry measures an actual value of both a resistor and a capacitor, and the controller uses the measured actual value of the capacitor when determining the value of a resistor.

Abstract: An integrated circuit formed on a semiconductor chip, comprising a low pass filter circuit having a first resistor of a first resistance value and a capacitor of a first capacitance value, wherein the first resistance value and the first capacitance value determine a corner frequency of the filter; and a tuning circuit having a second resistor of a second resistance value, a switched-capacitor of a third resistance value and a comparator that compares two voltage signals to produce a control signal, wherein the control signal adjusts the first and second resistance values as a function of the third resistance value. The corner frequency of the filter can be adjusted by varying one or more reference voltage signals. In combination, the corner frequency of the filter is adjusted by changing the frequency of a clock that controls the switched-capacitor to decrease the circuit sensitivity.

Abstract: A frequency-tuning loop of the invention used in the Transconductor-Capacitor filter is composed of: a first switching device and a second switching device, both having two signal-inputting ends and two signal-outputting ends for switching the output of two signals alternately from two signal-outputting ends according to a fixed clock signal. A transconductor's inputting ends linking to the two signal-outputting ends of said first switching device. One end of a first switch linking to the positive outputting end of the transconductor and the other end linking to the first capacitor and a signal-inputting end of the second switching device. One end of a second switch linking to the negative outputting end of the transconductor and the other end linking to the second capacitor and another signal-inputting end of the second switching device; and a integrated circuit composed of an integrator, a third capacitor, and a fourth capacitor.

Abstract: A switched low pass filter (18) minimizes transients generated during filter switching events and eliminates active circuit random noise. The switched low pass filter (18) includes a filter input terminal (26) for receiving an input base band signal, and an RC circuit (R1, C1, S1, S2) for receiving the input base band signal and for passing only a filtered portion of the input base band signal depending on a wide, mid or narrow band mode of filter operation. The switched low pass filter (18) also includes a transient reduction circuit (34) in switchable communication with the RC circuit (R1, C1, S1, S2) for minimizing transients and switching events caused by transitioning to the mid and narrow band modes of filter operation.

Abstract: Devices and method for effectively filtering a signal, particularly for a communication system, are disclosed. In this regard, an exemplary embodiment of the present invention may be construed as an AFE that includes a high-pass receive filter for a communication system. The filter includes an AC-coupled capacitive input and a plurality of RC integrators. At least one of the plurality of RC integrators includes a damping resistor in parallel with a feedback capacitor and a switch for enabling the damping resistor, such that when the damping resistor is enabled, the at least one RC integrator is damped so as to reduce DC instability.

Abstract: A composite loop compensation circuit and method for a low drop-out regulator configured to facilitate stable operation at very low output load currents is provided. An exemplary low drop-out regulator includes an error amplifier, a pass device, and a composite loop compensation circuit. The compensation loop compensation circuit includes a plurality of segmented sense devices, a plurality of switches and a biasing component. The plurality of segmented sense devices are configured to sense an output load current, i.e., the current from the output terminal of the pass device. The plurality of switches are coupled between the plurality of segmented sense devices and a biasing component. Composite loop compensation circuit is configured to adjust the dominant first pole of the composite feedback loop based on the output load current through biasing of the active resistor component.

Abstract: An output stage compensation circuit and method for a low drop-out regulator configured to facilitate stable operation while providing output voltage and current to downstream circuit devices is provided. An exemplary low drop-out regulator is configured with an output stage compensation circuit including one or more segmented sense devices configured to drive one or more fixed current sources. Each segmented sense device is configured to compensate a suitable range of output current and to multiply the effect of associated compensation capacitors. The one or more segmented sense devices are configured to provide pole-zero compensation based on output current. Further, the current range of each segment can be overlapped. As a result, the stability of the low drop-out regulator is not dependent upon the output current requirements or the capacitance requirements of the downstream circuit.

Abstract: A control system, method and apparatus is provided for an orthogonally variable inductor. A method and apparatus is also provided for voltage regulation. Regulation is provided without the use of Silicon devices, such as FET's, in the output current path. Efficient voltage regulation is provided via varying the inductance of a device in the output current path, and alternatively via varying the inductance and duty cycle. An orthogonal inductive device is provided to vary the inductance in the output current path. The orthogonal inductive device is an external H field device, a series method orthogonal flux device, or a combined core device. Furthermore, a variable inductor is also provided in filters, amplifiers, and oscillators.

Abstract: A semiconductor integrated circuit includes a filter and a time-constant detecting circuit. The filter includes resistance elements; capacitance elements, each of which consists of a capacitance-value switching circuit that can vary the capacitance of the capacitance elements and operational amplifiers. The time-constant detecting circuit detects the time constant of the capacitance element and resistance element, which are formed independently of the capacitance elements and resistance elements of the filter. The semiconductor integrated circuit varies the capacitance of the capacitance element in response to the detected time constant to prevent a reduction in the yield by adjusting the cut-off frequency of the filter in spite of variations in manufacturing the resistance elements and capacitance elements of the filter.

Abstract: A system and method have been provided for selectably equalizing an input signal to an integrated circuit (IC), to compensate for degradation in the transmission process. The selectable equalization circuit includes parallel equalizing and non-equalizing sections. When the equalizing section is engaged a resonant element modifies the circuit impedance to add a zero to the circuit transfer function. When the non-equalizing function is engaged, the equalizing section is disengaged without degrading gate capacitance, and the input signals are processed without a zero in the transfer function.

Abstract: A process variable transmitter providing a transmitter output representing a process variable sensed by a sensor. The transmitter has a filter with a bandwidth which is automatically adjusted based on noise detected in a sensor output. When the transmitter senses higher sensor noise levels, it automatically decreases the bandwidth to damp noise in the transmitter output. When the transmitter senses lower sensor noise levels, it automatically increases the bandwidth to provide faster response to changes in the process variable.

Abstract: A system and method have been provided for selectably equalizing an input signal to an integrated circuit (IC), to compensate for degradation in the transmission process. The selectable equalization circuit includes parallel equalizing and non-equalizing sections. When the equalizing section is engaged a resonant element modifies the circuit impedance to add a zero to the circuit transfer function. When the non-equalizing function is engaged, the equalizing section is disengaged without degrading gate capacitance, and the input signals are processed without a zero in the transfer function.

Abstract: By taking advantage of the ability to control the phase relationship between a processor's output (or portions of a processor's output) and the phase of the pre-processed signal (in a particular frequency range or ranges, a controlled accentuation or enhancement of the processor's effect can be realized. In one embodiment this is achieved by providing a gain control circuit that receives and selectively amplifies the input signal prior to it being summed with the processor's output.

Abstract: A system and method for selectively providing high pass filtering of two digital signals that are to be subsequently combined. Each of the first and second signals is passed through one of a high pass filter, an all-pass filter and a module that performs substantially no signal filtering, where the phase and magnitude for either high pass filter are substantially equal to the phase and magnitude for either all-pass filter. At the minimum, the system provides the following filtering combinations for the respective first signal and second signal: (no filter, no filter), (high pass, high pass), (high pass, all-pass) and (all-pass, high-pass). Suitable first order high pass and corresponding all-pass filters are determined.

Abstract: A system and method for use in cancelling phase jitter in a Phase Locked Loop (PLL) circuit. A phase jitter canceller receives a phase error signal having phase jitter centered around a center frequency. A frequency and phase control circuit determines the phase of a particular component of phase jitter and an amplitude control circuit determines the amplitude of the particular component of phase jitter in the signal. The output of the phase jitter canceller provides an estimate of the particular component of phase jitter. A parallel arrangement of phase jitter cancellers is also provided for use in cancelling several components of phase jitter.

Abstract: An integrated circuit having a passive circuit component that can be adjusted following the manufacturing process to provide a precise absolute value for resistance or capacitance. A plurality of passive elements are selectively combinable using logic gates to include or exclude each element from a network, wherein the combined value of the included passive elements equals the value of the passive circuit component. The logic gates are set by outputs from a decoder to reduce the required inputs to the chip.

Abstract: The present invention is to provide an integrated circuit capable of reducing the substrate area, a variable filter adjusting method for the integrated circuit, and an electronic equipment using the integrated circuit, in which disorder of an external element and its temperature characteristic can be automatically corrected following the adjustment of disorder of the internal elements and their temperature characteristics by performing digital/analog conversion of a control signal to be input to a first adjustment unit for adjusting the disorder of internal elements of the integrated circuit and their temperature characteristics, so that the control signal can be input to a second adjustment unit as a reference signal of a digital/analog converter.

Abstract: A low electric power consumption filter circuit includes an amplifying portion including an odd number of serial MOS inverters. A grounded capacitance is connected between an output of the amplifying portion and ground. A pair of balancing resistances connect an output of the MOS inverter to a supply voltage and ground at a previous stage of the last MOS inverter. A feedback impedance connects an output of the amplifying portion to its input. An input impedance is connected to the input of the amplifying portion.

Abstract: An information system comprises an information network and a station apparatus capable of receiving information from the network and sending a command to the network. An isolator comprises a first diplex filter having an input/output (I/O) port coupled to the network for passing signals with frequencies in first and second non-overlapping ranges. An output port is provided for signals with frequencies in the first range, and an input port is provided for signals with frequencies in the second range. A second diplex filter has an I/O port coupled to the station apparatus for passing signals with frequencies in both the first and second ranges. An input port is provided for signals with frequencies in the first range, and an output port is provided for signals with frequencies in the second range. A first circuit having a bandwidth including the first range provides a first signal path between the output port of the first diplex filter and the input port of the second diplex filter.

Abstract: A filter circuit having a signal input terminal and a signal output terminal includes a first and a second buffer. The first buffer has an input end connected to a first resistor and to a first capacitor. A second capacitor having one end is connected to an output end of the first buffer. A second resistor having one end is connected to the signal input terminal. The second buffer has an input end connected to the other end of the second resistor and to the other end of the second capacitor, and an output end connected to the signal output terminal. The filter circuit also includes a first signal supply circuit and a second signal supply circuit. The first signal supply circuit supplies a signal proportional to a difference between an output signal of the second buffer and a signal inputted from the signal input terminal, to the input end of the first buffer through the first resistor.

Abstract: A common transceiver circuit for use as either a modulator or demodulator and that is implemented through a shared resource approach. This approach is particularly, though not exclusively, suited for vestigial sideband (VSB) signals. Specifically, a VSB transceiver circuit (700), through strategically located multiplexing stages, physically re-uses a complex vestigial Nyquist filter (610), a complex mixer (620) and an equalizer (785) during demodulation and modulation. The VSB transceiver also selects a particular configuration of a common complex Hilbert transform circuit (720) for use during either demodulation or modulation. In addition, the same equalizer selectively provides both channel equalization, during de-modulation, and (sin x)/x compensation, during modulation, through use of differing corresponding sets of tap coefficients.

Abstract: An amplifier circuit (204) having a variable bandwidth comprises an amplifier (300), a capacitive element (304), a first npn transistor (302), and a switch control circuit (306). The first npn transistor (302) has a base coupled to an output terminal (205) of the amplifier (300), a collector coupled to a first reference voltage (113), and an emitter coupled to the capacitive element (304) and the switch control circuit (306). When the first npn transistor (302) is switched off by the switch control circuit (306), a first cutoff frequency is determined by a maximum operating frequency of the amplifier (300). When the first npn transistor (302) is switched on by the switch control circuit (306), a second cutoff frequency is determined by a capacitance of the capacitive element (304). For high frequency operation, the amplifier (300) includes at least a second npn transistor for amplification and the first cutoff frequency is determined by a Miller capacitance of the amplifier circuit (204).

Abstract: A power switching apparatus includes a positive-sequence fundamental signal magnitude detector. The positive-sequence fundamental signal magnitude detector derives a positive-sequence fundamental signal from a three-phase voltage signal carried by a power line; it also generates a switch firing command when the positive-sequence fundamental signal exceeds a predetermined threshold value indicative of a fault condition on the power line. The power switching apparatus also includes a solid state switch connected to the power line and the positive-sequence fundamental signal magnitude detector. The solid state switch bloch power on the power line in response to the switch firing command.