Unwanted Signal Suppression Patents (Class 327/551)
  • Patent number: 10868574
    Abstract: A method to cancel amplitude modulation noise (contamination) of an input (carrier) signal, including: receiving an input monochromatic signal contaminated with amplitude modulation noise; demodulating the amplitude modulation noise to generate a baseband amplitude modulation noise signal; signal processing the baseband amplitude modulation noise signal to generate an amplitude modulation noise cancelation signal; and amplitude modulating the input signal based on the amplitude modulation noise cancelation signal to generate an output signal, the output signal having less amplitude modulation noise than the input signal. A feedforward implementation can use signal inversion to generate a feedforward amplitude modulation noise cancelation signal. A feedback implementation, implemented with a gain controlled amplifier, can be based on, in a feedback path, demodulating the amplitude noise modulation signal in a feedback gain-controlled input signal to generate a feedback gain control signal.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: December 15, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Lawrence Herbert Zuckerman
  • Patent number: 10735013
    Abstract: A time-interleaved digital-to-analog converter system, comprising a digital pre-distorter configured to receive an input digital signal and an error signal and output a distorted digital signal based on the input digital signal and the error signal; a time-interleaved digital-to-analog converter having a first sample rate, the time-interleaved digital-to-analog converter configured to convert the distorted digital signal to an analog signal; and a calibration system. The calibration system includes an analog-to-digital converter having a second sample rate equal to or lower than the first sample rate, the analog-to-digital converter configured to receive the analog signal and covert the analog signal to a down-sampled digital signal, a discrete-time linear model configured to receive the input digital signal and the error signal and output a model signal, and a combiner to subtract the down-sampled digital signal from the model signal to generate the error signal.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: August 4, 2020
    Assignee: Tektronix, Inc.
    Inventors: Karen Hovakimyan, Gregory A. Martin, Daniel G. Knierim
  • Patent number: 10728081
    Abstract: A computer-implemented method of estimating IQ imbalance in a communication system including a transmitter and a receiver. The method includes: defining a system model in which a transmitted signal is affected by TX IQ imbalance, carrier frequency offset (CFO) and RX IQ imbalance; controlling a local oscillator at the transmitter to introduce a known carrier frequency offset (CFO) during a calibration; and estimating unknown parameters in the system model using a pre-defined training sequence to determine the TX IQ imbalance and the RX IQ imbalance.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: July 28, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Magnus Stig Torsten Sandell, Evgeny Tsimbalo, Ichiro Seto
  • Patent number: 10643400
    Abstract: A head-mounted display device with which a user can visually recognize a virtual image and an outside scene includes an image display unit configured to cause the user to visually recognize the virtual image, an augmented-reality processing unit configured to cause the image display unit to form the virtual image including a virtual object, at least a part of which is superimposed and displayed on a real object present in the real world, a color detecting unit configured to detect a real object color, which is a color of the real object, and a color adjusting unit configured to bring a visual observation color, which is a color obtained by superimposing a color of the virtual object on the real object color, close to a target color using the detected real object color.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: May 5, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Akio Yamazaki
  • Patent number: 10530326
    Abstract: An input/output apparatus of a multiplexer is provided, including: a main tap and at least two branch taps of the main tap, where each of the at least two branch taps is configured to couple to a different resonant cavity in the multiplexer, and the at least two branch taps include a first branch tap and a second branch tap; a coupling polarity of the first branch tap is opposite to that of the second branch tap; and a coupling calculation frequency of the second branch tap is closest to a coupling calculation frequency of the first branch tap. The input/output apparatus of the multiplexer enables two channels with closest frequencies to use different coupling polarities. Because the coupling polarities are different, signals naturally do not interfere with each other, and signal interference between channels is eliminated in principle. The embodiments of the present disclosure further provide a corresponding multiplexer.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: January 7, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Xiaofeng Zhang, Lixia Qiu, Ke Chen
  • Patent number: 10498573
    Abstract: Systems and methods for combining signals from multiple active wireless receivers are discussed herein. An exemplary system comprises a first downconverter, a phase comparator, a phase adjuster, and a second downconverter. The first downconverter may be configured to downconvert a received signal from a first antenna to an intermediate frequency to create an intermediate frequency signal. The phase comparator may be configured to mix the received signal and a downconverted signal to create a mixed signal, compare a phase of the mixed signal to a predetermined phase, and generate a phase control signal based on the comparison, the downconverted signal being associated with the received signal from the first antenna. The phase adjuster may be configured to alter the phase of the intermediate frequency signal based on the phase control signal. The second downconverter may be configured to downconvert the phase-shifted intermediate frequency signal to create an output signal.
    Type: Grant
    Filed: April 6, 2015
    Date of Patent: December 3, 2019
    Assignee: Aviat U.S., Inc.
    Inventor: Ying Shen
  • Patent number: 10367490
    Abstract: An electronic circuit may include a driver, a delay circuit, a strength control circuit, and an adder circuit. The driver may generate a second signal based on a first signal. The delay circuit may delay the first signal by as much as a reference time, to generate a third signal. The strength control circuit may adjust an amplitude of the third signal to generate a fourth signal. The adder circuit may add the second signal and the fourth signal to generate a fifth signal. In a first time interval determined based on the reference time, an amplitude of the fifth signal may be greater than an amplitude of the second signal. In a second time interval except for the first time interval, the amplitude of the fifth signal may be smaller than the amplitude of the second signal. In the second time interval, the amplitude of the fifth signal may be smaller than an amplitude of the first signal.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: July 30, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wangsoo Kim, Hangi Jung, Kiduk Park, Yoo-Chang Sung, Jae-Hun Jung, Cheongryong Cho, Hun-Dae Choi
  • Patent number: 10340933
    Abstract: A time interleaved digital to analog converters (TIDACs) system having a pre-processing filter to filter a digital signal prior to being converted by a respective digital-to-analog converter (DAC) of the TIDACs system to correct for mismatches between the DACs of the TIDACs system. Calibrating the pre-processing includes converting a discrete waveform at a first DAC to a first analog signals and at a second DAC to a second analog signal and combining the first and second analog signals into a combined signal. An analog-to-digital converter (ADC) converts the combined signal to a digital signal to determine an actual frequency response of the TIDACs system. A desired frequency response of the TIDACs system is received and a pre-processing filter is generated for the first DAC and the second DAC based on the actual frequency response of the TIDACs system and the desired frequency response of the TIDACs system.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: July 2, 2019
    Assignee: Tektonix, Inc.
    Inventor: Karen Hovakimyan
  • Patent number: 10295567
    Abstract: A probe module, which supports loopback test and is provided between a PCB and a DUT, includes an adapter, two probes, two inductive components provided at the adapter, and a capacitive component. The adapter has two connecting circuits. An end of each of the probes is connected to one of the connecting circuits, while another end thereof, which is a tip, contacts the DUT. Each of the inductive components has an end electrically connected to one of the connecting circuits, and another end electrically connected to the PCB through a conductive member, which is provided at the adapter, wherein two ends of the capacitive component are electrically connected to one of the connecting circuits, respectively. Whereby, the signal paths are changed by the differences between frequencies of signals, and the transmission path of high-frequency signals is effectively shortened.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: May 21, 2019
    Assignee: MPI CORPORATION
    Inventors: Wei-Cheng Ku, Hao Wei, Jun-Liang Lai, Chih-Hao Ho
  • Patent number: 10191589
    Abstract: A circuit described herein includes a charge to voltage converter circuit having an input coupled to receive a sense signal from a sense node associated with a mutual capacitance to be sensed, and an output. A reset switch is coupled between the output of the charge to voltage converter circuit and the input of the charge to voltage converter. An accumulator circuit is configured to accumulate voltages at the output of the charge to voltage converter circuit and to generate an accumulator output signal. Control circuitry is configured to generate control signals for the reset switch and accumulator circuit so as to reduce noise in the accumulator output signal.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: January 29, 2019
    Assignee: STMicroelectronics Asia Pacific Pte Ltd
    Inventors: Hugo Gicquel, Chee Weng Cheong
  • Patent number: 10133833
    Abstract: A method and a device for predictive evaluation of intermodulation power in an electronic device in which a predictive function f makes it possible to evaluate in a predictive manner values of power of an intermodulation component produced by an intermodulation distortion of an input signal, characterized in that the predictive function f includes an odd part V obtained by multiplication of an odd function F and of a function G, obtained by composition of a positive real-valued even function g and of a function Q in the form of a real series including at least one term of degree q belonging to the non-integer reals.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: November 20, 2018
    Assignee: CENTRE NATIONAL D'ÉTUDES SPATIALES—C N E S
    Inventors: Jacques Sombrin, Geoffroy Soubercaze-Pun, Isabelle Albert
  • Patent number: 10135646
    Abstract: A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: November 20, 2018
    Assignee: Rambus Inc.
    Inventors: Hae-Chang Lee, Brian S. Leibowitz, Jade M. Kizer, Thomas H. Greer, Akash Bansal
  • Patent number: 10109291
    Abstract: A noise suppression device includes an estimating unit that estimates, from a feature quantity representing the feature in each frequency range of a first acoustic signal which represents sound, the noise component of the feature quantity; a calculating unit that calculates, from the feature quantity and the noise component for each frequency range, a first suppression coefficient to be used in suppressing noise included in the first acoustic signal; a first attenuating unit that attenuates the first suppression coefficient in the time domain and calculates a second suppression coefficient; a second attenuating unit that attenuates the second suppression coefficient in the frequency domain and calculates a third suppression coefficient; and a generating unit that estimates, from the feature quantity and the third suppression coefficient, a voice component of the feature quantity and generates a second acoustic signal in which the noise included in the first acoustic signal is suppressed.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: October 23, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Hirohata, Yusuke Kida
  • Patent number: 10101483
    Abstract: Systems and methods for evaluating a cement installation are provided. In one example, the cement may be evaluated using a casing arrival measurement sensor that measures casing arrival signals resulting from firing a signal from a cement bond logging acoustic source. External signals (e.g., signals other than the casing arrival signals) may be attenuated by firing an attenuation firing signal.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: October 16, 2018
    Assignee: SCHLUMBERGER TECHNOLOGY CORPORATION
    Inventor: Jahir Pabon
  • Patent number: 10096571
    Abstract: A method includes bonding a die to a substrate, where the substrate has a first redistribution structure, the die has a second redistribution structure, and the first redistribution structure is bonded to the second redistribution structure. A first isolation material is formed over the substrate and around the die. A first conductive via is formed, extending from a first surface of the substrate, where the first surface is opposite the second redistribution structure, the first conductive via contacting a first conductive element in the second redistribution structure. Forming the first conductive via includes patterning an opening in the substrate, extending the opening to expose the first conductive element, where extending the opening includes using a portion of a second conductive element in the first redistribution structure as an etch mask, and filling the opening with a conductive material.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: October 9, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Ming-Fa Chen, Sung-Feng Yeh
  • Patent number: 9928297
    Abstract: A device generates, in a container box of a file for storage of video contents, a SampleGroupDescription box that provides a sample group description for a sample grouping. The SampleGroupDescription box includes a grouping type syntax element having a particular value. Additionally, the SampleGroupDescription box includes one or more sample group entries. The device generates, in the same container box, a plurality of SampleToGroup boxes. Each respective SampleToGroup box of the plurality of SampleToGroup boxes includes a respective grouping type syntax element having the particular value, includes a respective sample count syntax element indicating a number of samples in a respective sample grouping, and includes a respective group description index syntax element indicating an index of an entry in the SampleGroupDescription box which describes samples of the respective sample grouping. Each sample of the respective sample grouping comprises a respective picture of the video contents.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: March 27, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Fnu Hendry, Ye-Kui Wang
  • Patent number: 9900035
    Abstract: A detection apparatus according to an embodiment includes an acquisition unit, a calculation unit, and a detection unit. The acquisition unit acquires, via an antenna positioned on a movable body, data on which signal groups with different base frequencies are superimposed. The calculation unit calculates, based upon a frequency spectrum of the data acquired by the acquisition unit, the base frequencies of the respective signal groups. The detection unit detects signals in the respective signal groups based upon the base frequencies calculated by the calculation unit.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: February 20, 2018
    Assignees: FUJITSU TEN LIMITED, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Kosuke Takano, Takuma Sawaya
  • Patent number: 9866111
    Abstract: Aspects of the disclosure provide a circuit for providing a power supply. The circuit includes a control signal generator circuit and a switch network circuit. The control signal generator circuit is configured to generate a control signal with a voltage level that is a function of an output voltage on a load capacitor. The switch network circuit is coupled with the load capacitor and a flying capacitor to form a charge pump circuit. The switch network circuit is configured to charge the flying capacitor in a charge stage and pump the flying capacitor in a pump stage to generate the output voltage on the load capacitor. The switch network circuit is configured to provide a pump control voltage to the flying capacitor during the pump stage. The pump control voltage has a voltage level that is adjusted based on the control signal to maintain the output voltage to be stable.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: January 9, 2018
    Assignee: Marvell International Ltd.
    Inventors: Xiaoxiao Zhao, Wenrong Qian, Yifeng Huang, Yongxu Wang
  • Patent number: 9843346
    Abstract: A digital frontend circuit for a radio frequency (RF) comprises a digital predistortion (DPD) block, a plurality of sub-sample delay elements, and a selection circuit. The DPD block for computing predistorted transmit signals according to a Volterra series approximation model. The DPD block has an input for receiving input samples at a first sample rate and an output for providing the predistorted transmit signals at the first sample rate. Each of the sub-sample delay elements provides a delay to an input sample as specified by the Volterra series approximation model, where each of the delays is based on a fraction of the first sample rate. The selection circuit selects one of the plurality of sub-sample delay elements in response to a selection signal from the digital predistortion block. The selection signal for selecting a delay as specified by the Volterra series approximation model.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: December 12, 2017
    Inventors: Jayakrishnan Cheriyath Mundarath, Mir Masood, Peter Zahariev Rashev
  • Patent number: 9819330
    Abstract: A digital filter for filtering an input signal to form an output signal containing a coefficient multiplier and a moving-average filter. The coefficient multiplier is embodied to multiply values of the input signal by coefficients of the filter to form an intermediate signal. The moving-average filter is embodied to generate the output signal as a moving average of the intermediate signal.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: November 14, 2017
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventor: Stefan Schmidt
  • Patent number: 9719877
    Abstract: A system and method mitigate the effects of these external vibrations on a capacitance diaphragm gauge by sensing the motion of the diaphragm at the first natural frequency of the diaphragm of the CDG. The presence of the natural frequency signals superimposed on the pressure signal is determined by sensing variations in the output of a sensor at or near the known natural frequency of the diaphragm and filtering that known low frequency from the output. The filtered signal is used in a feedback circuit to impose electrostatic forces on the diaphragm. The imposed electrostatic forces oppose the motion created by the external vibration to suppress the effects of the vibration on the pressure measured by the CDG.
    Type: Grant
    Filed: February 28, 2015
    Date of Patent: August 1, 2017
    Assignee: Ferran Technology, Inc.
    Inventor: Robert J. Ferran
  • Patent number: 9722820
    Abstract: A method of calibrating coefficients of a calibrated decision feedback equalizer (DFE) across a process, voltage, and temperature (PVT) range, the calibrated DFE comprising a plurality of DFE taps for reducing distortions of an input signal, and a sampler for sampling the input signal, the method including applying a preset voltage to an input of the calibrated DFE, setting a DFE tap of the plurality of DFE taps to a maximum value, generating a source reference, via a source reference calibrator, to apply to the DFE tap, changing the source reference to a first level that causes an output of the sampler to transition from a first state to a second state, determining the first level as a calibrated source reference, and applying the calibrated source reference to the DFE tap during normal operation of the calibrated DFE.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: August 1, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Mohammad Hekmat, Amir Amirkhany
  • Patent number: 9660677
    Abstract: A method of rejecting impulsive noise in an OFDM receiver is described. The impulsive noise is rejected using channel state information (CSI) and is performed in the frequency domain. A noise power estimate (furthermore referred to as a noise value) is measured for a single OFDM symbol and compared to a threshold value, which may be generated based on a short-term average of OFDM symbols not corrupted by impulsive noise or predicted based on a small number of previously measured OFDM symbols not corrupted by impulsive noise. If the noise estimate for the particular OFDM symbol exceeds the threshold value, the CSI for that symbol is derated (i.e. modified) to reduce the influence of the information from this symbol on the decoding process.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: May 23, 2017
    Assignee: Imagination Technologies Limited
    Inventor: Paul Murrin
  • Patent number: 9654014
    Abstract: A current-mode switch-mode power supply controller includes a switch controller, a falling edge detector, and leading edge blanking (LEB) time logic. The switch controller is arranged to control regulation of an output signal via current-mode regulation by turning a primary switch on and off based on a current sense (CS) signal and an LEB signal, such that the switch controller is arranged to cause the primary switch to remain on while the LEB time signal is asserted. The falling edge detector is arranged to detect a falling edge in the CS signal. The LEB time logic is arranged to provide the LEB time signal such that the assertion of the LEB time signal begins when a gate signal is asserted, and such that the assertion of the LEB time signal ends when the falling edge detector detects the falling edge in the CS signal.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: May 16, 2017
    Assignee: Infineon Technologies Austria AG
    Inventor: Xiaowu Gong
  • Patent number: 9634026
    Abstract: A standard cell IC may include a plurality of pMOS transistors each including a pMOS transistor drain, a pMOS transistor source, and a pMOS transistor gate. Each pMOS transistor drain and pMOS transistor source of the plurality of pMOS transistors may be coupled to a first voltage source. The standard cell IC may also include a plurality of nMOS transistors each including an nMOS transistor drain, an nMOS transistor source, and an nMOS transistor gate. Each nMOS transistor drain and nMOS transistor source of the plurality of nMOS transistors are coupled to a second voltage source lower than the first voltage source.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: April 25, 2017
    Assignee: QUALCOMM INCORPORATED
    Inventors: Satyanarayana Sahu, Xiangdong Chen, Ramaprasath Vilangudipitchai, Dorav Kumar
  • Patent number: 9628199
    Abstract: A processing device detects an occurrence of the first set of use conditions associated with a power supply line coupled between a power source and a power sink in a user device. The processing device sets a tunable decoupling capacitor on the power supply line to a first capacitance value to reduce a level of electromagnetic interference on the power supply line at a first frequency corresponding to the first capacitance value. When the processing device detects a change from the first set of use conditions associated with the power supply line to a second set of use conditions, the processing device sets the tunable decoupling capacitor to a second capacitance value to reduce a level of electromagnetic interference on the power supply line at a second frequency corresponding to the second capacitance value.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: April 18, 2017
    Assignee: Amazon Technologies, Inc.
    Inventors: Mudit Sunilkumar Khasgiwala, Akshay Mohan, Jagan Vaidyanathan Rajagopalan, Duck Ho Bae
  • Patent number: 9595998
    Abstract: There is provided a sampling point adjustment apparatus including: a frequency conversion unit that converts a first signal and a second signal into a first narrow band signal and a second narrow band signal through frequency conversion; a central position determination unit that determines a central position of a window of the frequency conversion for the second signal based on an estimated value of a sampling interval offset between the first narrow band signal and the second narrow band signal; and a phase control unit that controls a phase of the second narrow band signal based on the estimated value.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: March 14, 2017
    Assignee: SONY CORPORATION
    Inventors: Mototsugu Abe, Masayuki Nishiguchi
  • Patent number: 9543122
    Abstract: In one embodiment, an RF generator includes an RF amplifier that includes an RF input, a DC input, and an RF output, the RF amplifier configured to receive at the RF input an RF signal from an RF source; receive at the DC input a DC voltage from a DC source; and provide an output power at the RF output; and a control unit operably coupled to the DC source and the RF source, the control unit configured to receive a power setpoint for the RF output; determine a power dissipation at the RF generator; and alter the DC voltage to a final DC voltage that decreases the power dissipation at the RF generator while enabling the output power at the RF output to be substantially equal to the power setpoint.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: January 10, 2017
    Inventor: Imran Ahmed Bhutta
  • Patent number: 9508314
    Abstract: An electronic equipment includes a control unit, an EMI frequency storage unit, and a settable range detection unit. The EMI frequency storage unit stores respective frequencies of EMI noise components in ones of driving pulse signals, which are transmitted from the control unit to other modules than a display module in association with the other modules. The settable range detection unit detects a settable range of the frequency of one of the driving pulse signals, which is transmitted from the control unit to the display unit. When transmitting the driving pulse signal to the display module, the control unit sets, as the frequency of the driving pulse signal to the display module, a frequency that is a frequency excluding the frequencies of the EMI noise components stored in association with the other modules that are being driven and also is a frequency in the settable range that has been detected.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: November 29, 2016
    Assignee: KYOCERA DOCUMENT SOLUTIONS INC.
    Inventor: Shinji Tomofuji
  • Patent number: 9419663
    Abstract: A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: August 16, 2016
    Assignee: Rambus Inc.
    Inventors: Hae-Chang Lee, Brian S. Leibowitz, Jade M. Kizer, Thomas H. Greer, Akash Bansal
  • Patent number: 9380231
    Abstract: A correlated double sampling (CDS) circuit may include a sampling circuit and a switching circuit. The CDS circuit may perform a CDS operation on a reset component of an input signal and an image component of the input signal based on a ramp signal, and the CDS circuit may generate an output signal. The switching circuit may include an auto-zero switch that connects a first input terminal receiving the input signal to an output node in response to an auto-zero control signal during an auto-zero interval. The switching circuit may connect a first terminal of the auto-zero switch to a reference voltage in order to cutoff a leakage current flowing to the auto-zero switch in response to a first boosting control signal during a first comparison interval and a second comparison interval. The output signal may be provided at the output node.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: June 28, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han Yang, Sin-Hwan Lim, Kyoung-Min Koh, Jae-Cheol Yun, Kwang-Hyun Lee, Soon-Ik Cho
  • Patent number: 9350329
    Abstract: An electronic system may include a first circuit driven by a first power voltage signal and a first ground voltage signal, and a second circuit driven by a second power voltage signal and a second ground voltage signal. The electronic system may also include a stabilizer coupled between a first ground terminal and a second ground terminal and suitable for blocking a current flowing from the second ground terminal toward the first ground terminal.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: May 24, 2016
    Assignee: SK Hynix Inc.
    Inventor: Jong Su Kim
  • Patent number: 9225492
    Abstract: Systems, methods, apparatuses, and computer program products for interference cancelation are provided. One method includes forming, by a wireless system, a signal structure to match a structure of an interfering signal with repetitive time structure. The method may further include using the formed signal structure to eliminate interference caused by the interfering signal. The signal structure includes parts that are synchronized with the repeated parts of the interfering signal structure to cancel the repetition of the interference, and the signal structure further comprises another part synchronized with the non-repeated parts of the interference signal.
    Type: Grant
    Filed: April 9, 2013
    Date of Patent: December 29, 2015
    Assignee: NOKIA TECHNOLOGIES OY
    Inventors: Rafael Paiva, Andre Mendes Cavalcante, Robson Domingos Vieira, Fabiano Chaves, Fuad Abinader, Jr., Angilberto Sobrinho, Erika Almeida
  • Publication number: 20150145571
    Abstract: A fractional-N phase-locked loop (PLL) includes a nonlinear time to digital converter that generates a digital representation of a phase error corresponding to a time difference between a feedback signal of the fractional-N PLL and a reference signal. A nonlinear quantization noise cancellation circuit supplies a correction signal to ensure that the generated digital representation has reduced quantization noise. The correctional signal may be applied in the analog or digital domain.
    Type: Application
    Filed: July 31, 2014
    Publication date: May 28, 2015
    Inventor: Michael H. Perrott
  • Publication number: 20150145593
    Abstract: Microfeature dies with redistribution structures that reduce or eliminate line interference are disclosed. The microfeature dies can include a substrate having a bond site and integrated circuitry electrically connected to the bond site. The microfeature dies can also include and a redistribution structure coupled to the substrate. The redistribution structure can include an external contact site configured to receive an electric coupler, a conductive line that is electrically connected to the external contact site and the bond site, and a conductive shield that at least partially surrounds the conductive line.
    Type: Application
    Filed: February 2, 2015
    Publication date: May 28, 2015
    Inventor: Mark S. Johnson
  • Patent number: 9030240
    Abstract: A signal processing device enables a high quality enhanced signal to be obtained, and includes: a transform unit which transforms a mixed signal in which a first signal and a second signal are mixed, into a phase component and an amplitude component or a power component in each frequency; a first control unit which rotates the phase component in a predetermined frequency; a second control unit which compensates the amplitude component or the power component in the predetermined frequency according to the amount of change of the amplitude component or the power component rotated by the first control unit; and a synthesizing unit which synthesizes the phase component rotated by the first control unit, and the amplitude component or the power component compensated by the second control unit.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: May 12, 2015
    Assignee: NEC Corporation
    Inventor: Ryoji Miyahara
  • Patent number: 9024683
    Abstract: A clock network includes a first plurality of shield wires associated with a first plurality of clock lines and a second plurality of shield wires associated with a second plurality of clock lines. The clock network also includes a first plurality of clock activity program circuits associated with the first plurality of clock lines and a second plurality of clock activity program circuits associated with the second plurality of clock lines, wherein the first and second plurality of shield wires and the first and second plurality clock activity program circuits are configured to reduce power spikes.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: May 5, 2015
    Assignee: Altera Corporation
    Inventors: David Lewis, Ryan Fung
  • Patent number: 9013232
    Abstract: A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: April 21, 2015
    Assignee: Silicon Laboratories Inc.
    Inventors: David Welland, Donald Kerth, Caiyi Wang
  • Publication number: 20150097616
    Abstract: A differential circuit system is provided. The differential circuit system includes: a different circuit set including a plurality of differential circuits, a voltage regulator, and a current drainage circuit set. The differential circuits are electrically connected between a first node and a second node, and each differential circuit generates a current flowing from the first node to the second node. A high voltage is provided to the first node and a low voltage is provided to the second node. The first node receives an external voltage. According to the first voltage, the voltage regulator generates the low voltage. The low voltage is provided to the second node. The current drainage circuit set generates a drainage current in between the second node and a ground voltage. A superposed current flowing to the voltage regulator is difference of the summation of currents minus the conducting current.
    Type: Application
    Filed: October 3, 2014
    Publication date: April 9, 2015
    Inventors: Fan-Yi Jien, Wen-Tai Wang, Sheng-Tsai Huang, Yen-Cheng Chen
  • Patent number: 9000838
    Abstract: A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.
    Type: Grant
    Filed: December 30, 2012
    Date of Patent: April 7, 2015
    Assignee: Silicon Laboratories Inc.
    Inventors: David Welland, Donald Kerth, Caiyi Wang
  • Publication number: 20150091639
    Abstract: A semiconductor device includes conducting lines of a first group and a second group arranged in parallel, a plurality of first internal elements respectively coupled to the conducting lines of the first group and the second group and a plurality of first contact pads arranged between and along the conducting lines of the first group and the second groups, wherein at least a part of the plurality of first contact pads are respectively coupled to control terminals of the plurality of first internal elements, and the part of the plurality of first internal elements receive a plurality of first control signals through corresponding control terminals, respectively.
    Type: Application
    Filed: December 19, 2013
    Publication date: April 2, 2015
    Applicant: SK hynix Inc.
    Inventor: Bo-Yeun KIM
  • Publication number: 20150091640
    Abstract: A passive filter for connection between an AC source and a load, in either three-phases or in a single-phase arrangement. The filter includes, for each phase, a trap circuit having an inductor in series with a capacitor, the trap circuit having at least two terminals. A line reactor is connected between the AC source and the load, the line reactor having at least an input terminal, an output terminal and a tap terminal. A switch selectively connects at least one of the trap circuit terminals to a selected one of the line reactor terminals. The switch is capable of selecting which of the trap circuit terminals to connect to which of the line reactor terminals on the basis of a level of voltage distortion being experienced by the AC source, or on the basis of a calculated level of background voltage total harmonic distortion.
    Type: Application
    Filed: September 30, 2014
    Publication date: April 2, 2015
    Applicant: TCI, LLC
    Inventors: Ian Wallace, Ashish Bendre, Neil Wood, William Kranz
  • Patent number: 8995519
    Abstract: Generating updated coefficients for an adaptive equalizer involves generating phase tracking information using asynchronous detection strategy (ADS) based on resolved data, and equalized signals, and estimating a phase corrected error based on the equalized signals, the phase tracking information and the resolved data. An inhibit signal is generated to inhibit updating of the equalization coefficients, the inhibit signal representing a likelihood of the phase corrected error being accurate, determined according to the phase corrected error, and the equalized signals. The equalization coefficients for the equalizer are adapted based on the received signals, and on the phase corrected error, and the adapting is inhibited according to the inhibit signal. Compared to conventional ADS, the new combination with the inhibit signal can enable improved convergence of coefficient adaptation. This is particularly useful for coherent receivers for optical systems.
    Type: Grant
    Filed: October 15, 2010
    Date of Patent: March 31, 2015
    Assignee: Telefonaktiebolaget L M Ericsson (Publ)
    Inventors: Tommaso Foggi, Giulio Colavolpe
  • Patent number: 8988110
    Abstract: A noise removal circuit is provided having a first holding circuit (20) and a second holding circuit (22) which holds a value of an input signal (IN) at a plurality of different timings in synchronization with rising and falling of an internal clock signal (ICL) generated within a semiconductor device, and which removes noise of the input signal (IN) according to the held value.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: March 24, 2015
    Assignee: Semiconductor Components Industries, LLC
    Inventor: Yoshihiro Nagae
  • Publication number: 20150070088
    Abstract: A method of canceling nonlinear distortions in pulse width modulated signals includes receiving an input signal. A first signal that is the modulated input signal is generated. The first signal has quantized levels representing the input signal. A pulse width modulated (PWM) sequence that is representative of the first signal is generated. A second signal that is the PWM sequence mixed with a carrier signal is generated. An error signal is generated in response to the first signal and modeled from the second signal. The error signal is added to the input signal.
    Type: Application
    Filed: September 6, 2013
    Publication date: March 12, 2015
    Applicant: Texas Instruments Incorporated
    Inventors: Lei Ding, Rahmi Hezar, Joonhoi Hur
  • Patent number: 8970291
    Abstract: A method of debouncing a variable frequency step signal is provided. The method includes the steps of: (a) determining a first period in oscillations of the variable frequency step signal and applying a first debounce time to debounce oscillations in the variable frequency step signal, (b) detecting a second period in the oscillations of the variable frequency step signal, (c) calculating a second debounce time as a fraction of the first period, (d) applying the second debounce time to debounce oscillations having the second period, and (e) repeating the steps (b)-(d) for debouncing successive oscillations of varying periods in the variable frequency step signal.
    Type: Grant
    Filed: December 10, 2013
    Date of Patent: March 3, 2015
    Assignee: Caterpillar Inc.
    Inventors: Jesse R Gerdes, Jackson Wai, Benjamin Paul Gottemoller, Sangameshwar Sonth
  • Publication number: 20150048880
    Abstract: A glitch filter is disclosed herein. The glitch filter includes a high glitch filter circuit, a low glitch filter and a control circuit. The high glitch filter circuit is configured for generating a pull-up control signal in accordance with the input signal. The low glitch filter circuit is configured for generating a pull-down control signal in accordance with the input signal. The control circuit is configured for determining the logic level of the output of the glitch filter in accordance with the pull-up control signal and the pull-down control signal. A filtering method for filtering glitches is disclosed herein as well.
    Type: Application
    Filed: August 14, 2013
    Publication date: February 19, 2015
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventor: Bin LIU
  • Patent number: 8937496
    Abstract: A clock monitoring circuit is disclosed. The clock monitoring circuit is configured to receive first and second clock signals generated in respective clock domains. The clock monitoring circuit includes a first counter configured to count clock cycles of the first clock signal for a first period of time delineated by clock cycles of the second clock signal. The first counter outputs a count value indicating the number of counted clock cycles. The clock monitoring circuit also includes a threshold comparator circuit configured to generate an error signal in response to expiration of the first period of time and the first count value output by the first counter falling outside of an expected range.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: January 20, 2015
    Assignee: Xilinx, Inc.
    Inventors: Sagheer Ahmad, Alex S. Warshofsky, Ygal Arbel
  • Patent number: 8938291
    Abstract: In an embodiment, an electrical-line-noise canceller includes a phase detector, a phase lock loop, a zero-crossing detector, and an adaptive filter. The phase detector is configured to receive a composite input signal including an input neural signal combined with electrical line noise and to detect a phase of the electrical line noise. The phase lock loop is coupled to the phase detector and is configured to lock to the phase of the electrical line noise. The zero-crossing detector is coupled to the phase lock loop and is configured to detect zero crossings of an output of the phase lock loop. The adaptive filter is coupled to the zero-crossing detector and is configured to remove the electrical line noise from the composite input signal and output a filtered neural signal that is substantially similar to the input neural signal.
    Type: Grant
    Filed: October 18, 2010
    Date of Patent: January 20, 2015
    Assignee: Blackrock Microsystems, LLC
    Inventors: Ehsan Azarnasab, Erik Alfonso Nilsen
  • Patent number: 8928398
    Abstract: The even order harmonic distortion in a differential circuit is reduced or eliminated by treating the amplitude and phase mismatch sources that cause the distortion as impedance mismatches, and utilizing switched resistor circuitry that adjusts the load resistance to reduce the effects of the amplitude mismatch sources, and switched capacitor circuitry that adds shunt capacitance to reduce the effects of the phase mismatch sources.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: January 6, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Bumha Lee, Yongseon Koh