Abstract: Voltage fluctuations on a power feeding path for feeding power to a motor controller are reduced. A processing apparatus reduces voltage fluctuations on a power feeding path for feeding power from a direct current power supply to at least one motor controller. The apparatus includes a filter circuit and a controller. The filter circuit includes a plurality of predetermined units each including a circuit element and a semiconductor switch. The circuit element includes at least one predetermined passive element. The semiconductor switch controls a current to be fed to the circuit element. The filter circuit is connected to the power feeding path. The controller controls switching of the semiconductor switch included in each of the plurality of predetermined units in the filter circuit to reduce voltage fluctuations or current fluctuations of direct current on the power feeding path.

Abstract: A chip with power-glitch detection is provided, which includes a power terminal receiving power, an inverter, and a back-up power storage device coupled to the power terminal. The inverter has an input terminal coupled to the power terminal. The back-up power storage device transforms the power to back-up power. The inverter is powered by the back-up power when a power glitch occurs on the power terminal, and the power glitch is reflected at an output terminal of the inverter.

Abstract: RF transistor amplifiers include a Group III nitride-based RF transistor amplifier die that includes a semiconductor layer structure, a conductive source via that is connected to a source region of the Group III nitride-based RF transistor amplifier die, the conductive source via extending through the semiconductor layer structure, and an additional conductive via that extends through the semiconductor layer structure. A first end of the additional conductive via is connected to a first external circuit and a second end of the additional conductive via that is opposite the first end is connected to a first matching circuit.

Abstract: A high frequency package includes a package having an input terminal and an output terminal. A substrate housed in the package, has a first side, a second side facing the input terminal, and a third side facing the output terminal. The first side extends in a first direction and connects the second side and the third side, and the second side and the third side extend in a second direction intersecting the first direction. A coupling circuit on the substrate is electrically connected to the input terminal and the output terminal to input an input signal from the input terminal disposed at the second side of the substrate and output an output signal to the output terminal disposed at the third side of the substrate. A filter circuit on the substrate is electrically connected to the coupling circuit, an is configured to reduce third-order IMD (Inter Modulation Distortion) included in the output signal.

Abstract: Methods, systems, and devices for wireless communication are described. A communication device may receive control signaling indicating a downlink reference signal configuration, for example, a demodulation reference signal (DMRS) configuration. The communication device may receive a downlink reference signal (e.g., a DMRS) over a downlink control channel (e.g., a physical downlink control channel (PDCCH)) during an initial symbol duration of a transmission time interval (TTI). The downlink reference signal may include a set of bits including a first subset of bits including network temporary identifier bits and a second subset of bits including constellation bits associated with a downlink data channel (e.g., a physical downlink shared channel (PDSCH)). The communication device may process the downlink reference signal (e.g., a DMRS) based on the downlink reference signal configuration (e.g., a DMRS configuration).

Abstract: A physiological activity detection system comprises a signal acquisition module configured for non-invasively acquiring a signal from an anatomical structure of a user, the acquired signal having a physiological-encoded component and a periodic artifact component that dominates the physiological-encoded component. The physiological activity detection system further comprises a phase-locked loop (PLL) component configured for estimating a phase of the periodic artifact component of the acquired signal, and generating a periodic reference signal having a phase representative of the estimated phase of the periodic artifact component of the acquired signal.

Abstract: A converter circuit, included in a power converter circuit, may generate a given voltage level on a regulated power supply node of a computer system. A control circuit may monitor a voltage level and assert a control signal in response to a determination that a regulation event has occurred. A boost converter circuit, included in the power converter circuit, may inject charge into to the regulated power supply node via a capacitor, in response to an assertion of the control signal.

Abstract: An apparatus includes a main core processor configured to receive a first signal through a first main buffer, a second signal through a second main buffer, a third signal through a third main buffer and a fourth signal through a fourth main buffer, a shadow core processor configured to receive the first signal through a first shadow buffer, the second signal through a second shadow buffer, the third signal through a third shadow buffer and the fourth signal through a fourth shadow buffer, and a first glitch suppression buffer coupled to a common node of an input of the first main buffer and an input of the first shadow buffer.

Abstract: Embodiments of a differential bootstrapped track-and-hold circuit are disclosed. In an embodiment, the differential bootstrapped track-and-hold circuit includes first and second single-ended bootstrapped track-and-hold circuits. Each single-ended bootstrapped track-and-hold circuit includes a sampling switch connected between an input terminal and an output terminal, a sampling capacitor connected to the output terminal, and a dummy sampling switch connected between the input terminal and a dummy output terminal. The sampling switch and the dummy sampling switch are controlled by a bootstrap driver connected to the input terminal.

Abstract: Techniques are provided herein for generating PWM signals. Furthermore, a direct-drive method is disclosed in which a PWM signal is generated as a differential signal made up of OUTP and OUTN signals, where OUTP is a copy of OUTN but shifted in time by half a period. The PWM signal is generated by passing each of an input period and an input duty cycle through corresponding sigma-delta circuits to generate a refined period and a refined duty cycle, respectively. In some example cases, a threshold mapper uses a lookup table (LUT) or similar mechanism to select timing thresholds for rise times and fall times for each of the OUTP and OUTN signals, where the timing thresholds are selected based on the refined period and the refined duty cycle. In some example cases, a pulse generator generates the OUTP and OUTN signals based on the timing thresholds.

Abstract: Tactile interface comprising a panel (1) having an interactive surface (2) with one or a plurality of exterior elements, comprising a plurality of interactive areas (Z1, Z2, Z3, Z4) arranged relative to one another, such that they cover substantially the whole of the interactive surface (2) and a plurality of actuators (A1, A2, A3, A4) in contact with the panel, control means (6) of actuators configured to send control signals to the actuators, comprising means for calculating (8) said control signals, said calculating means (8) executing an inverse filtering operation, so as to emit, from a desired displacement or displacements of one or more interactive areas (Z1, Z2, Z3, Z4), control signals compensating at least partially the distortion, reverberation and propagation of waves.

Abstract: The present invention discloses a power converter controller having a short-circuit protection threshold voltage no higher than an over-current protection threshold voltage so that any abnormal voltage or current stress on semiconductor components can be timely sensed via a current sense pin in the event of a short-circuit fault, effectively preventing semiconductor components from being damaged.

Abstract: An electronic system includes a reception device and a transmission device. The reception device generates reception data from transmission data input to a reception node and includes a termination circuit which is coupled to the reception node to perform an impedance matching operation. The transmission device generates a drive control signal from internal data based on a mode signal and drives the transmission data based on the drive control signal.

Abstract: A device includes a first die and a second die. The first die includes: a first substrate that contains first electrical circuitry, a first interconnection structure disposed over the first substrate, a first dielectric layer disposed over the first interconnection structure, and a plurality of first bonding pads disposed over the first dielectric layer. The second die includes: a second substrate that contains second electrical circuitry, a second interconnection structure disposed over the second substrate, a second dielectric layer disposed over the second interconnection structure, and a plurality of second bonding pads disposed over the second dielectric layer. The first bonding pads of the first die are bonded to the second bonding pads of the second die. At least one of the first die or the second die includes a metal-insulator-metal (MIM) capacitor. The MIM capacitor includes more than two metal layers that are stacked over one another.

Abstract: A circuit interrupting device including one or more line terminals for connecting to an external power supply, one or more load terminals for connecting to an external load, one or more contacts electrically connecting one or more line terminals to one or more load terminals; and an auto-monitoring circuit. The auto-monitoring circuit continuously monitoring one or more signals to determine an operating state of said circuit interrupting device. Wherein if said auto-monitoring circuit determines that said circuit interrupting device has reached its end-of-life and it is determined that the contacts have not failed, then a signal is driven to a first level to actuate a switch and open the contacts. Wherein said signal is further driven to a second level to inhibit said circuit interrupting device from resetting when it is determined that contacts of said interrupting device have failed. Wherein the second level has a voltage greater than zero volts.

Abstract: The nonlinearity of power amplifiers (PAs) has been a severe constraint in performance of modern wireless transceivers. This problem is even more challenging for the fifth generation (5G) cellular system since 5G signals have extremely high peak to average power ratio. Nonlinear equalizers that exploit both deep neural networks (DNNs) and Volterra series models are provided to mitigate PA nonlinear distortions. The DNN equalizer architecture consists of multiple convolutional layers. The input features are designed according to the Volterra series model of nonlinear PAs. This enables the DNN equalizer to effectively mitigate nonlinear PA distortions while avoiding over-fitting under limited training data. The non-linear equalizers demonstrate superior performance over conventional nonlinear equalization approaches.

Abstract: A method to cancel amplitude modulation noise (contamination) of an input (carrier) signal, including: receiving an input monochromatic signal contaminated with amplitude modulation noise; demodulating the amplitude modulation noise to generate a baseband amplitude modulation noise signal; signal processing the baseband amplitude modulation noise signal to generate an amplitude modulation noise cancelation signal; and amplitude modulating the input signal based on the amplitude modulation noise cancelation signal to generate an output signal, the output signal having less amplitude modulation noise than the input signal. A feedforward implementation can use signal inversion to generate a feedforward amplitude modulation noise cancelation signal. A feedback implementation, implemented with a gain controlled amplifier, can be based on, in a feedback path, demodulating the amplitude noise modulation signal in a feedback gain-controlled input signal to generate a feedback gain control signal.

Abstract: A time-interleaved digital-to-analog converter system, comprising a digital pre-distorter configured to receive an input digital signal and an error signal and output a distorted digital signal based on the input digital signal and the error signal; a time-interleaved digital-to-analog converter having a first sample rate, the time-interleaved digital-to-analog converter configured to convert the distorted digital signal to an analog signal; and a calibration system. The calibration system includes an analog-to-digital converter having a second sample rate equal to or lower than the first sample rate, the analog-to-digital converter configured to receive the analog signal and covert the analog signal to a down-sampled digital signal, a discrete-time linear model configured to receive the input digital signal and the error signal and output a model signal, and a combiner to subtract the down-sampled digital signal from the model signal to generate the error signal.

Abstract: A computer-implemented method of estimating IQ imbalance in a communication system including a transmitter and a receiver. The method includes: defining a system model in which a transmitted signal is affected by TX IQ imbalance, carrier frequency offset (CFO) and RX IQ imbalance; controlling a local oscillator at the transmitter to introduce a known carrier frequency offset (CFO) during a calibration; and estimating unknown parameters in the system model using a pre-defined training sequence to determine the TX IQ imbalance and the RX IQ imbalance.

Abstract: A head-mounted display device with which a user can visually recognize a virtual image and an outside scene includes an image display unit configured to cause the user to visually recognize the virtual image, an augmented-reality processing unit configured to cause the image display unit to form the virtual image including a virtual object, at least a part of which is superimposed and displayed on a real object present in the real world, a color detecting unit configured to detect a real object color, which is a color of the real object, and a color adjusting unit configured to bring a visual observation color, which is a color obtained by superimposing a color of the virtual object on the real object color, close to a target color using the detected real object color.

Abstract: An input/output apparatus of a multiplexer is provided, including: a main tap and at least two branch taps of the main tap, where each of the at least two branch taps is configured to couple to a different resonant cavity in the multiplexer, and the at least two branch taps include a first branch tap and a second branch tap; a coupling polarity of the first branch tap is opposite to that of the second branch tap; and a coupling calculation frequency of the second branch tap is closest to a coupling calculation frequency of the first branch tap. The input/output apparatus of the multiplexer enables two channels with closest frequencies to use different coupling polarities. Because the coupling polarities are different, signals naturally do not interfere with each other, and signal interference between channels is eliminated in principle. The embodiments of the present disclosure further provide a corresponding multiplexer.

Abstract: Systems and methods for combining signals from multiple active wireless receivers are discussed herein. An exemplary system comprises a first downconverter, a phase comparator, a phase adjuster, and a second downconverter. The first downconverter may be configured to downconvert a received signal from a first antenna to an intermediate frequency to create an intermediate frequency signal. The phase comparator may be configured to mix the received signal and a downconverted signal to create a mixed signal, compare a phase of the mixed signal to a predetermined phase, and generate a phase control signal based on the comparison, the downconverted signal being associated with the received signal from the first antenna. The phase adjuster may be configured to alter the phase of the intermediate frequency signal based on the phase control signal. The second downconverter may be configured to downconvert the phase-shifted intermediate frequency signal to create an output signal.

Abstract: An electronic circuit may include a driver, a delay circuit, a strength control circuit, and an adder circuit. The driver may generate a second signal based on a first signal. The delay circuit may delay the first signal by as much as a reference time, to generate a third signal. The strength control circuit may adjust an amplitude of the third signal to generate a fourth signal. The adder circuit may add the second signal and the fourth signal to generate a fifth signal. In a first time interval determined based on the reference time, an amplitude of the fifth signal may be greater than an amplitude of the second signal. In a second time interval except for the first time interval, the amplitude of the fifth signal may be smaller than the amplitude of the second signal. In the second time interval, the amplitude of the fifth signal may be smaller than an amplitude of the first signal.

Abstract: A time interleaved digital to analog converters (TIDACs) system having a pre-processing filter to filter a digital signal prior to being converted by a respective digital-to-analog converter (DAC) of the TIDACs system to correct for mismatches between the DACs of the TIDACs system. Calibrating the pre-processing includes converting a discrete waveform at a first DAC to a first analog signals and at a second DAC to a second analog signal and combining the first and second analog signals into a combined signal. An analog-to-digital converter (ADC) converts the combined signal to a digital signal to determine an actual frequency response of the TIDACs system. A desired frequency response of the TIDACs system is received and a pre-processing filter is generated for the first DAC and the second DAC based on the actual frequency response of the TIDACs system and the desired frequency response of the TIDACs system.

Abstract: A probe module, which supports loopback test and is provided between a PCB and a DUT, includes an adapter, two probes, two inductive components provided at the adapter, and a capacitive component. The adapter has two connecting circuits. An end of each of the probes is connected to one of the connecting circuits, while another end thereof, which is a tip, contacts the DUT. Each of the inductive components has an end electrically connected to one of the connecting circuits, and another end electrically connected to the PCB through a conductive member, which is provided at the adapter, wherein two ends of the capacitive component are electrically connected to one of the connecting circuits, respectively. Whereby, the signal paths are changed by the differences between frequencies of signals, and the transmission path of high-frequency signals is effectively shortened.

Abstract: A circuit described herein includes a charge to voltage converter circuit having an input coupled to receive a sense signal from a sense node associated with a mutual capacitance to be sensed, and an output. A reset switch is coupled between the output of the charge to voltage converter circuit and the input of the charge to voltage converter. An accumulator circuit is configured to accumulate voltages at the output of the charge to voltage converter circuit and to generate an accumulator output signal. Control circuitry is configured to generate control signals for the reset switch and accumulator circuit so as to reduce noise in the accumulator output signal.

Abstract: A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.

Abstract: A method and a device for predictive evaluation of intermodulation power in an electronic device in which a predictive function f makes it possible to evaluate in a predictive manner values of power of an intermodulation component produced by an intermodulation distortion of an input signal, characterized in that the predictive function f includes an odd part V obtained by multiplication of an odd function F and of a function G, obtained by composition of a positive real-valued even function g and of a function Q in the form of a real series including at least one term of degree q belonging to the non-integer reals.

Abstract: A noise suppression device includes an estimating unit that estimates, from a feature quantity representing the feature in each frequency range of a first acoustic signal which represents sound, the noise component of the feature quantity; a calculating unit that calculates, from the feature quantity and the noise component for each frequency range, a first suppression coefficient to be used in suppressing noise included in the first acoustic signal; a first attenuating unit that attenuates the first suppression coefficient in the time domain and calculates a second suppression coefficient; a second attenuating unit that attenuates the second suppression coefficient in the frequency domain and calculates a third suppression coefficient; and a generating unit that estimates, from the feature quantity and the third suppression coefficient, a voice component of the feature quantity and generates a second acoustic signal in which the noise included in the first acoustic signal is suppressed.

Abstract: Systems and methods for evaluating a cement installation are provided. In one example, the cement may be evaluated using a casing arrival measurement sensor that measures casing arrival signals resulting from firing a signal from a cement bond logging acoustic source. External signals (e.g., signals other than the casing arrival signals) may be attenuated by firing an attenuation firing signal.

Abstract: A method includes bonding a die to a substrate, where the substrate has a first redistribution structure, the die has a second redistribution structure, and the first redistribution structure is bonded to the second redistribution structure. A first isolation material is formed over the substrate and around the die. A first conductive via is formed, extending from a first surface of the substrate, where the first surface is opposite the second redistribution structure, the first conductive via contacting a first conductive element in the second redistribution structure. Forming the first conductive via includes patterning an opening in the substrate, extending the opening to expose the first conductive element, where extending the opening includes using a portion of a second conductive element in the first redistribution structure as an etch mask, and filling the opening with a conductive material.

Abstract: A device generates, in a container box of a file for storage of video contents, a SampleGroupDescription box that provides a sample group description for a sample grouping. The SampleGroupDescription box includes a grouping type syntax element having a particular value. Additionally, the SampleGroupDescription box includes one or more sample group entries. The device generates, in the same container box, a plurality of SampleToGroup boxes. Each respective SampleToGroup box of the plurality of SampleToGroup boxes includes a respective grouping type syntax element having the particular value, includes a respective sample count syntax element indicating a number of samples in a respective sample grouping, and includes a respective group description index syntax element indicating an index of an entry in the SampleGroupDescription box which describes samples of the respective sample grouping. Each sample of the respective sample grouping comprises a respective picture of the video contents.

Abstract: A detection apparatus according to an embodiment includes an acquisition unit, a calculation unit, and a detection unit. The acquisition unit acquires, via an antenna positioned on a movable body, data on which signal groups with different base frequencies are superimposed. The calculation unit calculates, based upon a frequency spectrum of the data acquired by the acquisition unit, the base frequencies of the respective signal groups. The detection unit detects signals in the respective signal groups based upon the base frequencies calculated by the calculation unit.

Abstract: Aspects of the disclosure provide a circuit for providing a power supply. The circuit includes a control signal generator circuit and a switch network circuit. The control signal generator circuit is configured to generate a control signal with a voltage level that is a function of an output voltage on a load capacitor. The switch network circuit is coupled with the load capacitor and a flying capacitor to form a charge pump circuit. The switch network circuit is configured to charge the flying capacitor in a charge stage and pump the flying capacitor in a pump stage to generate the output voltage on the load capacitor. The switch network circuit is configured to provide a pump control voltage to the flying capacitor during the pump stage. The pump control voltage has a voltage level that is adjusted based on the control signal to maintain the output voltage to be stable.

Abstract: A digital frontend circuit for a radio frequency (RF) comprises a digital predistortion (DPD) block, a plurality of sub-sample delay elements, and a selection circuit. The DPD block for computing predistorted transmit signals according to a Volterra series approximation model. The DPD block has an input for receiving input samples at a first sample rate and an output for providing the predistorted transmit signals at the first sample rate. Each of the sub-sample delay elements provides a delay to an input sample as specified by the Volterra series approximation model, where each of the delays is based on a fraction of the first sample rate. The selection circuit selects one of the plurality of sub-sample delay elements in response to a selection signal from the digital predistortion block. The selection signal for selecting a delay as specified by the Volterra series approximation model.

Abstract: A digital filter for filtering an input signal to form an output signal containing a coefficient multiplier and a moving-average filter. The coefficient multiplier is embodied to multiply values of the input signal by coefficients of the filter to form an intermediate signal. The moving-average filter is embodied to generate the output signal as a moving average of the intermediate signal.

Abstract: A method of calibrating coefficients of a calibrated decision feedback equalizer (DFE) across a process, voltage, and temperature (PVT) range, the calibrated DFE comprising a plurality of DFE taps for reducing distortions of an input signal, and a sampler for sampling the input signal, the method including applying a preset voltage to an input of the calibrated DFE, setting a DFE tap of the plurality of DFE taps to a maximum value, generating a source reference, via a source reference calibrator, to apply to the DFE tap, changing the source reference to a first level that causes an output of the sampler to transition from a first state to a second state, determining the first level as a calibrated source reference, and applying the calibrated source reference to the DFE tap during normal operation of the calibrated DFE.

Abstract: A system and method mitigate the effects of these external vibrations on a capacitance diaphragm gauge by sensing the motion of the diaphragm at the first natural frequency of the diaphragm of the CDG. The presence of the natural frequency signals superimposed on the pressure signal is determined by sensing variations in the output of a sensor at or near the known natural frequency of the diaphragm and filtering that known low frequency from the output. The filtered signal is used in a feedback circuit to impose electrostatic forces on the diaphragm. The imposed electrostatic forces oppose the motion created by the external vibration to suppress the effects of the vibration on the pressure measured by the CDG.

Abstract: A method of rejecting impulsive noise in an OFDM receiver is described. The impulsive noise is rejected using channel state information (CSI) and is performed in the frequency domain. A noise power estimate (furthermore referred to as a noise value) is measured for a single OFDM symbol and compared to a threshold value, which may be generated based on a short-term average of OFDM symbols not corrupted by impulsive noise or predicted based on a small number of previously measured OFDM symbols not corrupted by impulsive noise. If the noise estimate for the particular OFDM symbol exceeds the threshold value, the CSI for that symbol is derated (i.e. modified) to reduce the influence of the information from this symbol on the decoding process.

Abstract: A current-mode switch-mode power supply controller includes a switch controller, a falling edge detector, and leading edge blanking (LEB) time logic. The switch controller is arranged to control regulation of an output signal via current-mode regulation by turning a primary switch on and off based on a current sense (CS) signal and an LEB signal, such that the switch controller is arranged to cause the primary switch to remain on while the LEB time signal is asserted. The falling edge detector is arranged to detect a falling edge in the CS signal. The LEB time logic is arranged to provide the LEB time signal such that the assertion of the LEB time signal begins when a gate signal is asserted, and such that the assertion of the LEB time signal ends when the falling edge detector detects the falling edge in the CS signal.

Abstract: A standard cell IC may include a plurality of pMOS transistors each including a pMOS transistor drain, a pMOS transistor source, and a pMOS transistor gate. Each pMOS transistor drain and pMOS transistor source of the plurality of pMOS transistors may be coupled to a first voltage source. The standard cell IC may also include a plurality of nMOS transistors each including an nMOS transistor drain, an nMOS transistor source, and an nMOS transistor gate. Each nMOS transistor drain and nMOS transistor source of the plurality of nMOS transistors are coupled to a second voltage source lower than the first voltage source.

Abstract: A processing device detects an occurrence of the first set of use conditions associated with a power supply line coupled between a power source and a power sink in a user device. The processing device sets a tunable decoupling capacitor on the power supply line to a first capacitance value to reduce a level of electromagnetic interference on the power supply line at a first frequency corresponding to the first capacitance value. When the processing device detects a change from the first set of use conditions associated with the power supply line to a second set of use conditions, the processing device sets the tunable decoupling capacitor to a second capacitance value to reduce a level of electromagnetic interference on the power supply line at a second frequency corresponding to the second capacitance value.

Abstract: There is provided a sampling point adjustment apparatus including: a frequency conversion unit that converts a first signal and a second signal into a first narrow band signal and a second narrow band signal through frequency conversion; a central position determination unit that determines a central position of a window of the frequency conversion for the second signal based on an estimated value of a sampling interval offset between the first narrow band signal and the second narrow band signal; and a phase control unit that controls a phase of the second narrow band signal based on the estimated value.

Abstract: In one embodiment, an RF generator includes an RF amplifier that includes an RF input, a DC input, and an RF output, the RF amplifier configured to receive at the RF input an RF signal from an RF source; receive at the DC input a DC voltage from a DC source; and provide an output power at the RF output; and a control unit operably coupled to the DC source and the RF source, the control unit configured to receive a power setpoint for the RF output; determine a power dissipation at the RF generator; and alter the DC voltage to a final DC voltage that decreases the power dissipation at the RF generator while enabling the output power at the RF output to be substantially equal to the power setpoint.

Abstract: An electronic equipment includes a control unit, an EMI frequency storage unit, and a settable range detection unit. The EMI frequency storage unit stores respective frequencies of EMI noise components in ones of driving pulse signals, which are transmitted from the control unit to other modules than a display module in association with the other modules. The settable range detection unit detects a settable range of the frequency of one of the driving pulse signals, which is transmitted from the control unit to the display unit. When transmitting the driving pulse signal to the display module, the control unit sets, as the frequency of the driving pulse signal to the display module, a frequency that is a frequency excluding the frequencies of the EMI noise components stored in association with the other modules that are being driven and also is a frequency in the settable range that has been detected.

Abstract: A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.

Abstract: A correlated double sampling (CDS) circuit may include a sampling circuit and a switching circuit. The CDS circuit may perform a CDS operation on a reset component of an input signal and an image component of the input signal based on a ramp signal, and the CDS circuit may generate an output signal. The switching circuit may include an auto-zero switch that connects a first input terminal receiving the input signal to an output node in response to an auto-zero control signal during an auto-zero interval. The switching circuit may connect a first terminal of the auto-zero switch to a reference voltage in order to cutoff a leakage current flowing to the auto-zero switch in response to a first boosting control signal during a first comparison interval and a second comparison interval. The output signal may be provided at the output node.

Abstract: An electronic system may include a first circuit driven by a first power voltage signal and a first ground voltage signal, and a second circuit driven by a second power voltage signal and a second ground voltage signal. The electronic system may also include a stabilizer coupled between a first ground terminal and a second ground terminal and suitable for blocking a current flowing from the second ground terminal toward the first ground terminal.

Abstract: Systems, methods, apparatuses, and computer program products for interference cancelation are provided. One method includes forming, by a wireless system, a signal structure to match a structure of an interfering signal with repetitive time structure. The method may further include using the formed signal structure to eliminate interference caused by the interfering signal. The signal structure includes parts that are synchronized with the repeated parts of the interfering signal structure to cancel the repetition of the interference, and the signal structure further comprises another part synchronized with the non-repeated parts of the interference signal.

Abstract: A fractional-N phase-locked loop (PLL) includes a nonlinear time to digital converter that generates a digital representation of a phase error corresponding to a time difference between a feedback signal of the fractional-N PLL and a reference signal. A nonlinear quantization noise cancellation circuit supplies a correction signal to ensure that the generated digital representation has reduced quantization noise. The correctional signal may be applied in the analog or digital domain.