Abstract: Various aspects provide for error detection and compensation for a multiplexing transmitter. For example, a system can include an error detector circuit and a duty cycle correction circuit. The error detector circuit is configured to measure duty cycle error for a clock associated with a transmitter to generate error detector output based on a clock pattern for output generated by the transmitter in response to a defined bit pattern. The duty cycle correction circuit is configured to adjust the clock associated with the transmitter based on the error detector output. Additionally or alternatively, the error detector circuit is configured to measure quadrature error between an in-phase clock and a quadrature clock in response to the defined bit pattern. Additionally or alternatively, the system can include a quadrature error correction circuit configured to adjust phase shift between the in-phase clock and the quadrature clock based on quadrature error.

Abstract: A device may include a first set of electrodes, a second set of electrodes that is transverse the first set, and at least one connection between an electrode in the first set to an electrode in the second set by a high pass filter. The connected electrode(s) in the first set and the connected electrode(s) in the second set may form an antenna. The device may include a processor and memory. The memory may store programmed instructions which cause the processor, when executed, to transmit a wireless signal using the connected electrodes during a first time, and measure a capacitance signal using electrodes in the first set and electrodes in the second set during a second time.

Abstract: A DC offset filter for wide band beamforming receivers is disclosed. In an exemplary embodiment, an apparatus includes a first mixer configured to down-convert an RF wideband beamformed signal to generate a first baseband wideband beamformed signal, the RF wideband beamformed signal having a beam pattern selected from a plurality of beam patterns, and a notch filter configured to remove DC offset from the first baseband wideband beamformed signal independent of the beam pattern.

Abstract: A bandpass sense amplifier circuit (FIG. 2A) is disclosed. The circuit includes a capacitor (C0) having a first terminal coupled to receive an input signal (Vin) and a second terminal. A current conveyor circuit (200-206,212) has a third terminal (X) coupled to the second terminal of the capacitor and a fourth terminal (Z) arranged to mirror a current into the third terminal. A voltage follower circuit (214) has an input terminal coupled to the fourth terminal of the current conveyor circuit and an output terminal.

Abstract: A programmable variable admittance circuit may be used in a programmable filter or a variable gain amplifier in a number of different applications including tuners and other RF receiver circuits. A variable admittance circuit and operation is described including a number of switchable admittance elements arranged in parallel branches. The variable admittance circuit requires fewer transitions to change between successive admittance values than a binary weighted circuit and fewer branches for implementation then a thermometry admittance circuit.

Abstract: A clock generator is disclosed for use with an oscillator device. The clock generator may include a signal conditioning pre-filter and a comparator. The signal conditioner may have an input for a signal from the oscillator device, and may include a high pass filter component and a low pass filter component. The high pass filter component may pass amplitude and frequency components of the input oscillator signal but reject a common mode component of the oscillator signal. Instead, the high pass filter component further may generate its own common mode component locally over which the high frequency components are superimposed. The low pass filter component may generate a second output signal that represents the locally-generated common mode component of the first output signal. The clock generator may have a comparator as an input stage which is coupled to first and second outputs of the filter structure.

Abstract: A filter provides high-pass coupling between circuits. The filter includes charge storage elements and switch elements coupling the charge storage elements. A controller is coupled to the switch elements for sequencing configurations of the switch elements in phases for each of a succession of sample periods to perform a time sampled continuous value signal processing of the input signal to form the processed signal. The sequenced configurations include a configuration in which a charge representing a value of the input signal is stored on a multiple of the charge storage elements, a configuration in which charge storage elements are coupled with the switch elements, and a set of one or more configurations that implement a scaling of a charge on one of the charge storage elements to be on one or more of the charge storage elements.

Abstract: Apparatus and methods are disclosed, such as those involving a receiver device. One such apparatus includes an equalizer configured to process an input signal transmitted over a channel. The equalizer includes a first node configured to receive the input signal; a second node; and a programmable gain amplifier (PGA) having an adjustable gain. The PGA has an input electrically coupled to the first node, and an output electrically coupled to a third node. The equalizer also includes a high pass filter (HPF) having an input electrically coupled to the third node, and an output electrically coupled to the second node; and a control block configured to adjust one or more of the PGA or the HPF at least partly in response to a PGA output signal from the PGA or an HPF output signal from the HPF.

Abstract: An apparatus comprising an input circuit, a cross coupled active circuit and an output circuit. The input circuit may be configured to generate a first portion of an intermediate signal in response to an input signal. The cross coupled active circuit may be configured to generate a second portion of the intermediate signal in response to a feedback of an output signal. The output circuit may be configured to generate the output signal in response to the intermediate signal. The output signal may pass frequencies above a target frequency.

Abstract: A band pass filter has a high pass filter into which an input signal is input; an amplifier having an inverting input terminal into which an output of the high pass filter is input, wherein the amplifier amplifies an input voltage between the inverting input terminal and a non-inverting input terminal and outputs an output signal to an output terminal; a first resistor connected between a non-inverting output terminal and the inverting input terminal of the amplifier; a first capacitor having a first terminal that is connected to the inverting input terminal; and an inverting amplifier that inverts a polarity of an output signal from the non-inverting output terminal of the amplifier and outputs the inverted signal to a second terminal of the capacitor.

Abstract: The device described herein proposes an electronic active filter void of capacitors and inductors. The circuit utilizes only operational amplifiers (OP-Amp) and resistors, hence the name Op-R. Although capable of being constructed of lumped circuit elements this filter is intended for integrated circuit (IC) applications. Filtering of signals can be accommodated from dc through the UHF frequency range depending on the selected op-amp ICs. Low pass, band pass, high pass, as well as band reject frequency responses are achievable. Although the circuits described herein are single input-single output, multiple inputs and outputs present no difficulty, being limited only chip space. Temperature and production spread variations are also considered within the realm of tenability.

Abstract: A filter network having a variable cut-off frequency can be controlled in a way that allows the cut-off frequency to be changed gradually to avoid undesirable transient effects. An impedance network (such as a resistor network) that provides a plurality of impedance values is provided. Logic, and a corresponding method, are provided to change the impedance value gradually, such as on a step-wise basis, to change the cut-off frequency gradually. The size of the impedance step and the duration of the step can be preprogrammed, and may be different for different types of events that trigger the need for a frequency change. It may also be possible for those preprogrammed values to be initial values only, with the values changing under programmed control during the frequency changing process. Other values, such as the initial and target impedance values that determine the initial and target frequency, also may be programmable.

Abstract: A high frequency circuit device includes: two transmission lines having ends which are opposed to each other and are spaced from each other; a capacitor that is mounted on the end of one of the two transmission lines and has a lower face electrode acting as a mount face and an upper face electrode positioned higher than the lower face electrode; a resistor element that is provided on a region between the ends of the two transmission lines and connects the ends of the two transmission lines; and a connection conductor electrically connecting the upper face electrode of the capacitor and the other of the two transmission lines.

Abstract: An apparatus comprising an input circuit, a cross coupled active circuit and an output circuit. The input circuit may be configured to generate a first portion of an intermediate signal in response to an input signal. The cross coupled active circuit may be configured to generate a second portion of the intermediate signal in response to a feedback of an output signal. The output circuit may be configured to generate the output signal in response to the intermediate signal. The output signal may pass frequencies above a target frequency.

Abstract: An active RC resonator includes a first operational amplifier having first and second inputs and first and second outputs, a second operational amplifier having first and second inputs and first and second outputs, a first resistor coupled between the first input of the first operational amplifier and the second output of the second operational amplifier, a second resistor coupled between the second input of the first operational amplifier and the first output of the second operational amplifier, a third resistor coupled between the first output of the first operational amplifier and the first input of the second input of the second operational amplifier, a fourth resistor coupled between the second output of the first operational amplifier and the second input of the second operational amplifier, and at least one of 1) a first capacitor coupled between the first input of the first operational amplifier and the first output of the second operational amplifier, and a second capacitor coupled between the second

Abstract: A switch for an analog signal may include a main MOS transistor whose source forms an input terminal of the switch and whose drain forms an output terminal of the switch, a capacitor having a first terminal permanently connected to the source of the main transistor, a circuit for charging the capacitor, and a first auxiliary transistor configured to connect the second terminal of the capacitor to the gate of the main transistor in response to a control signal. The charge circuit may include a resistor permanently connecting the second terminal of the capacitor to a power supply line. The capacitor and the resistor may form a high-pass filter having a cutoff frequency lower than the frequency of the analog signal.

Abstract: A relaxation oscillator for generating a first and a second oscillation signals, comprising: a reference-voltage providing circuit for providing a high and a low reference voltages; switches for directing the high and low reference voltages to inputs of a transconductance amplifier and a non-inverting input of a comparator; the transconductance amplifier for generating an output current with a value determined by its transconductance value, controlled by an input tuning voltage, and multiplied by its inputs' voltage difference; a capacitor connecting between the transconductance amplifier output and ground; and the comparator for generating a first and a second digital signals; wherein the first and second digital signals are digital control signals to the switches, and the first and second oscillation signal of the relaxation oscillator respectively; wherein the oscillation frequency of the relaxation oscillator is independent of the reference voltages, achieving accurate frequency turning, and simplifying t

Abstract: An equalization circuit includes a first differential amplifier having first and second transistors, and a first differential high-pass filter coupled to respective gate terminals of the first and second transistors. A source terminal of the first transistor is coupled to a first input node, and a source terminal of the second transistor is coupled to the second input node. The equalization circuit further includes a second differential amplifier having third and fourth transistors, and a second differential high-pass filter coupled to respective gate terminals of each of the third and fourth transistors. A source terminal of the third transistor is coupled to the first input node, and a source terminal of the second transistor is coupled to the second input node. Using such a circuit, continuous time decision feedback equalization may be performed.

Abstract: An adjustable equalizer that includes a first branch including a low pass filter (LPF) and having a variable gain (?), and a second branch including a high pass filter (HPF) and having another variable gain (?). The equalizer can be implemented using CMOS technology so that the gain parameters ? and ? are independently adjustable and the equalizer is capable of equalizing an input indicative of data having a maximum data rate of at least 1 Gb/s. In some embodiments, the equalizer includes two differential pairs of MOS transistors and a controllable current source determines the tail current for each differential pair. When the equalizer includes purely resistive impedances Z0 and Z1, the equalizer's transfer function is Z1/Z0·(?+?·(1+s·C0·Z0)), where ? is a gain parameter determined by the tail current of one differential pair and ? is a gain parameter determined by the tail current of the other differential pair.

Abstract: A transmitting and receiving circuit includes a transmitting side amplifier circuit amplifying a transmission signal transmitted from an antenna, a receiving side amplifier circuit amplifying a reception signal received by the antenna and being electrically connected to the a transmitting side amplifier circuit, a first matching circuit matching the antenna and the transmitting side amplifier circuit, a second matching circuit matching the antenna and the receiving side amplifier circuit, a first current source circuit capable of controlling an operating state and setting a first connection point between the first matching circuit and an output terminal of the transmitting side amplifier circuit to a given voltage, and a second current source circuit capable of controlling an operating state and setting a second connection point between the second matching circuit and an input terminal of the receiving side amplifier circuit to a given voltage.

Abstract: Device for providing electrical signals with high immunity to noise. The invention develops a device for processing electrical signals (100) coming from a measurement sensor (60), said sensor (60) being subjected to noise disturbances caused by radio interference and lightning effects, such that said device uses a single current-loop cable (70), through which passes the electrical signal (100) encoded according to the signal time (Ta) and repetition time (Tr) of the current wave of said signal (100), such that said signal (100) contains an upper current state (10) and a lower current state (20) whose values are outside the decision window that activates a reading device (4) in the device, which reads the electrical signal (100) coming from the sensor.

Abstract: An equalization circuit is disclosed. The equalization circuit includes a first differential amplifier having first and second transistors, and a first differential high-pass filter coupled to respective gate terminals of the first and second transistors. A source terminal of the first transistor is coupled to a first input node, and a source terminal of the second transistor is coupled to the second input node. The equalization circuit further includes a second differential amplifier having third and fourth transistors, and a second differential high-pass filter coupled to respective gate terminals of each of the third and fourth transistors. A source terminal of the third transistor is coupled to the first input node, and a source terminal of the second transistor is coupled to the second input node. Using such a circuit, continuous time decision feedback equalization may be performed.

Abstract: A high pass filter has a cutoff frequency. The high pass filter includes a first amplifier to receive an input signal. The high pass filter attenuates low frequency signals of the input signal that are below the cutoff frequency. A second amplifier provides an output signal. The output signal comprising only high frequency signals of the input signal that are above the cutoff frequency. A capacitive element is coupled in between the first amplifier and the second amplifier. A variable frequency module controls a plurality of resistive paths of the high pass filter. Each resistive path corresponds to a different cutoff frequency for the high pass filter. The variable frequency module is configured to prevent any leakage current from draining the capacitive element.

Abstract: An adjustable equalizer that includes a first branch including a low pass filter (LPF) and having a variable gain (?), and a second branch including a high pass filter (HPF) and having another variable gain (?). Outputs of the branches in response to an input signal are summed to produce an equalized output. The equalizer can be implemented using CMOS technology so that the gain parameters ? and ? are independently adjustable and the equalizer is capable of equalizing an input indicative of data having a maximum data rate of at least 1 Gb/s. Typically, the inventive equalizer is embodied in a receiver for use in equalizing a signal, indicative of video or other data, that has propagated over a serial link to the receiver.

Abstract: A transceiving system utilizing a shared filter module is provided. The shared filter module is selectively filtering signals in a first band in a first mode and a second band in a second mode. The first mode is a receiver mode whereas the second mode is a transmission mode. The shared filter module comprises a compound filter comprising two low pass filters and a coupling controller to manage input and output wiring of the low pass filters. When the coupling controller is enabled in the first mode, the compound filter acts as a bandpass filter. When the coupling controller is disabled, the compound filter acts as two independent low pass filters.

Abstract: An active low-pass current filter apparatus and method reduces conducted emissions above a predefined cutoff frequency at high power levels. The apparatus and method use a bidirectional DC-DC converter to minimize current fluctuations on a power lead that may result in conducted emissions above the predefined cutoff frequency. The bidirectional DC-DC converter absorbs current from the power lead and feeds current to the load lead as needed to compensate for the current fluctuations on the power lead. Power to the DC-DC converter is provided by a separate auxiliary power source. A monitoring circuit compares the voltage level of the auxiliary power source to a reference voltage and compensates for variations in the voltage level of the auxiliary power source without interfering with the suppression of the conducted emissions.

Abstract: The present invention discloses a circuit for settling DC offset and controlling RC time-constant in a direct conversion receiver. The circuit includes a variable resistive unit for providing a continuously or non-continuously variable resistance in the direct conversion receiver. The variable resistive unit can provide the variable resistance by utilizing a controllable transistor or a plurality of resistors. Accordingly, the variable resistive unit can be coupled to a capacitor for constituting a high pass filter, which is capable of rapidly settling DC offset in a direct conversion receiver.

Abstract: The device described herein proposes an electronic active filter void of capacitors and inductors. The circuit utilizes only operational amplifiers (OP-Amp) and resistors, hence the name Op-R. Although capable of being constructed of lumped circuit elements this filter is intended for integrated circuit (IC) applications. Filtering of signals can be accommodated from dc through the UHF frequency range depending on the selected op-amp ICs. Low pass, band pass, high pass, as well as band reject frequency responses are achievable. Although the circuits described herein are single input-single output, multiple inputs and outputs present no difficulty, being limited only chip space. Temperature and production spread variations are also considered within the realm of tunability.

Abstract: A high pass filter chip with a large size capacitor is disclosed. The high pass filter chip includes a fully-differential sensing device circuit. The fully differential sensing device circuit includes a first amplifier circuit, a second amplifier circuit, and a miller capacitor module including a third amplifier. The first amplifier circuit includes a first transistor and a second transistor, in which the base of the first transistor is coupled to the base of the second transistor. The second amplifier circuit includes a third transistor and a fourth transistor, in which the base of the third transistor is coupled to the base of the fourth transistor. A first input terminal of the third amplifier is coupled to the base of the second transistor of the first amplifier circuit, and a second terminal of the amplifier is coupled to the base of the third transistor of the second amplifier circuit.

Abstract: A digital signal detector detects digital signals by only sensing the rising and falling edges of a received digital signal and latches the logic state between the detected edges. Such edges contain very high frequencies that are much higher than the fundamental frequency of the digital signal train. A small high pass filter filters out at least the DC component and the fundamental frequency of the received digital signal. A filtered edge appears as a spike that goes either positive or negative depending on whether the edge is a rising or falling edge. A memory element, such as comprising an RS flip flop, is triggered by the positive and negative spikes. A positive spike triggers the flip flop to output a logical one, and a negative spike triggers the latch to output a logical zero. In this way, the digital signal is recreated without the original digital signal itself being required to pass through the high pass filter.

Abstract: A method and a system for reducing a dynamic offset during the processing of asymmetric signal strings includes reducing a dynamic offset which allows a reduction of any disturbing influence on subsequent process steps. In every no-pulse period a capacitor is discharged by an amount depending on the value of the amplitude of the voltage of the high-pass structure on the input side.

Abstract: Disclosed are a circuit and a method for tuning a programmable filter including input terminals, output terminals, a filter network and a transadmittance stage. The input terminals can receive input signals, and the output terminals output a filtered signal. The transadmittance stage, coupled to the input terminals, generates a current at its output based on the input signals. The output of the transadmittance stage can be coupled to the output terminals. The filter network can be a resistive-capacitive network connected to the input terminals. The RC network can include a capacitance respectively coupling the input terminals to output terminals, and a voltage divider network coupling the input and output terminals together. The transadmittance stage output terminals can be connected to the voltage divider, and the output terminals of the programmable filter circuit are coupled to respective intermediate nodes of the voltage divider network to provide a filtered output signal.

Abstract: The present invention sets forth a controllable resistive circuit which comprises a transistor, a capacitor, a charging unit and a discharging unit. The transistor is capable of providing a variable resistance which is controlled to vary continuously and smoothly. The charging and discharging units are used to respectively charge and discharge the capacitor in different periods. As a result, the capacitor can provide a variable voltage which is controlled to vary continuously and smoothly to control the equivalent resistance of the transistor during the period the capacitor is discharging. Therefore, the controllable resistive circuit in accordance with the present invention is capable of being used in any kind of circuit which requires a variable resistance varied continuously and smoothly.

Abstract: Low flicker noise mixer and buffer. This design employs some native metal oxide semiconductor field-effect transistors (MOSFETs) (e.g., having no threshold voltage) within a passive mixer whose gates are driven using clock signals. These native MOSFETs maybe biased at one half of the power supply voltage to provide a lower noise figure. A cooperatively operating buffer employs appropriately places MOSFETs and resistors to ensure the desired gain. Relatively larger valued resistors can be employed to provide for higher voltage gain, and this can sometimes be accompanied with using a higher than typical power supply voltage. Source followers serve as output buffers and also ensure the required output DC voltage level as well. It is also noted that this design can be implemented using n-channel metal oxide semiconductor field-effect transistors (N-MOSFETs) of p-channel metal oxide semiconductor field-effect transistors (P-MOSFETs).

Abstract: An integrated circuit comprises a pin coupled to receive signals from outside the integrated circuit and an input network. The input network equalizes incoming signals by attenuating lower frequency input signals more than higher frequency input signals received at the pin. The input network is configured to generate a DC bias voltage at an output of the input network in response to an AC coupled input signal or a DC coupled input signal received at the pin with a wide common-mode range.

Abstract: An active compensation filter for the application in the electric power supply in a land vehicle, which comprises a high-pass filter which is to be coupled with a supply voltage line which carries a supply voltage, in order to detect frequency and amplitude of interference voltage components of the supply voltage. A signal amplifier which is connected in series with the high-pass filter amplifies the detected interference voltage components and supplies them to a coupling element as output signals, which is connected in series with the signal amplifier and comprises a primary side and a secondary side. The primary side is fed with the output signals of the signal amplifier and the secondary side is looped into the supply voltage line.

Abstract: A noise shaping and voltage gain filtering third order electrical circuit and method comprises at least one pair of input resistors; a Frequency Dependent Negative Resistance (FDNR) filter positioned in between the at least one pair of input resistors; a feedback resistor; and an amplifier operatively connected to the feedback resistor and the at least one pair of input resistors, wherein as an electrical signal is introduced to the electrical circuit, the FDNR filter is adapted to filter signal blockers out of the electrical signal prior to the electrical signal reaching the amplifier for signal amplification, wherein the FDNR filter does not contribute noise to a signal-to-noise ratio (SNR) of the electrical signal, and wherein a transfer function of the FDNR filter is substantially elliptical in shape.

Abstract: A low-pass filtering circuit and method are disclosed. The circuit includes a low-pass filter with a capacitor, and a multiplier configured to multiply the capacitance of the capacitor by feeding-back a high-frequency signal apparent in an output signal of the low-pass filter to the capacitor.

Abstract: The present invention discloses a circuit for settling DC offset and controlling RC time-constant in a direct conversion receiver. The circuit includes a variable resistive unit for providing a continuously or non-continuously variable resistance in the direct conversion receiver. The variable resistive unit can provide the variable resistance by utilizing a controllable transistor or a plurality of resistors. Accordingly, the variable resistive unit can be coupled to a capacitor for constituting a high pass filter, which is capable of rapidly settling DC offset in a direct conversion receiver.

Abstract: An improved capacitive feedback circuit (20) comprises a feedback capacitor (23) having its output terminal connected to a high-impedance node (N). More particularly, the improved capacitive feedback circuit comprises a first branch (24) having a bias current source (25), an amplifying element (26), and a current sensor (27) connected in series, the amplifying element having a high-impedance control terminal (26c). The feedback capacitor (23) has its output terminal connected to said control terminal (26c). A current-to-voltage converting feedback loop (28) has a high-impedance output terminal (28c) connected to said feedback capacitor output terminal.

Abstract: A semiconductor integrated circuit can include a first voltage pad, a second voltage pad, and a voltage stabilizing unit that is connected between the first voltage pad and the second voltage pad. The first voltage pad can be connected to a first internal circuit, and the second voltage pad can be connected to a second internal circuit.

Abstract: A variable frequency module controls a cutoff frequency of a high pass filter and includes a resistive element that communicates with a capacitive element of the high pass filter. A first transistor communicates with the resistive element and a reference node and includes a first source/drain region formed in a first well region and a first diode region formed between the first source/drain region and the first well region. A first node of the first diode region is connected to the first source/drain region and the reference node, and a second node of the first diode region is connected to the reference node.

Abstract: A transconductance filtering device with a flexible architecture that can selectively present a different topology and/or order beginning with the same initial structure is disclosed. For example, depending on the communications standard detected, the elementary cells of the filtering circuit required to form the adapted filter are selected and connected in such a manner as to obtain the configuration desired for the filtering means. As an example, the filter may be for use with a wireless communications system forming, in particular, a cellular mobile telephone. The filter is configurable by means of at least two elementary cells of the same structure and of controllable interconnection means each having an open or closed state.

Abstract: A capacitor has one end receiving an input signal and the other end outputting an output signal. A resistor circuit, connected between a power source and the other end of the capacitor, functions as a resistor. The resistor circuit includes a PNP transistor having a base connected to the other end of the capacitor and an NPN transistor having a base connected to the other end of the capacitor. A differential amplifier supplies complementary current to the PNP transistor and the NPN transistor. The differential amplifier receives, as negative feedback, the output signal from the other end of the differential amplifier.

Abstract: An application-specific integrated circuit (CS) comprises a first analog stage (E1), comprising first filtering means (C11-C2M, R11-R2P) responsible for carrying out a filtering of the high-pass type on an input signal (SE) so as to deliver an intermediate signal (SI), and a second digital stage (E2), comprising second filtering means (M2) capable of introducing various first time constants depending on combinations of coefficient values and responsible for correcting any distortion potentially present in the intermediate signal (SI). The first filtering means comprise an assembly of electronic components configured in parallel and/or in series and capable of introducing various second time constants depending on their combination.

Abstract: An active compensation filter for the application in the electric power supply in a land vehicle, which comprises a high-pass filter which is to be coupled with a supply voltage line which carries a supply voltage, in order to detect frequency and amplitude of interference voltage components of the supply voltage. A signal amplifier which is connected in series with the high-pass filter amplifies the detected interference voltage components and supplies them to a coupling element as output signals, which is connected in series with the signal amplifier and comprises a primary side and a secondary side. The primary side is fed with the output signals of the signal amplifier and the secondary side is looped into the supply voltage line.

Abstract: The various embodiments disclose capacitor multiplier circuits that may be integrated into imaging devices, such as for semiconductor Complimentary Metal Oxide Semiconductor (CMOS) image sensors, to create an effective capacitance in response to a low frequency, such as row-wise temporal noise, that may be generated along a row of image sensor pixels. The created effective capacitance from any one of the capacitor multiplier circuits along with a small signal resistance created by a trans-conductance of a current biasing transistor form a low pass filter that will attenuate the low frequency noise.

Abstract: Control system for programmable filters, master-slave calibration system and fully programmable high precision filter for use in such control system, such filters being provided with a filter input and a filter output including a first, first order low pass filter section comprising first and second mutually identical operational transconductance amplifiers (OTAs), having a controllable transconductance Gm from a differential voltage input having first and second differential voltage input terminals to a single current output carrying a single phase current output signals, said first and second OTAs being provided with first and second control inputs, respectively, said filter input being coupled to the first differential voltage input terminal of said first OTA.

Abstract: A high pass filter circuit having a signal input terminal and a signal output terminal. The high pass filter circuit is provided with a voltage source, first and second inverters, and a capacitor. The voltage source provides a DC bias voltage. The first inverter couples to the voltage source to invert the DC bias voltage. The second inverter couples to the first inverter and a signal output terminal respectively. The second inverter inverts the DC bias voltage inverted by the first inverter to provide the DC bias voltage to the signal output terminal. The second inverter also provides large impedance at the signal output terminal. The capacitor is coupled between the signal input terminal and the signal output terminal to provide a low corner frequency in cooperation with the second inverter. The circuit further comprises an operational amplifier.

Abstract: The invention concerns a continuous-time delta-sigma analog-digital converter for the conversion of an analog input signal into a digital output signal, comprising an analog filter which filters the analog input signal and at least one externally circuited operational amplifier (OPAMP) for the formation of an integrator stage, a clock-driven quantizer, which quantizes the filtered analog signal outputted through the analog filter to generate the digital output signal, and a feedback arrangement with at least one digital-analog converter, which supplies to the analog filter at least one feedback signal on the basis of the digital output signal.