Abstract: A System-on-Chip (SoC) includes first and second voltage supply pins configured to receive first and second supply voltages, respectively, a first supply path beginning at the first supply pin, and a supply proportion checker. The first supply path includes a first plurality of voltage supply nodes and a supply switch coupled between adjacent voltage supply nodes, wherein each node is configured to provide a corresponding internal voltage supply to a corresponding portion of the SoC. The supply proportion checker is coupled to receive the corresponding internal voltage supply from each voltage supply node, and configured to determine whether a first internal voltage supply supplied by a first supply node of the first plurality of nodes has a legitimate proportion to a second internal voltage supply supplied by a second supply node of the first plurality of nodes, wherein the legitimacy is checked using only resistors which do not require trimming.

Abstract: A peak detector comprises multiple small-size amplitude detection circuits coupled in parallel to signal inputs at which a signal is received from a VCO. Each amplitude detection circuit generates a voltage on an output, indicating a voltage peak or amplitude of a first signal input and a second signal input (specifically, differential output of VCO). At a given time, only one small-size amplitude detection circuit is activated to load VCO, reducing the impact on LC resonant frequency. The plurality of small-size detection circuits work sequentially, and an automatic averaging of their outputs can significantly improve the peak detector fluctuation (caused by process variation and device mismatch) compared to each single small-size amplitude detection circuit.

Abstract: In one embodiment, a processor includes: at least one core to execute a workload; a voltage regulator to provide an operating voltage to the at least one core; and a power controller coupled to the voltage regulator. The power controller may control the voltage regulator to provide the operating voltage, and may have a voltage regulator control circuit to select one of a plurality of power state profiles based at least in part on a classification of the workload, and to cause an update to a power state of the voltage regulator according to the selected power state profile. Other embodiments are described and claimed.

Abstract: Disclosed herein are related to an integrated circuit to regulate a supply voltage. In one aspect, the integrated circuit includes a metal rail including a first point, at which a first functional circuit is connected, and a second point, at which a second functional circuit is connected. In one aspect, the integrate circuit includes a voltage regulator coupled between the first point of the metal rail and the second point of the metal rail. In one aspect, the voltage regulator senses a voltage at the second point of the metal rail and adjusts a supply voltage at the first point of the metal rail, according to the sensed voltage at the second point of the metal rail.

Abstract: A single-ended sense amplifier includes a virtual-supply voltage-adapted (VVDD-adapted) inverter circuit, a virtual-supply voltage-adapted (VVDD-adapted) voltage-level converter circuit (VLC), and a virtual-supply-voltage-adaptation circuit (VSVA). The single-ended sense amplifier receives a data signal input, a sensing-operation-enabling signal input, and a pre-charging control signal input to generate a final amplified signal output. There are a first virtual-supply node and a second virtual-supply node in the VVDD-adapted inverter circuit. There is a third virtual-supply node in the VVDD-adapted VLC. The VSVA connects both the first and third virtual supply voltage nodes. The output end of the virtual-supply voltage-adapted inverter circuit connects to the input end of the VVDD-adapted VLC.

Abstract: A receiving circuit is provided that can accurately detect a clock signal that has a single phase and a small amplitude. A receiving circuit includes an AC coupled circuit 22 that creates an AC coupling between a first end and a second end, a low-pass filter circuit 23, 25 that produces a third signal by applying a low-pass filtering on a second signal that is produced on the second end in response to a first signal that is applied to the first end, and a comparator 21 that inputs the second signal and the third signal.

Abstract: A comparator includes a first amplification unit suitable for differentially amplifying a pixel signal and a ramp signal, a second amplification unit suitable for amplifying a signal outputted from the first amplification unit and outputting a comparison result, a current control unit suitable for controlling a current flow in response to the comparison result and a current compensation and noise removal unit suitable for compensating for current and removing noise under control of the current control unit.

Abstract: A differential amplifier includes an input common mode voltage generation unit suitable for generating an input common mode voltage, an input common mode voltage sampling unit suitable for performing an independent sampling operation on the input common mode voltage, and a differential amplifying unit suitable for performing a differential amplifying operation on an input voltage and the sampled input common mode voltage.

Abstract: An electrical circuit includes a comparator that receives a first signal at a first input pin, where the first signal is indicative of a current drawn from a power supply unit (PSU) that delivers power to an electronic component. The comparator substantially simultaneously receives a second signal at a second input pin, where the second signal is indicative of a voltage provided by the PSU to the electronic component and is set to a predetermined threshold. An output of the comparator changes if a difference exists between the first signal and the second signal. The electrical circuit includes a variable gain amplifier that provides the first signal to the comparator, where a gain of the variable gain amplifier is set according to the predetermined threshold.

Abstract: An electrical circuit includes a comparator that receives a first signal at a first input pin, where the first signal is indicative of a current drawn from a power supply unit (PSU) that delivers power to an electronic component. The comparator substantially simultaneously receives a second signal at a second input pin, where the second signal is indicative of a voltage provided by the PSU to the electronic component and is set to a predetermined threshold. An output of the comparator changes if a difference exists between the first signal and the second signal. The electrical circuit includes a variable gain amplifier that provides the first signal to the comparator, where a gain of the variable gain amplifier is set according to the predetermined threshold.

Abstract: A low noise comparator for a high resolution ADC is provided. The comparator includes: an inputter configured to receive a signal and amplify the signal; and an outputter configured to output a result of comparing the signal output from the inputter, wherein an inductor is connected to an input terminal of an input element of at least one of the inputter and the outputter. Accordingly, the comparator can satisfy the gain value and the noise performance at the same time by using the inductor which has no voltage headroom problem.

Abstract: USB apparatus suitable for interconnection with a USB host having a D? bus coupled to ground via a pull-down resistance, the USB apparatus including a microcontroller having a first port and a second port, the first port being coupled via a resistance to a voltage source and a switch, operated by the microcontroller via the second port, selectably interconnecting the first port and the bus of the USB host.

Abstract: In some embodiments, disclosed is an AC amplitude detector to compare the magnitude of an AC signal against a detector threshold level and to provide an indication as to whether the AC magnitude is larger or smaller than the detector threshold level.

Abstract: Described is an apparatus comprising: a reference generator to provide a first reference and a second reference; a first input coupled to the first reference; a second input coupled to the second reference; and a comparator coupled to the first and second inputs, the comparator to receive a clock signal and to update an output signal according to a phase of the clock signal.

Abstract: An auto-mute control circuit is disclosed. The auto-mute control circuit includes an analog amplifier, a detecting circuit and a direct-current (DC) level adjusting circuit. The analog amplifier receives an input signal and outputs a sensing voltage signal accordingly. The detecting circuit compares a common-mode voltage received with the sensing voltage signal received and outputs a comparison signal accordingly. The DC adjusting circuit receives the comparison signal and outputs an Up-Down digital signal, a fine tune digital signal and a rough tune digital signal, so that a sensing DC level is equal to the common-mode voltage.

Abstract: A system for signal processing comprising a cyclic analog to digital converter structure having a first stage and a second stage, wherein the first stage is configured to receive an input signal to perform 1.5 bits/stage ADC and to generate a first stage output signal, and the second stage is configured to receive the first stage output signal and to perform fine offset tuning using a final conversion phase. The second stage further configured to perform 1.5 bits/stage ADC and to generate a second stage output that is fed back to the first stage to iteratively generate a next 1.5 bits, until (N?3) most significant bits of N bits of data are generated. A third stage configured to generate a three least significant bits of the N bits of data using a flash ADC sampling circuit that samples a residue signal at the output of the first stage.

Abstract: A high-speed differential comparator circuit is provided with an accurately adjustable threshold voltage. Differential reference voltage signals are provided to control the threshold voltage of the comparator. The common mode voltage of the reference signals preferably tracks the common mode voltage of the differential high-speed serial data signal being processed by the comparator circuit.

Abstract: An apparatus for comparing differential input signal inputs is provided. The apparatus comprises a CMOS sense amplifier (which has having a first input terminal, a second input terminal, a first output terminal, and a second output terminal), a first output circuit (which has a first load capacitance), a second output circuit (which has a second load capacitance), and an isolation circuit. The isolation circuit is coupled between the first output terminal of the CMOS sense amplifier and the first output circuit and is coupled between the second output terminal of the CMOS sense amplifier and the second output terminal of the CMOS sense amplifier. The isolation circuit isolates the first and second load capacitances from the CMOS sense amplifier.

Abstract: Determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a plurality of NAND strings and a buffer are formed.

Abstract: A level detector, an internal voltage generator including the level detector, and a semiconductor memory device including the internal voltage generator are provided. The internal voltage generator includes a level detector that compares a threshold voltage that varies with temperature with an internal voltage to output a comparative voltage, and an internal voltage driver that adjusts an external supply voltage in response to the comparative voltage and that outputs an internal voltage.

Abstract: A bulk-driven current-sense amplifier and an amplifier operating method are disclosed. The bulk-driven current-sense amplifier includes a differential amplifier, a first driver, and a second driver. The first driver is coupled to the differential amplifier, and a first node is formed at a connectivity segment of the first driver. The second drive is coupled to the differential amplifier, and a second node is formed at a connectivity segment of the second driver. When a first switch of the first driver and a second switch of the second driver are turned on, the differential amplifier charges the first node and the second node. When the charging is completed, the first node and the second node respectively have a different stabilized potential according to currents separately flowing through a first memory unit of the first driver and a second memory unit of the second drive, and the differential amplifier generates a voltage.

Abstract: A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.

Abstract: Embodiments of the invention are related to sense amplifiers. In an embodiment involving a sense amplifier used with a memory cell, signals BL, ZBL, SN and SP are pre-charged and equalized to a voltage reference, e.g., Vref, using an equalizing signal. A compensation signal, e.g., SAC, is applied to compensate for the mismatch between transistors in the sense amplifier. The word line WL is activated to connect the memory cell to a bit line, e.g., bit line ZBL. Because the memory cell shares the charge with the connected bit line ZBL, it causes a differential signal to be developed between bit lines BL and ZBL. When enough split between bit lines BL and ZBL is developed, signals SP and SAE are raised to VDD (while signal SN has been lowered to VSS) to turn on the sense amplifier and allow it to function as desire. Other embodiments and exemplary applications are also disclosed.

Abstract: A current-sense amplifier with low-offset adjustment and a low-offset adjustment method thereof are disclosed. The current-sense amplifier includes a sensing unit, an equalizing unit and a bias compensation unit. The sensing unit includes a sense amplifier, a latch circuit, a first precharged bit line, and a second precharged bit line. The equalizing unit is electrically connected to the first and the second precharged bit line for regulating a voltage of the first precharged bit line and a voltage of the second precharged bit line to the same electric potential. The bias compensation unit is electrically connected to the sense amplifier for compensating an input offset voltage of the current-sense amplifier.

Abstract: A differential amplifier stage under a band design whereby a data signal at a maximum transfer rate among received waveforms is subjected to attenuation upon passing through a transmission line is not amplified, and a signal at a transfer rate half the maximum transfer rate is amplified. If it is determined that a signal whose amplitude is larger in value than a high reference voltage, the signal is determined as a signal “1” while if smaller in value than a low reference voltage, the signal is determined as a signal “0”. If the first amplitude detector detects that the amplitude of the signal is smaller in value than the high reference voltage, and the second amplitude detector detects that the amplitude of the signal is larger in value than the low reference voltage, the present signal is determined as an inverting signal of an immediately preceding signal.

Abstract: A level detector, an internal voltage generator including the level detector, and a semiconductor memory device including the internal voltage generator are provided. The internal voltage generator includes a level detector that compares a threshold voltage that varies with temperature with an internal voltage to output a comparative voltage, and an internal voltage driver that adjusts an external supply voltage in response to the comparative voltage and that outputs an internal voltage.

Abstract: Systems, apparatus, memory devices, sense amplifiers and methods are provided, such as a system that includes an input node, a first transistor having a gate that couples to the input node, and a second transistor having another gate that couples to the input node. In one or more embodiments, the second transistor has a greater activation voltage threshold than does the first transistor and the first transistor amplifies a signal that is present on the input node. In one such embodiment, after the first transistor amplifies the signal, the second transistor maintains the amplified signal on the input node while the first transistor is deactivated.

Abstract: A high-speed differential comparator circuit is provided with an accurately adjustable threshold voltage. Differential reference voltage signals are provided to control the threshold voltage of the comparator. The common mode voltage of the reference signals preferably tracks the common mode voltage of the differential high-speed serial data signal being processed by the comparator circuit.

Abstract: In an embodiment, set forth by way of example and not limitation, a data slicer includes a signal input node, a comparator having a first input of a first polarity, a second input of a second polarity which is the opposite of the first polarity, and an output coupled to a data out node, the first input of the comparator being coupled to the signal input node, and a multi-mode threshold generator including a first threshold generator and second threshold generator, whereby the first threshold generator is selected firstly and the second threshold generator is selected secondly.

Abstract: A dynamic comparator with background offset calibration is provided. The dynamic comparator includes at least one input differential pair, a first back-to-back inverter, a second back-to-back inverter, and an integrator. The input differential pair includes two current branches, wherein one of the current branches has an input referred offset. The first back-to-back inverter determines which one of the two current branches has the input referred offset in response to a first clock signal and generates two control signals accordingly. The integrator generates two calibration voltages for the input differential pair in response to the two control signals, so as to calibrate the input referred offset. The second back-to-back inverter determines a difference between two input signals received by the input differential pair after the input referred offset is calibrated in response to a second clock signal and outputs two comparison signals accordingly.

Abstract: The present invention provides an OOB detection circuit capable of making accurate signal determination even in the case where a characteristic fluctuation occurs in an analog circuit, thereby preventing deterioration in the yield of a product. To an amplitude determining circuit, a characteristic adjustment register for changing setting of an amplitude threshold adjustment mechanism for distinguishing a burst and a squelch from each other provided for the amplitude determining circuit is coupled. The characteristic adjustment register is controlled by a self determination circuit. An output of the amplitude determination circuit is supplied to a time determining circuit and also to the self determination circuit. On the basis of the output of the amplitude determining circuit, the self determination circuit controls the characteristic adjustment register.

Abstract: A sense amplifier having a sampling circuit to sample the amplifier input signal; a reference node storing a reference signal corresponding to the input signal; and a timing circuit activating the sampling circuit for a predetermined interval, and admitting the reference signal to the reference node. The sense amplifier also can include a pump capacitor substantially maintaining a value of the reference signal; and a gain circuit coupled with the reference node and disposed to adaptively adjust gain of an output signal produced by the sense amplifier. The sense amplifier can be a single-ended sense amplifier.

Abstract: A level detector, a voltage generator, and a semiconductor device are provided. The voltage generator includes a level detector that senses the level of an output voltage to output a sensing signal and a voltage generating unit that generates the output voltage in response to the sensing signal. The level detector may include a first reference voltage generator configured to divide a first voltage and to output a first reference voltage, a second reference voltage generator configured to divide a second voltage in response to the output voltage and to output a second reference voltage that varies as a function of temperature, and a differential amplifier configured to receive the first and second reference voltages and to output a sensing signal in response to a sensing voltage generated by amplifying a difference between the first and second reference voltages.

Abstract: A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.

Abstract: According to one embodiment, there is provided an optocoupler system configured to generate current signals having high, low and no amplitude portions in response to the receipt of logic high and low input signals. The varying amplitude portions of the current signals are used to drive other portions of the isolation circuitry, and result in reduced power consumption and dissipation, as well as reduced pulse width distortion.

Abstract: A differential sense amplifier can perform data sensing using a very low supply voltage.

Abstract: A sense amplifier circuit is provided with a first transistor arrangement comprising a first n-type field effect transistor (NFET) having a respective body node, and a second transistor arrangement comprising a second NFET having a respective body node. The second transistor arrangement is electrically coupled to the first transistor arrangement, and the body node of the first NFET is electrically coupled to the body node of the second NFET. The sense amplifier circuit also includes or cooperates with a voltage condition selector that is electrically coupled to the body node of the first NFET and to the body node of the second NFET. The voltage condition selector is configured to assert one of a plurality of voltage conditions at the body node of the first NFET and at the body node of the second NFET.

Abstract: During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a plurality of NAND strings and a buffer are formed.

Abstract: A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.

Abstract: A waveform generating circuit includes a constant current circuit that supplies a constant current through a power source; a current mirror circuit that flows an output current that is n times an input current; and a switching circuit that switches a flowing direction of the current in the constant current circuit between the current mirror circuit and the output terminal according to the logical level of the rectangle input signal. The waveform generating circuit generates a triangle wave having a falling slope waveform that is n times the rising slope. On the other hand, the waveform generating circuit that receives an inverted signal of the signal generates a triangle wave and its voltage is compared with another in the comparator to generate an output signal.

Abstract: A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.

Abstract: A conversion circuit for converting a differential input signal into an output signal includes an amplifier that has an input terminal and an output terminal; a first capacitor in which, in a first period, a difference voltage of the differential input signal is applied across first and second terminals, and in a second period the first terminal is coupled to the output terminal of the amplifier and the second terminal is coupled to the input terminal of the amplifier; and a second capacitor in which, in the second period, a reference voltage in accordance with the differential input signal is applied to a first terminal, and the second terminal of the first capacitor is coupled to a second terminal of the second capacitor.

Abstract: A solid-state imaging device includes a light receiving section having a plurality of threshold voltage modulation pixel circuits each configured including a MOS transistor having a gate electrode connected to a supply terminal of a gate voltage of a vertical scanning circuit, and a source electrode connected to one end of each capacitor of a line memory group via a switching element, and a photodiode having an anode connected to a back-gate electrode of the MOS transistor and a cathode connected to a drain electrode thereof, and a buffer circuit having an input terminal connected to a supply line of a control voltage of the control voltage supply means adapted to supply the vertical scanning circuit with the control voltage, and an output terminal connected to the other end of each capacitor, and having a signal transfer characteristic the same as that of the pixel circuit.

Abstract: A differential sense amplifier can perform data sensing using a very low supply voltage.

Abstract: A level detector, a voltage generator, and a semiconductor device are provided. The voltage generator includes a level detector that senses the level of an output voltage to output a sensing signal and a voltage generating unit that generates the output voltage in response to the sensing signal. The level detector may include a first reference voltage generator configured to divide a first voltage and to output a first reference voltage, a second reference voltage generator configured to divide a second voltage in response to the output voltage and to output a second reference voltage that varies as a function of temperature, and a differential amplifier configured to receive the first and second reference voltages and to output a sensing signal in response to a sensing voltage generated by amplifying a difference between the first and second reference voltages.

Abstract: A dual reference input receiver, and a method of receiving, wherein the input receiver includes a first input buffer which is synchronized with and enabled by a clock signal, senses a difference between the input data signal and a first reference voltage, and amplifies the sensing result; a second input buffer which is synchronized with and enabled by the clock signal, senses a difference between a second reference voltage and the input data signal, and amplifies the sensing result; and a phase detector which detects a difference between a phase of output signals of the first and second input buffers, and outputs a signal corresponding to the detection result. The first and second reference voltages may respectively be higher and lower than a median voltage of the input data signal. Thus, a single input data signal is advantageously used and a wide input data eye is provided.

Abstract: A single-ended differential sense amplifier comprises a dynamic reference voltage generation circuit and a differential sense amplifier circuit. Input data with an input data line voltage is provided to the differential sense amplifier circuit. The input data line voltage also feeds back to the dynamic reference voltage generation circuit, which then generates a dynamic reference voltage based on the input data line voltage. The differential sense amplifier circuit is coupled to the dynamic reference voltage generation circuit and receives the dynamic reference voltage for determining the input data. The dynamic reference voltage increases and the input data line voltage decreases when reading the input data of a logic state, e.g., logic “0.

Abstract: The invention concerns a method for controlling a switching assembly comprising a plurality of transistors connected in parallel, having a linear operating mode, a closed-switch operating mode and an off operating mode including a first operating phase during which a current flows from a source terminal to a drain terminal and a second operating phase during which no current flows. The method includes the following successive steps; (a) controlling the switching assembly in closed-switch mode during part of the first phase; (b) controlling the switching assembly in linear mode; (c) controlling the assembly in off mode during part of the second phase.

Abstract: A sensing amplifier for a memory cell comprises a selection stage that outputs one of a reference current and a memory cell current during a first period and the other of the reference current and the memory cell current during a second period. The first period and the second period are non-overlapping. An input stage generates a first current based on the one of the reference current and the memory cell current during the first period and generates a second current based on the other of the reference current and the memory cell current during the second period. A sensing stage senses a first value based on the first current and stores the first value during the first period, senses a second value based on the second current during the second period and compares the first value to the second value.

Abstract: A system for monitoring multiple power supply signals with respect to a threshold has multiple inputs for receiving input power supply signals. A processing circuit of the system produces an output signal at a first level when the power supply signals have a prescribed relationship to a threshold value, and produces the output signal at a second level when at least one of the input power supply signals does not have the prescribed relationship to the threshold value. The processing circuit is configured for selecting the first level corresponding to a level of an input power supply signal at a pre-selected one of the inputs.