Abstract: To make a memory system smaller, a memory system includes a plurality of memory cell arrays including a plurality of pairs of bit lines, a plurality of first data amplifiers for amplifying data of corresponding pairs of bit lines, a reference voltage circuit for outputting a reference voltage level, and a plurality of second amplifiers for receiving an output of the corresponding first data amplifier and the reference voltage level, for judging which voltage level is higher between the output of the corresponding first data amplifier and the reference voltage level, and for amplifying the voltage level being higher.

Abstract: In an input buffer circuit for use in a semiconductor integrated circuit, comprising a differential pair formed of a pair of MOS transistors and receiving a reference voltage and an input signal supplied from an external, a first constant current source MOS transistor connected to the differential pair, and a load circuit connected to the differential pair, a second constant current source MOS transistor is connected in parallel to the first constant current source MOS transistor. A gate voltage of the second constant current source MOS transistor is controlled by a reference voltage convening circuit which receives the reference voltage.

Abstract: A sensing amplifier that works over a large operating frequency having a plurality of reference inputs, at least one signal input and at least one signal output, where the amplifier comprises a plurality of transistors to internally compare the signal input to the average value of the reference inputs and producing an output based on the comparison. In some cases, the output can be a latched binary signal.

Abstract: An improved current sensing differential amplifier which includes a separate p-channel bias stage to reduce the minimum operating voltage VCC of the circuit. The separate p-channel bias stage is also used to pre-bias a driver stage to more quickly generate differential output currents. Finally, the improved current sensing differential amplifier also includes negative feedback transistors to improve the recovery time of the circuit.

Abstract: In reading circuits for memories in integrated circuit form, notably non-volatile memories, a differential amplifier for reading the memory cell is connected to a precharged bit line and a reference line. A balancing device balances the potentials of the bit line and reference line, and the corresponding inputs to the differential amplifier, before the reading phase of the circuit. The balancing device includes a follower amplifier having an input connected to the differential amplifier and an output connected to the bit line to inject a load current to the bit line during a balancing phase of the reading circuit.

Abstract: A transmission-line-voltage control circuit for controlling a level of a transmission line is disclosed. A signal of a first level indicating a logic high and a signal of a second level indicating a logic low are supplied to the transmission line. The transmission-line voltage control circuit includes a circuit connected to the transmission line. This circuit reduces, after the signal of the first level is supplied to the transmission line, the level of the transmission line to a third level which indicates the logic high and is less than the first level. And also the circuit increases, after the signal of the second level is supplied to the transmission line, the level of the transmission line to a fourth level which indicates the logic low and is higher than the second level.

Abstract: A memory sense amplifier includes a latch formed for interconnected CMOS gates with an input gate connected to one node of the latch and a reference gate connected to the other node of the latch the reference gate has an input connected to a source of reference voltage and the reference gate and input gate are activated in response to common enable signal. When the input signal, e.g., a data signal from a memory, has a signal value lower than the reference signal value when the two gates are enabled, the reference gate will discharge the node to which it is connected more rapidly than the input gate will discharge the other node. Due to the internal cross connections of the latch, the latch will rapidly change state so as to further discharge the node to which the reference is connected and further charge the other node.

Abstract: A circuit which differentially amplifies voltages that are close to ground with differences of about 0.15 volts uses voltage level shifters, a cross coupled current source and inverters to provide increased speed, accuracy, and gain. Symmetric cross coupled current sources are used in a differential amplifier to provide the differential amplifier with a balanced load. A symmetric and balanced layout senses smaller voltage differences and operates faster than would otherwise be possible. The gain of the cross coupled current source is controlled by four FETs. Voltage level shifters at the input to the differential amplifier allow the differential amplifier to sense signals that are close to ground with a voltage difference of about 0.15 volts. The voltage level shifters also shift the signals to a voltage that increases the gain of the differential amplifier. Two inverters block half level signals from being outputted until the sense amplifier data has been latched.

Abstract: In reading circuits for memories in integrated circuit form, notably non-volatile memories, to obtain a better compromise between reading speed and the reliability of the information read, there is proposed a reading circuit. A differential amplifier for reading a memory cell is connected to a precharged bit line and reference line. A follower amplifier balances the input potentials of the differential amplifier before the reading phase. The follower amplifier has one input connected to the output of the differential amplifier and is connected during the balancing phase in such a way that it injects a load current to the- bit line in a direction tending to cancel the output voltage of the differential amplifier. A cascode transistor can be used to accelerate the reading.

Abstract: In the present invention, there are disposed (i) a P-channel MOSFET for detecting variations of the voltage level of a data line to supply an electric current, and (ii) a current mirror circuit to which an electric current from the P-channel MOSFET is entered as a reference current and of which output current terminal is connected to the data line. When the data line is lowered in voltage level so that an electric current flows from the P-channel MOSFET to the current mirror circuit, an output current of the current mirror circuit flows to the drain of an N-channel MOSFET, so that the data line is electrically discharged. Thus, there is achieved a sensing circuit unit which is suitably used for a dynamic circuit and which can detect, at a high speed, variations of the voltage level of the data line as precharged.

Abstract: In reading circuits for memories in integrated circuit form, notably non-volatile memories, to obtain a better compromise between reading speed and the reliability of the information read, there is proposed a reading circuit constituted as follows: a differential amplifier, means for the precharging of the bit line before a reading phase and means for the balancing of the input potentials of the differential amplifier before the reading phase. The balancing means comprise a follower amplifier that has one input connected to the output of the differential amplifier and is connected during the balancing phase in such a way that it injects a load current of the bit line in a direction tending to cancel the output voltage to the differential amplifier. A cascode transistor can be used to accelerate the reading.

Abstract: In a semiconductor memory device, amplification of data is realized with a high speed without influences of fluctuations at fabrication. Potentials of a common data line pair are set at a reference voltage by current negative feedback of differential amplifiers. In this way signal amplitude in the common data line pair is decreased. A current from a memory cell is transformed into a voltage by transistors in a negative feedback loop. Even if there are fluctuations or an offset voltage in the differential amplifiers, it is possible to decrease the signal amplitude in the common data line pair and to realize a high speed data amplification with low electric power consumption.

Abstract: A high-voltage differential sensor includes an attenuator formed of two matched monolithic capacitance divider networks. Each divider network is formed of a series connection of monolithically integrated capacitors, which together generate an attenuated differential signal from a high-voltage differential input signal. The attenuated differential signal from the capacitance divider networks is then amplified and fed to a comparator, which generates a first output level when the high-voltage differential input signal is above a selected level, and generates a second output level when the high-voltage differential input signal is below the selected level. By using monolithically integrated capacitors in the divider networks of the attenuator, a simple, compact, low power, high performance high-voltage differential sensor is obtained.

Abstract: A nonvolatile memory device includes a matrix array of transistors. A read potential generation circuit provides a potential to a selected transistor and generates a read potential in accordance with the flow of current which indicates the data storage state of the transistor. A reference potential generation circuit provides a potential to a selected dummy transistor and generates a reference potential based on the current which flows through the dummy transistor. The memory device incorporates one or more strategies to prevent the relative magnitudes of the read potential and reference potential from being erroneously inverted immediately after the nonvolatile memory is switched from standby to an operational mode. A reference potential decreasing circuit incorporated within the reference potential generation circuit is activated for a predetermined time period after chip enable.

Abstract: A control circuit for maintaining the mean value of the amplitudes of control pulses having a first level and data pulses having a second level includes a detector for providing the control pulses and the data pulses. A reference voltage source provides first, second and third reference voltages having three different levels. A plurality of comparators each receive both the control pulses and the data pulses. A first comparator also receives the lowest of the reference voltages and provides regulation pulses when the control pulses reach the level of the lowest reference voltage. A second comparator receives the second highest reference voltage and provides level limiting pulses to maintain the level of the regulation pulses constant. A third of the comparators receives the highest reference voltage and provides data pulses when the third reference voltage is reached.

Abstract: A circuit employing a modulated-current offset-type or current-unbalance, offset-type sense amplifier for reading programmable memory cells employs loads identical to each other and a differential input pair of transistors of the differential amplifier are "cross-coupled" with said identical loads to realize a latch structure for storing an extracted data. The circuit also employs a pair of pass transistors, and a pair of precharge transistors. The pass transistors connect the differential input transistors to a memory matrix and the precharge transistors charge lines of the memory matrix. By properly sizing and fabricating these transistors, the pass transistors connect the differential input transistors with the memory matrix while the currents provided from the precharge transistors are either nulled or minimized.

Abstract: A memory device has memory cells each of which is addressed according to a timing signal, current sense amplifiers each of which determines whether a current flows in the addressed memory cell or not and reads-out the data stored in such memory cell, a circuit which generates a control signal to become active at a timing when the memory cell Is addressed and to become inactive after the read-out of the stored data is completed by the current sense amplifier, and a circuit which cuts-off based on the control signal a current path of a steady-state current flowing in the current sense amplifier. It is possible to substantially reduce power consumption without sacrificing the capability of the read-out the stored data at a high speed.

Abstract: The discriminating sensitivity of a sense amplifier and the speed of the circuit are increased by exploiting the difference of potential which develops across the output nodes of the two control circuits, employed for enabling/disabling current paths of the input network of the differential amplifier, as a virtual additional signal for the sensing differential amplifier, by employing said output potentials of the two control circuits as virtual reference potentials for the pair of input transistors of the differential amplifier during a discriminating phase of the reading cycle. Two pass-transistors driven by a control signal provide to force to ground potential the output nodes of said control circuits, thus reestablishing a correct ground reference potential of the amplifier, during the final phase of amplification and storage of the extracted datum in an output latch, as well as during the successive standby period. Alternative embodiments also include various anti-overshoot circuits.

Abstract: This invention is an improved pull-up circuit for P-channel sense amplifiers in dynamic random access memory arrays having non-bootstrapped wordlines. The improved pull-up circuit features a voltage-comparator-controlled P-channel device which couples the power supply bus to a pull-up node for high current flow to the node and to digit lines which are coupled to the node via P-channel isolation devices. During the pull-up cycle, the P-channel device remains "on" as long as a reference voltage is greater than a variable voltage which represents the voltage level on portions of the digit lines farthest from the P-channel sense amplifier. The pull-up circuit also has an N-channel device which couples the power supply node to the pull-up node for maintenance of a desired voltage level equal to V.sub.cc minus the threshold voltage of the N-channel device.