Abstract: The present invention relates to a semiconductor integrated circuit. In greater detail, the present invention relates to a semiconductor integrated circuit which conducts calculations using a voltage adding function by means of capacity and threshold operations.

Abstract: A power supply voltage level sensing circuit and its application to circuits that interface with circuits that have performance characteristics that conform to universally accepted standards such as TTL, is described. An input terminal of a threshold shifting means is connected to the power supply to be detected to shift the voltage level of the power supply to a level acceptable by a Schmitt trigger. The threshold voltage level of the Schmitt is set so as to detect the range of the voltages that may be present at the power supply. The output of the Schmitt trigger is the data input to a first flip-flop. A system reset terminal provides a power-on-reset signal to a reset terminal of the first flip-flop and to the clock input of the first flip-flop through a buffer circuit. The power-on-reset signal maintains the output of the first flip-flop at a first level for a period of time after the activation of the power supply.

Abstract: An electronic memory has a voltage sense amplifier coupled to a memory cell via a bit line for supply of an output signal under control of data stored in the cell. The sense amplifier is both powered and controlled by redistribution of electric charge, representative of the data and initially accumulated at the bit line, between the bit line and the output of the sense amplifier.

Abstract: A current sense amplifier for use in a semiconductor memory device having a pair of sub-I/O lines and a pair of I/O lines includes a first circuit leg having a first PMOS transistor in series with a second NMOS transistor. A second circuit leg has a third PMOS transistor in series with a fourth NMOS transistor. The gates of the PMOS transistors are each cross coupled to the drain of the other PMOS transistor. The gates of the NMOS transistor are each cross coupled to the source of the PMOS transistor in the other circuit leg. The source of each PMOS transistor comprises a sub-Input/Output line with an Input/Output line located between the transistors in each of the legs.

Abstract: A bit line sensing circuit of a semiconductor memory device having NMOS and PMOS sense amps connected to a bit line includes a variable delay path for variably controlling an interval of the operating time between the NMOS and PMOS sense amps in response to a power voltage sensing signal generated by sensing a power voltage level.

Abstract: A high-performance differential latch circuit which includes a differential amplifier circuit comprised of an NMOS transistor (27) serving as a constant current source, PMOS transistors (3, 4) and NMOS transistors (23,24), a latch circuit comprised of NMOS transistors (25, 26), and a switch circuit comprised of NMOS transistors (21,22,28) for alternately operating the differential amplifying function and latch function, the transistor (27) serving as the constant current source having a drain terminal directly connected to the transistors (23,24) and a source terminal directly connected to a ground voltage (2), whereby the differential latch circuit differentially amplifies the signals without the loss of the constant current source function during the differential amplification.

Abstract: A differential sense amplifier includes positive feedback cross coupling to control operation in one mode as a differential sense amplifier and in another mode as a latch to control a data-latching load. Circuit nodes are precharged and equalized in response to applied enable signal.

Abstract: A SRCMOS sense amplifier is provided with a latch in the output stage. When a sense amplifier input signal propagates through the circuit and reaches the output stage, a reset signal is generated resetting and charging the input stage and an enable buffer stage of the amplifier to allow the input stage to begin receiving new data while previous data is latched in the output stage. An output stage reset enable is generated when data is at the output terminals of the output stage. The reset enable is combined with a clock signal in a separate output stage reset circuit to reset the circuit on a clocked basis. A further input to the output stage reset circuit is a feedback from a next circuit stage indicating that the data has been properly received in the next stage. The output stage may be reset either in response to the feedback signal from the next stage or in the presence of the reset enable and the clock signal.

Abstract: To permit effective testing of a sense amplifier circuit, the sense amplifier is designed to be responsive to data stored in a selected memory cell in a controlled test mode. The sense amplifier circuit includes a pull-down circuit having delay circuit to receive and respond to a control signal which indicates whether the sensing circuit is to operate in test mode or normal mode. The sense amplifier circuit also includes an output circuit which is configured and arranged to generate a reference signal corresponding to the data stored in a selected memory cell. To permit sufficient time to test the circuit for correct data values at the output signal, the reference signal is delayed in response to the control signal indicating that the sensing circuit is to operate in test mode.

Abstract: A low power sense amplifier to sense the output of any memory cell whose output may be ill-defined is especially suited for use with gain memory cells. The low power sense amplifier circuit is based on an inverter with a feedback loop with additional circuitry providing stability after signal sensing. The bit sense line is discharged before sensing and after sensing it is locked to either a logical "0" or a logical "1" corresponding to the logical value of the gain memory cell during a read cycle. The low power sense amplifier provides a logic output that is well defined with respect to the supply voltage and corresponds to the logic valve of gain memory cell. The low power sense amplifier has no bias current flow during signal sensing and no power consumption in the stand by mode. The present invention low power sense amplifier is capable of being shared by a first bit sense line and a second bit sense line.

Abstract: Disclosed is a low power-consumption type comparator circuit having two input terminals for receiving two input signals, one of which is an input reference signal and the other of which is an input comparison signal, and two output terminals, the circuit comprising signal converting portion for converting the input signals into current signals, respectively; switching portion for controlling transmission of the current signals to output terminals of the circuit in response to a latch signal indicating a latch operation or a normal operation of the circuit; high level holding portion for maintaining each voltage level of the output terminals to a logical high-state only when the latch operation of the circuit is not performed; amplifying/determining portion for amplifying the current signals and determining logical level of the input comparison signal; and output feedback portion for receiving output signals of the output terminals and enabling to make a current flowing in the circuit to a zero-state, only whi

Abstract: A high speed self-resetting, edge-triggered CMOS (SRCMOS) receiver and parallel L1/L2 latch combination are provided which may be used to receive and latch data from a single-ended input of static random access memory (SRAM) or a dynamic random access memory (DRAM). The invention comprises a true/complement generator circuit (TCG) for generating a data and its complement from a single-ended input, a reset circuit for automatically resetting the TCG independent of the system clock, and a parallel L1/L2 latch for storing the data for further processing. The L1/L2 latch preferably has scan-in and scan-out ports useful for testing and diagnostic purposes.

Abstract: According to the present invention, the delay associated with a logic stage external to a sense amplifier is eliminated by absorbing the logic state into the sense amplifier circuitry. The sense amplifier inputs are swapped based on a sense enable signal which may be a derivative signal of a Data In signal. The sense amplifier may sense continuously or it may be clocked. The sense enable circuitry may be applied to various types of sense amplifiers such as dynamic, current mirror, differential, cross coupled, and level shifting sense amplifiers.

Abstract: A comparator (10) provides a high speed comparison between at least two input signals and includes at least two stages (12) and (14). Each stage (12 and 14) includes a pair of transistors (24), a complementary pair of transistors (28) and an enabling transistor (26). The stages are coupled to provide positive feedback back to the first stage (12). A controller (15) operably couples to the enabling transistors. When the first input signal (16) is at a higher voltage level than the second input signal (18), the first comparison output (20) goes low. Conversely, when the second input signal (18) is at a higher voltage level than the first input signal (16), the second comparison output (22) goes low. When the first comparison output (20) goes low, the second enabling transistor (34) is disabled by the controller (15). When the second comparison output goes low, the first enabling transistor (26) is disabled by the controller (15).

Abstract: A latch-type current sense amplifier circuit generates complementary latched data outputs indicative of a difference between first and second input currents provided to the sense amplifier circuit respectively via first and second input data lines. Included in the sense amplifier circuit are a latch circuit formed from cross-coupled inverters, a transmission gate responsive to a first control signal for equalizing the outputs of the sense amplifier circuit, and three transistors. The first transistor is responsive to a second control signal, activated after a delay after deactivation of the first control signal, for connecting a reference voltage to the latch circuit.

Abstract: A sense amplifier circuit includes a voltage developing stage which receives first and second data inputs, din1 and din2, and generates a differential voltage, in response to feedback signals received from a first and second data outputs, dout1 and dour2, of the sense amplifier circuit, which is indicative of a voltage difference between the first and second data inputs, din1 and din2; a full-swing locking stage which generates and latches, in response to a control signal .PHI..sub.2 ', complementary latched data outputs from the first and second data outputs, dout1 and dout2, generated by the voltage developing stage; and a voltage equalization stage which equalizes, in response to a control signal .PHI..sub.0 ', voltages on data lines respectively connected to the first and second data outputs, dout1 and dout2. In addition, the voltage equalization stage is used to initiate the voltage developing stage. Timing of the control signals, .PHI..sub.0 ' and .PHI..sub.2 ', is such that the control signal .PHI..

Abstract: There is disclosed a sense amplifier for a semiconductor memory device comprising a cross coupled latch for sense-amplifying data signals on bit lines, a pull-up driver connected between the cross coupled latch and a supply voltage source for controlling an amount of current of a supply voltage being supplied to the cross coupled latch, a pull-down driver connected between the cross coupled latch and a ground voltage source for controlling an amount of current of a ground voltage being supplied no the cross coupled latch, and a voltage detector for detecting a difference between the supply voltage and the ground voltage and controlling the pull-up driver and the pull-down driver in accordance with the detected result. According to the present invention, when the voltage difference is high in level, the sense amplifier minimizes a noise component being generated. In the case where the voltage difference is low in level, the sense amplifier amplifies the data signals on the bit lines at a high speed.

Abstract: A flip-flop type amplifier circuit is adapted to amplify a voltage difference between a first voltage and a second voltage. This amplifier circuit includes a first power line supplying a first power supply voltage, a second power line supplying a second power supply voltage lower than the first power supply voltage, a flip-flop circuit including first through fourth nodes, and first and second inverters coupled in a ring. The first node couples an input of the first inverter and an output of the second inverter and receiving the first voltage, and the second node couples an output of the first inverter and an input of the second inverter and receives the second voltage. A first impedance element is coupled between the first power line and the third node of the flip-flop circuit, and a second impedance element is coupled between the second power line and the fourth node of the flip-flop circuit.

Abstract: A system and method for detecting the voltage level of a power supply signal and generating a notification signal to indicate when the supply voltage exceeds a minimum voltage that is programmable by a user. A programming signal, that allows for multiple voltages to be detected, is applied to the voltage detection system to generate a notification signal in response to the supply voltage attaining the minimum voltage indicated by the programming signal.

Abstract: A sense amplifier for an SRAM providing both a small power consumption and a high speed sensing operation.

Abstract: A circuit for comparing an input signal having a first voltage to a reference signal having a second voltage to determine whether the input signal voltage is greater than or less than the reference signal voltage. In a preferred embodiment, the circuit essentially employs only four transistors (two inverters). First and second complimentary transistors are coupled in series to form the first inverter. Third and fourth complimentary transistors are coupled in series to form the second inverter. Between the first and second complimentary transistors is a first node and between the third and fourth transistors is a second node. The first and third transistors are coupled to together at a third node. The second and fourth transistors are coupled together at a fourth node. In a first phase of operation, the circuit receives the input voltage and the reference voltage.

Abstract: A SRCMOS sense amplifier is provided with a latch in the output stage. When a sense amplifier input signal propagates through the circuit and reaches the output stage, a reset signal is generated resetting and charging the input stage and an enable buffer stage of the amplifier to allow the input stage to begin receiving new data while previous data is latched in the output stage. An output stage reset enable is generated when data is at the output terminals of the output stage. The reset enable is combined with a clock signal in a separate output stage reset circuit to reset the circuit on a clocked basis. A further input to the output stage reset circuit is a feedback from a next circuit stage indicating that the data has been properly received in the next stage. The output stage may be reset either in response to the feedback signal from the next stage or in the presence of the reset enable and the clock signal.

Abstract: A sense amplifier apparatus for use in a memory array having a plurality of memory cells is provided. The sense amplifier apparatus includes a differential sense amplifier and a dynamic sense amplifier. The differential sense amplifier has a first set of switches for driving the voltages of the sense amplifier apparatus and are coupled to a complementary pair of outputs. Also provided are a second set of switches, which are coupled to a complementary pair of input lines so as to amplify the input signal on either of the pair of input lines to a first signal level at a first rate of amplification. The dynamic sense amplifier shares the first set of switches with the differential sense amplifier and further includes a third set of switches that are coupled to a complementary pair of input lines and the output lines and also a sense enable line. This allows the first signal level to be amplified to a second signal level at a second rate of amplification faster than the first rate of amplification.

Abstract: A sense circuit has input and output terminals coupled through resistances to two fixed potentials. The input potential is amplified and inverted to control the gate of a field-effect transistor coupled between the input and output terminals. Alternatively, a sense circuit has first and second input terminals, and first and second output terminals. The first input terminal is connected to the gate of a depletion-mode field-effect transistor coupled between the second input and output terminals. The second input terminal is connected to the gate of a depletion-mode field-effect transistor coupled between the first input and output terminals. The depletion-mode field-effect transistors may be replaced by negative-resistance circuits. These sense circuits can obtain large voltage outputs from small current inputs.

Abstract: A memory system is provided wherein array signals begin at the start of a first phase of a system clock and a sense amplifier set signal is developed during a second phase of the system clock which includes an array of memory cells including word lines and bit lines, word drivers connected to the word lines, a word address decoder enabled by the first phase of the clock system and coupled to the word drivers, a bit switch coupling a bit line to a sense amplifier, a system clock inverting circuit, a timing circuit having a first input connected to a late select signal, a second input connected to the inverting circuit and an output connected to the bit switch and a delay circuit having an input coupled to the inverting circuit and an output connected to the sense amplifier.

Abstract: A sense amplifier for detecting the difference in voltage between two bitlines of a memory circuit. The sense amplifier is comprised of a differential amplifier which is coupled to the two bitlines and generates an output signal based on voltage levels sensed in the bitlines. The differential amplifier is coupled to V.sub.CC and ground through an active load and a current source respectively. To address the problem of increased common mode voltage levels found in the bitlines, a pair of transistors are connected in parallel across the active load to V.sub.CC and the differential amplifier. The gate of one of the transistors is coupled to one of the bitlines and the gate of the other one of the transistors is coupled to the other one of the bitlines. With these two transistors coupled in parallel across the load as described, the differential amplifier has increased immunity to elevated common mode levels found in the bitlines.

Abstract: A sense amplifier (10) has a pair of cross-coupled latches (12, 14, 16, 18) connected between a first voltage supply (V.sub.DD) and the sources of two transistors (20, 22). The gates of the two transistors receive a voltage differential to be sensed. The drains of the two transistors are coupled to a second voltage supply (V.sub.SS) through an enabling transistor (24). The resulting sense amplifier is fast, small, and relatively simple to construct.

Abstract: A sense amplifier circuit includes a voltage developing stage which receives first and second data inputs, din1 and din2, and generates, in response to a first control signal .PHI..sub.1, a differential voltage indicative of a voltage difference between the first and second data inputs, din1 and din2; a full-swing locking stage which generates and latches, in response to a second control signal .PHI..sub.2, first and second latched data outputs, dout1 and dout2, from the differential voltage generated by the voltage developing stage; and a voltage equalization stage which equalizes, in response to a third control signal .PHI..sub.0, voltages on data lines respectively connected to the first and second data outputs, dout1 and dout2. Timing of the first, second and third control signals, .PHI..sub.1, .PHI..sub.2 and .PHI..sub.0, is such that the first control signal is activated after a finite period following the initial activation of the third control signal .PHI..sub.0, and the second control signal .PHI..

Abstract: The present invention provides a sense circuit including a first bit line, a second bit line, a first plurality of memory cells coupled to the first bit line, a second plurality of memory cells coupled to the second bit line, and selection circuitry coupled to the first bit line and the second bit line. The selection circuitry provides a wide AND gate function in one mode and provides a zero power circuit for generating a function of a single input in another mode.

Abstract: A sense circuit has input and output terminals coupled through resistances to two fixed potentials. The input potential is amplified and inverted to control the gate of a field-effect transistor coupled between the input and output terminals. Alternatively, a sense circuit has first and second input terminals, and first and second output terminals. The first input terminal is connected to the gate of a depletion-mode field-effect transistor coupled between the second input and output terminals. The second input terminal is connected to the gate of a depletion-mode field-effect transistor coupled between the first input and output terminals. The depletion-mode field-effect transistors may be replaced by negative-resistance circuits. These sense circuits can obtain large voltage outputs from small current inputs.

Abstract: A data sensing circuit for a semiconductor memory device having complementary bit lines, including a PMOS sense amplifier connected between the complementary bit lines, an NMOS sense amplifier connected between the complementary bit lines, a bit line equalization and precharge circuit connected between the complementary bit lines, a sense amplifier equalization and precharge circuit connected between sensing control nodes of the PMOS and NMOS sense amplifiers, a plurality of first capacitors, a plurality of second capacitors, a plurality of first fuses connected between the sensing control node of the PMOS sense amplifier and respective ones of the first capacitors, a plurality of second fuses connected between the sensing control node of the NMOS sense amplifier and respective ones of the second capacitors.

Abstract: An improved sense amplifier is disclosed employing bleeder and dampening devices coupled in a robust feedback configuration for maintaining a relatively narrow and stable voltage level above the high threshold of the sense amplifier.

Abstract: A high speed self-resetting, edge-triggered CMOS (SRCMOS) receiver and parallel L1/L2 latch combination are provided which may be used to receive and latch data from a single-ended input of static random access memory (SRAM) or a dynamic random access memory (DRAM). The invention comprises a true/compliment generator circuit (TCG) for generating a data and its compliment from a single-ended input, a reset circuit for automatically resetting the TCG independent of the system clock, and a parallel L1/L2 latch for storing the data for further processing. The L1/L2 latch preferably has scan-in and scan-out ports useful for testing and diagnostic purposes.

Abstract: An all-CMOS output buffer drives a bus that can operate at 3 volts and 5 volts. When in a high-impedance state, the output buffer draws little or no current. If the bus is driven to 5 volts by an external device, the high impedance output buffer is in danger of latch-up and distortion of the bus logic level since it only has a 3-volt power supply and does not use a charge pump or an extra 5-volt supply. A biasing circuit couples an N-well that contains p-channel transistors and a driver transistor to the bus driven to 5 volts. Thus the N-well is also driven to 5 volts, the voltage on the bus. The gate of the p-channel driver transistor in the high-impedance output buffer is also coupled to the N-well by another p-channel transistor, raising the gate potential to 5 volts. Thus the gate and body of the p-channel driver transistor is at 5 volts, eliminating reversing current and latch-up problems. A transmission gate isolates the gate of the p-channel driver transistor from the rest of the device's circuitry.

Abstract: A semiconductor device and an electronic apparatus with the semiconductor device incorporated therein, include a sense amplifier so that a storage device can be read at a high speed and at a low speed, whereby low power consumption may be realized driving low speed reading. When a high speed mode is set and a read instruction is given, the sense amplifier is driven to send out a signal of a bit line to a data bus through the sense amplifier, while when a low speed mode is set and a read instruction is given, a sense amplifier is brought into a non-driven state to send out a signal of a bit line to a data bus without going through the sense amplifier. The semiconductor device may also include a clock control circuit and a clock selection circuit for selecting a high frequency clock signal when the high speed mode is set and for selecting a low frequency clock signal when the low speed mode is set.

Abstract: A voltage controlled oscillator (VCO) (23) includes a periodic signal generator (30) such as a comparator (42)followed by a latch (43), and a logic gate such as a NAND gate (31) connected to the output of the latch (43) to adjust for asymmetries in the output signals from the latch (43). In one embodiment, the NAND gate (31) includes two pullup transistors (80, 81) receiving first and second output signals from the latch and connected between a first power supply voltage terminal and an output node (86). Two switching branches (82, 83 and 84, 85) each including two transistors are connected between the output node (86) and a second power supply voltage terminal. The order of the input signals received by the two transistors is reversed between the two switching branches (82, 83 and 84, 85) to compensate for any duty cycle asymmetries. A frequency divider (32) divides the output of the NAND gate (31) to complete the duty cycle adjustment.

Abstract: A single ended sense amplifier that not only preserves the high speed feature of the ordinary .vertline.V.sub.TP .vertline., the threshold voltage of a PMOS transistor, but also eliminates the current leakage problem of conventional designs. The single-ended sense amplifier uses seven transistors and one phase clock instead of eleven transistors and two phase clocks as used in the prior art.

Abstract: A dynamic random access memory (DRAM) of 2/3 VDD precharge scheme is disclosed. A latch driving circuit controls the voltage of the common node of a sense latch so as to limit the downward voltage swing of bitlines to 1/3 VDD, a low level restore voltage. The sense latch is coupled to a pair of I/O data lines through PMOS FET column switches. This invention provides high speed memory operation and reduces power consumption.

Abstract: Reduced manufacturing costs and wafer size, lower power consumption, and increased operating speed are achieved in memory circuits by providing a novel sense amplifier design that is most sensitive to voltages variations around the source voltage (V.sub.dd). The sense amplifier includes two inverters that are regeneratively cross-coupled through a circuit that is controlled by a system clock. The inverters are powered from the bit lines that couple the sense amplifier to a memory cell. Novel applications of the sense amplifier in memory circuits also are described.

Abstract: A high-speed memory employing the pipeline technique is disclosed, in which the minimum operating cycle time is reduced by use of a latch circuit for a small signal using a bipolar transistor. A small-signal latch circuit operating at a signal smaller than an output signal level is inserted between an amplifier circuit for amplifying the data held in a memory cell circuit and an output buffer circuit. A switch signal is also interposed between the latch circuit and the amplifier circuit, thereby shortening the cycle time.