Abstract: A Negative Bias Temperature Instability (NBTI) tolerant sense amplifier is provided. The sense amplifier includes an input stage having a pair of balanced isolation devices. Each of the balanced isolation devices has an input connected to receive a separate one of a pair of differential input signals. Each of the balanced isolation devices also has a gate that is connected to receive a common bias voltage. The sense amplifier further includes a sense stage connected to the input stage. The sense stage is configured to receive and amplify a higher signal to be provided by the pair of balanced isolation devices. The sense amplifier is also equipped to operate a low voltage levels.

Abstract: Systems and methods for reducing or eliminating the effect of timing variations in signals generated by devices that are subject to the history effect, wherein devices are enabled using a combination of timing signals, some of which are subject to timing variations arising from the history effect, and some of which are not. In one embodiment, a sense amplifier includes a pair of serially configured transistors that couple the sense amplifier to ground. One of the transistors is switched on/off by a clock signal that is not subject to history-effect timing variations, and the other is switched on/off by a signal that is subject to such variations. The second signal has pulses that are selectively delayed so that they will (or will not) overlap with the pulses of the clock signal in a controlled manner.

Abstract: A flipflop. In the flipflop, a differential pair is coupled to two input signals inverse to each other. A first latch unit is connected to the differential pair in parallel, and includes a first node and a second node coupled to generate complementary latch signals according to the first and second data signals. A signal amplification circuit is coupled to the differential pair and the first latch unit to generate complementary amplified signals according to the complementary latch signals. A second latch unit is coupled to the signal amplifier circuit to generate complementary static output signals according to the complementary amplified signals and to maintain the complementary static output signals.

Abstract: A device to control a sense amplifier comprise a resetable control circuit containing a first input, a second input, a third input, and an output; the first input coupled to the output or to a ground; the second input coupled to receive a start signal; the third input coupled to receive output signals of the sense amplifier; the output coupled to the sense amplifier.

Abstract: An integrated circuit has one or more components that operate with reference to a distributed reference voltage. A reference voltage driver produces a compensated reference voltage, and the compensated reference voltage is distributed to form the distributed reference voltage at the components. Due to factors such as trace resistance and gate leakage, the distributed reference voltage is degraded relative to the compensated reference voltage. The reference voltage driver is responsive to feedback derived from the distributed reference voltage to adjust the compensated reference voltage so that the distributed reference voltage is approximately equal to a nominal reference voltage.

Abstract: A sense amplifying circuit and a bit comparator having the sense amplifying circuit. The sense amplifying circuit may include a selecting unit, a sensing unit, a latching unit, an output unit, and a switching unit. The selecting unit may select one pair from a first pair of a first signal and a first inverted signal and a second pair of a second signal and a second inverted signal, in response to a selection signal and an inverted selection signal. The sensing unit may sense voltage levels of one pair of signals selected from the first pair and the second pair. The latching unit may precharge first and second nodes in response to a clock signal and controls voltage levels of the first and second nodes in response to a sensing result of the sensing unit. The output unit may invert the voltage levels of the first and second nodes to generate first and second output signals. The switching unit is capable of controlling the operation of the selecting unit in response to the clock signal.

Abstract: In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch with integrated testability. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, three voting structures with inputs from the first, second, and third settable memory elements, determine the logical value held on each of the settable memory elements. Data may be scanned into and out of the second settable memory element. Data is propagated through the buffer into the third settable memory element. The third settable memory element may be used to scan data out of the triple redundant latch. The propagation delay through a latch is the only propagation delay of the triple redundant latch.

Abstract: A sense-amplifier based on current-source-evaluation. Compared to conventional sense-amplifiers, a design based on static-current sources scales better to small transistor geometries. The design has lower power consumption, reduced noise, and improved clock scaling.

Abstract: A first sense amplifier has complementary inputs and outputs coupled between a pair of complementary sense lines. Each sense line is connected to a respective complementary digit line through a coupling transistor. The coupling transistors are activated during an initial sensing period to couple a differential voltage from the digit lines to the sense lines. The sense lines are then isolated from the digit lines to allow the first sense amplifier to respond to the differential voltage without being loaded by the capacitance of the digit lines. The sense lines are also coupled to complementary inputs of a second sense amplifier that has complementary outputs coupled to the digit lines. By coupling the inputs of the second sense amplifier to the sense lines rather than the digit lines, the differential voltage applied to the second sense amplifier increases faster than the increase of the differential voltage between the digit lines.

Abstract: In a DRAM memory circuit, the sense amplifiers, for amplifying the differential voltage sensed between the cores of a bit line, in each case contain two transistor circuits, each of which has two switching transistors. The first transistor circuit pulls the lower potential of the sensed differential voltage down to a defined low logic potential. The second transistor circuit pulls the higher potential up to a defined high logic potential. According to the invention, all the transistors in the sense amplifier are field-effect transistors of the same conduction type, in the case of which the channel is at low impedance if the gate potential is higher than the source potential at least by the amount of the threshold voltage Vth.

Abstract: A differential output circuit includes first and second inputs, first and second outputs, a resistor element connected between the outputs, first and second N-channel MISFETs, and first and second P-channel MISFETs. The inputs respectively receive first and second complementary input signals. The first N-channel MISFET has a source connected to the first input, a gate receiving a power supply potential, and a drain connected to the first output. The second N-channel MISFET has a source connected to the second input, a gate receiving the power supply potential, and a drain connected to the second output. The first P-channel MISFET has a source receiving the power supply potential, a gate connected to the second input, and a drain connected to the first output. The second P-channel MISFET has a source receiving the power supply potential, a gate connected to the first input, and a drain connected to the second output.

Abstract: An input circuit includes a data input unit for receiving input data of the input circuit. A data latch unit latches output data of the input circuit. A reset unit resets the data latch unit in response to a first logic level of a first clock signal. A latch enhancement unit enhances the latching operation of the data latch unit in response to a first logic level of a second clock signal that is delayed in phase from the first clock signal. A clock synchronization unit transfers the input data from the input unit to the data latch unit in response to a second logic level of the first clock signal, the clock synchronization unit blocking a feedthrough current that flows through the reset unit, the data latch unit, and the latch enhancement unit when the first and second clock signals are in a first logic level state.

Abstract: In a crosspoint switch, both input buses and output buses are driven at low swing. Self-timed, differential, push-pull, low swing driver circuits drive the input buses and are provided in the crosspoints to drive the output buses. Clocked, regenerative sense amplifiers are provided in crosspoints and at outputs of the data buses.

Abstract: A latch circuit capable of ensuring race-free staging for signals in dynamic logic circuits is disclosed. The latch circuit includes four separate logic gates. The first inputs of the first and second logic gates are connected to a first and second precharged internal nodes of the dynamic logic circuit, respectively. The second inputs of the first and second gates are connected to a first and second differential outputs of the dynamic logic circuit, respectively. The first inputs of the third and fourth gates are connected to an output of the first and second logic gates, respectively. The second input of the fourth gate is connected to an output of the third logic gate to provide a first output for the latch circuit. Similarly, the second input of the third logic gate is connected to the output of the fourth logic gate to provide a second output for the latch circuit.

Abstract: A sensor for a switching circuit detects the logical state of the switching circuit by monitoring the current flow through the switching circuit. The current flow is conditioned by one or more current limiters and a voltage regulator, coupled in series with the switching circuit. The sensor also includes a current limit control circuit coupled to each of the current limiters. The sensor is effectively shielded from the effect of parasitic capacitance in the switching device because the current flow through the switching circuit reacts immediately and without regard to the level of parasitic capacitance whenever the switching circuit makes a state change.

Abstract: A sense amplifier circuit includes a latch circuit to enhance the speed of a sensing operation and to obviate the need for a latch circuit to capture the output value of the sense amplifier circuit. In one embodiment, first and second differential amplifiers provide a differential signal to the latch circuit. The high gain in the latch circuit resolves the differential signal to a logic signal, which is then provided to an output amplifier. In one embodiment, the differential signal is provided to the latch circuit after the differential signal across the input terminals of the first and second differential amplifiers exceeds a predetermined value.

Abstract: In order to provide a comparator circuit without generating a malfunction, the comparator circuit according to the present invention may comprise a comparator circuit including a differential amplification circuit having a differential pair transistor (M1, M2) for inputting a signal as an object of comparison, and a current mirror load circuit (M3, M4, M5, M6); a latch circuit having inversion amplifiers that are configured so that an input of one amplifier becomes an input of other amplifier so as to amplify a differential output signal outputted from the current mirror load circuit in accordance with a magnitude relation of the signal as an object of comparison; an equalization transistor (M9) for equalizing a signal of the differential amplification circuit; a delay circuit (M13, M14,M15, M16) for generating a signal to delay a control signal to be inputted in a control electrode of the equalization transistor; and a control transistor (M10) for inputting an output signal of the delay circuit in the contro

Abstract: A sampling receiver includes: at least one slave latch circuit; and at least one master latch circuit which further includes: at least one differential input transistor pair, and at least one bistable circuit. Output terminals of the at least one differential input transistor pair and output terminals of the at least one bistable circuit are coupled to the at least one slave latch circuit but in parallel to each other with reference to the at least one slave latch circuit for the purpose of reducing an output impedance to allow the sampling receiver to exhibit a high speed latch operation.

Abstract: A method and circuit are disclosed for detecting the performance of an oscillator circuit. In particular, the circuit may detect a signal, such as the output of the oscillator circuit, failing to oscillate as desired. The second circuit may be capable of detecting whether the signal oscillates at a frequency that is less than a predetermined frequency. The second circuit may include timing circuits for determining whether the signal remains in a first logic state for at least a predetermined period of time and whether the signal remains in a second logic state for at least the predetermined period of time.

Abstract: A data latch circuit and method for improving operating speed therein may provide a reduction in delay time. The data latch circuit includes a sense amplifying unit outputting a first signal in response to input data, a first inverted signal in response to a clock signal, a second signal in response to given cascode data, and a second inverted signal in response to the clock signal. A clock latch unit may generate a gated clock signal to enable output of the given cascade data to the sense amplifying unit, in response to an enabling signal and the clock signal. A MUX unit outputs the first signal as output data and the first inverted signal as feedback data, or outputs the second signal as output data and second inverted signal as feedback data, based on the logic level of the enabling signal.

Abstract: A preferred embodiment includes a distributed network of a plurality of dynamically configurable bi-directional input/output (I/O) cells, each including a forward datapath having a first receiver, for receiving a first input signal from downstream driver on a first port of a signal line, coupled to a first driver for sending a first output signal to a first upstream receiver on a second port of the signal line; and a reverse datapath having a second receiver, for receiving a second input signal from a second downstream driver on the second port of the signal line, coupled to a second driver for sending a second output signal to a second upstream receiver on the first port of the signal line; wherein the first input signal and the second output signal are transmitted concurrently on the first port of the signal line.

Abstract: An integrated circuit has one or more components that operate with reference to a distributed reference voltage. A reference voltage driver produces a compensated reference voltage, and the compensated reference voltage is distributed to form the distributed reference voltage at the components. Due to factors such as trace resistance and gate leakage, the distributed reference voltage is degraded relative to the compensated reference voltage. The reference voltage driver is responsive to feedback derived from the distributed reference voltage to adjust the compensated reference voltage so that the distributed reference voltage is approximately equal to a nominal reference voltage.

Abstract: A sense amplifier includes a feedback controlled bit line access scheme that feeds a sense amplifier output signal back to control operation of its associated bit line access transistor. This feedback may be implemented using a pair of inverter circuits each coupling a respective output signal to the control gate of the associated access transistor. Alternatively, the feedback may be implement using a logic gate which logically combines the sense amplifier output signals together to generate an output signal for controlling operation of both access transistors. The logic gate is preferably a NAND gate. The sense amplifier further includes a cross-connected feedback inversion circuit which inverts a sense amplifier output signal from a first latch inverter for application to a conducting line of a second latch inverter.

Abstract: A latch circuit includes a sample section for responding to complementary clock signals to sample complementary data signals during a sample period, a latch section for latching the sampled complementary data signals on latch output nodes to transfer the same through latch output nodes during a hold period, and a precharge section for precharging the latch output nodes during the sample period. The latch circuit has a smaller dead zone including a smaller setup time and a smaller hold time.

Abstract: A sense amplifier has a pair of internal nodes that are precharged to a power-supply level. A first pair of n-channel transistors supplies current to the internal nodes responsive to a pair of data signals, both of which are initially high. When one of the data signals begins falling toward the low level, the corresponding n-channel transistor immediately reduces the current supplied to one of the internal nodes. A second pair of n-channel transistors, cross-coupled to the internal nodes, amplifies the resulting potential difference between the internal nodes, thereby pulling down the potential of one of the internal nodes. An output signal is generated from one or both of the internal nodes. The output signal is obtained quickly, because amplification begins without delay.

Abstract: A circuit includes an input terminal, an output terminal and a latch. The input terminal receives an input signal. The latch is programmable with a value. The latch communicates the input signal to the output terminal in response to the circuit not being in a sleep mode and in response to the circuit being in the sleep mode, furnishes a second signal to the output terminal indicative of the value.

Abstract: An electronic circuit comprising an amplifier (AMP) for amplifying a binary input signal (Ui) including an input stage coupled to receive the binary input signal (Ui) comprising means for supplying a DC current to the input stage. The means supplies a current having a first (I1) current value to the input stage during a period of time that is approximately equal to the period of time corresponding to a transition phase from a first binary signal value to a second binary signal value. During the remaining time, the means supplies a current having a second (I2) current value which is smaller than the first (I1) current value. By virtue thereof, the electronic circuit only consumes a significant amount of power during a transition phase from the first binary signal value to the second binary signal value. The amplifier (AMP) can be implemented in all kinds of digital circuits, of which the digital voltage range (the difference between the second and the first binary values) must be increased.

Abstract: A control clocks generator and method thereof for a high speed sense amplifier generates control clocks by utilizing RC delay and gate delay, in combination with reference sensing delay induced from a reference sense amplifier, and thereby, is tracking well for the high speed sense amplifier with process, temperature and voltage variations.

Abstract: A multi-way set associative cache memory includes a set selection signal operating a sense amplifier. In reading data stored in a set, a set selection signal enables the sense amplifier to select one of sets while plural sets are active by a row address. The simplified structure of the present cache memory reduces power consumption by the rate of 1/N (N is the number of sets).

Abstract: Disclosed is an apparatus and method for decreasing the timing delay variation of output signals obtained from an SOI technology sense amplifier. The cross-coupled latch includes FETs where the body is connected to one of source and drain to minimize switching history effects while the input FETs have a higher than normal gate switching voltage to increase input signal sensitivity.

Abstract: A sense amplifier that is capable of sensing small differential voltage between two inputs with full voltage range includes a first inverter 305 and 306; a second inverter 307 and 308 cross coupled with the first inverter; a first transmission gate 301 coupled between a reference node REF and an input of the first inverter; a second transmission gate 302 coupled between a data node RD and an input of the second inverter; a pull-up enable switch 303 coupled between a high side voltage source node VDD, and the first and second inverters; and a pull-down enable switch 304 coupled between a low side voltage source node, and the first and second inverters.

Abstract: A negative voltage switch for use in flash memory. The switch has a control end and two voltage output ends, and includes two inverting units for transferring a positive voltage, two driving units for transferring a negative voltage, and two negative voltage pass-gate transistors for respectively transferring the negative voltage to the voltage outputs. Each inverting unit connects to a driving unit at a corresponding node, and each negative voltage pass-gate transistor connects to one of the nodes. According to a voltage at the control end, the switch turns on one inverting unit to transfer the positive voltage at the corresponding node, and the driving unit connected to the other node turns on to transfer the negative voltage to the corresponding negative voltage pass-gate transistor such that the negative voltage pass-gate transistor stops outputting the negative voltage at the other voltage output.

Abstract: The present invention provides a clock signal input circuit that is able to provide inverse internal clock signals generated by the same input buffer as the address and data signals which exhibit reduced skew. When a skewed external noninverse clock signal and a corresponding external inverse clock signal are passed through respective reference voltage input buffers there is no reduction in skew between the two internal signals. In a preferred embodiment, the invention provides back to back inverters connected to both lines carrying the noninverted and inverted internal clock signals. The slower internal clock signal has an extra inverter driving it when it switches states and the faster internal clock signal has an extra inverter fighting it when it switches states. The skew of the two signals is reduced, allowing for faster operation of the integrated circuit and a reduction in misread data signals.

Abstract: An active cascode differential latch for providing a logic output signal indicative of whether or not a first current is greater than a second current. The first and second currents are fed into two input ports of the active cascode differential latch. The active cascode differential latch has a relatively small input impedance, and has utility for comparators and discrete-time analog filters, to name just a few, particularly when used in high bandwidth and low voltage applications.

Abstract: A sense amplifier for a memory device comprising: a first sensing stage comprising a first sensing device and a second sensing device operably connected to a first sense line and a second sense line respectively, to reduce the capacitive load on the first sense line and second sense line. A source terminal of the sensing device is connected to a switchable current sink with drain terminal thereof connected to an input of a second sensing stage. The sense amplifier also includes a second sensing stage comprising cross-coupled inverters responsive to the first sensing stage, the second sensing stage is activated by a sense enable signal following a selected delay, and an output driver responsive to the second sensing stage.

Abstract: A sense amplifier adapted to sense an input signal on global bitlines, having an amplifier offset cancellation network and an offset equalization network. The amplifier offset cancellation network mitigates an inherent offset signal value, a dynamic offset signal value, or both, yet produces a residual offset signal value, which is substantially eliminated by the offset equalization network. The sense amplifier also can include an isolation circuit to isolate the sense amplifier from the corresponding global bitlines when the sense amplifier is unused. Also, a charge-sharing circuit is used to share charge between the bitlines when the sense amplifier is activated, thus producing a limited voltage swing on the bit lines. The sense amplifier uses an amplifier offset cancellation network having multiple precharge-and-balance transistors, and an offset equalization network having at least one balancing transistor.

Abstract: A sensor for a switching circuit detects the logical state of the switching circuit by monitoring the current flow through the switching circuit. The current flow is conditioned by one or more current limiters and a voltage regulator, coupled in series with the switching circuit. The sensor also includes a current limit control circuit coupled to each of the current limiters. The sensor is effectively shielded from the effect of parasitic capacitance in the switching device because the current flow through the switching circuit reacts immediately and without regard to the level of parasitic capacitance whenever the switching circuit makes a state change.

Abstract: A circuit including a differential sense circuit and a latch, the differential sense circuit and the latch coupled so as to form a differential sense latch such that, in operation, an electronic signal stored in the latch is retained for at least one clock cycle.

Abstract: A sense amplifier type input receiver includes a differential receiver circuit operatively coupled to an output stage. The output stage includes a pass gate enabled latch. The differential receiver circuit may output a first differential output and a second differential output. The output stage may include a first pass gate operatively coupled between the first differential output and an output of the output stage, a second pass gate operatively coupled between the second differential output and the pass gate enabled latch, and the pass gate enabled latch may be operatively coupled to the output of the output stage.

Abstract: Structures and methods for improving sense amplifier operation are provided. A first embodiment includes a sense amplifier having a pair of cross-coupled inverters. Each inverter includes a transistor of a first conductivity type and a pair of transistors of a second conductivity type which are coupled at a drain region and are coupled at a source region. The drain region for the pair of transistors is coupled to a drain region of the transistor of the first conductivity type. A pair of input transmission lines are included where each one of the pair of input transmission lines is coupled to a gate of a first one of the pair of transistors in each inverter. A pair of output transmission lines is included where each one of the pair of output transmission lines is coupled to the drain region of the pair of transistors and the drain region of the transistor of the first conductivity type in each inverter.

Abstract: A sense amplifier for use in a memory device and in a memory-resident system. The sense amplifier operates on a lower voltage consistent with the voltage range of the differential input data and the sense amplifier further operates on a higher voltage to level-shift the output signal concurrently with the sensing operation. The sense amplifier includes a pair of differential cross-coupled inverters whose inputs are coupled to receive the data from the memory. Once the input nodes of the cross-coupled inverters are charged, the cross-coupled inverters are further coupled to pull-up and pull-down circuits that span the higher voltage range for performing the level-shifting functionality. In order to recondition the sense amplifier for a subsequent sensing process, a clamp circuit shorts the level-shifted outputs together to prevent a higher voltage level from being inadvertently passed to the memory device when isolating pass gates are reactivated.

Abstract: A low power latch sense amplifier for electrically being coupled to a bit line of a memory cell array is disclosed. The low power latch sense amplifier comprises a common gate sense amplifier and an activated latch register. The common gate sense amplifier comprising a current source and a biased metal-oxide semiconductor is applied for sensing the current of the bit line. The current source and the biased MOS are coupled to a first node, and the common gate sense amplifier outputs a sensing signal at the first node. The activated latch register comprises a first clock signal-synchronized inverter which includes a first inverter and a first switch. The first inverter responds to the sensing signal, and the first inverter outputs a first inverter output signal. The first switch is controlled by a first set of control signal, and the first inverter output signal is corresponding to the sensing signal when the first switch is turned on.

Abstract: There is provided a latched comparison circuit for generating complementary latched output signals. The latched comparison circuit includes a comparator circuit for comparing an input address with a redundant address for generating a comparison output signal. The latched comparison circuit further includes a flip-flop circuit coupled to the comparison output signal for latching the comparison output signal and for providing complementary latched comparison output signals in response to a clock signal.

Abstract: An input receiver controls an offset voltage by using an output feedback signal to improve a sense speed. The input receiver includes a pre-amplifier that controls an offset voltage in response to a feedback signal and amplifies an input signal with reference to a reference voltage. A sense amplifier amplifies an output signal and an inverted output signal of the pre-amplifier in response to a clock signal. A latch circuit latches an output signal and an inverted output signal of the sense amplifier. An inversion circuit uses the reference voltage as a power supply voltage and inverts an inverted output signal of the latch circuit. In addition, an output signal of the inversion circuit is supplied as the feedback signal. Alternatively, the output signal of the latch circuit may be directly supplied to the pre-amplifier as the feedback signal while not using the inversion circuit.

Abstract: Clocked full-rail differential logic circuits with sense amplifier and shut-off are activated by a delayed clock and include a sense amplifier circuit that is triggered by a second delayed clock and a shut-off device. The addition of the sense amplifier circuit, and second delayed clock signal allows the sense amplifier circuit to act as the driver and therefore there is no need for increasing the size of the differential logic network to provide a driver function. The addition of the shut-off device provides a full-rail differential logic circuit with shut-off that does not experience the large “dip” experienced by prior art full-rail differential logic circuits and is therefore more power efficient.

Abstract: An amplifier in a semiconductor integrated circuit includes a current-mirror typed differential amplifier and a cross-coupled differential amplifier, whereby a minute voltage difference from a bit line signal or a data bus signal is amplified. The amplifier for generating an amplified signal includes a load for coupling to a first voltage potential, a first sense amplifier responsive to a first data signal, and a second sense amplifier responsive to a second data signal. The first and second sense amplifiers are commonly coupled to the load, and the amplified signal of the first or second data signal is generated.

Abstract: A multiphase comparator circuit includes a first differential stage; a first switching arrangement for connecting an output of the first differential stage to an input of a load circuit; and two or more regeneration stages. Each regeneration stage is connected to a load circuit and to the first switching arrangement. A clock-controlled second switching arrangement selectively provides an operating current to the regeneration stages. The first and second switching arrangements have switches that are driven so as to operate the regeneration stages in a manner temporally offset from each other.

Abstract: An apparatus comprising a plurality of serially coupled delay cells configured to generate an output signal having a frequency varied in response to a control signal. Each of the delay cells may be configured to generate one or more intermediate signals in response to the control signal and present the intermediate signals to a next of the delay cells. One or more next to the last of the intermediate signals may be fed back to a first of the delay cells. One or more last of the intermediate signals may be presented as the output signal.

Abstract: A sense amplifier is provided for sensing an input voltage level of a data signal. Such a sense amplifier pre-charges, and subsequently discharges, a pair of nodes through a respective pair of discharge paths. Each of those discharge paths is capable of performing the discharge operation at a rate that is related to either a system voltage supply or an input logic level of the data signal. Because the discharge path that is associated with the data signal includes a greater amount of conductance, it can perform the discharge operation at a faster rate, even where the input logic level does not exceed the voltage of the system voltage supply. A determination is made as to which of the discharge is the faster and, responsively, a rail-to-rail output signal having the same polarity as the data signal, is generated. The input data signal is conveyed to the sense amplifier by a single wire. Also, the sense amplifier does not require a specialized reference voltage for proper operation.

Abstract: A sense amplifier circuit for sensing data fed to its data input terminal and operating on the data according to a pre-charge signal, a latch signal and a sense amplifier enable signal. The sense amplifier circuit includes a pre-charge sense circuit that receives data from a data input terminal and outputs a first output value as well as a latching circuit that receives the first output value and outputs a second output value within a preset period. The pre-charge sense circuit further includes a first circuit and a second circuit. The first circuit is capable of pre-charging the data input terminal to a preset potential level. The second circuit produces a first output value according to the input data. In addition, the first circuit and the second circuit are connected in parallel between a voltage source and a data input terminal.