Abstract: An over/under voltage protection circuit includes a voltage input terminal, a digital-to analog converter, a comparator, and a control circuit. The comparator includes a first input coupled to an output of the digital-to-analog converter, and a second input coupled to the voltage input terminal. The control circuit includes an output coupled to an input of the digital-to-analog converter, and an input coupled to an output of the comparator. The control circuit is configured to set the digital-to-analog converter to generate an overvoltage fault threshold responsive to the output of the comparator indicating that voltage of a signal at the voltage input terminal exceeds a threshold currently generated by the digital-to-analog converter.

Abstract: A switch sensor for sensing a state of a switch including a programmable memory, pulse generation circuitry, and comparator circuitry. The memory stores a state value indicative of a detected state of the switch. The pulse generation circuitry provides a pulse-train voltage signal to a first end of the switch, in which the pulse-train voltage signal is toggled between an active state for switch state detection and an inactive state for conserving power. A second terminal of the switch is coupled through resistive circuitry to a supply voltage node and may be coupled to an input terminal of the sensor. The comparator circuitry compares a state of the input terminal with the state value when the pulse-train voltage signal is in the active state for providing a state change signal indicative thereof.

Abstract: A dynamic error introduced by track-and-hold circuits can be reduced by using an input signal derivative to perform linear extrapolation during the hold period, allowing the output of the track-and-hold circuit to provide improved performance in reconstructing an undistorted input waveform, or to perform other applications such as demultiplexing. As described herein, a track-and-hold circuit and related techniques can include use of a first-order (e.g., linear) extrapolation. A first-order extrapolation can better approximate or reconstruct a signal during a specified hold duration, as compared to a zeroth-order technique. Use of analog circuits to implement the first-order extrapolation can one or more of reduce complexity of a circuit implementation or improve performance, such as by not requiring digital signal processing circuitry in performing the extrapolation.

Abstract: A digital constant on-time controller adaptable to a direct-current (DC)-to-DC converter includes a current sensing circuit that senses stored energy of the DC-to-DC converter, thereby generating a sense voltage; a semi-amplitude detector that detects half of a peak-to-peak amplitude of the sense voltage, thereby generating a semi-amplitude voltage; a DC voltage detector that detects a DC voltage across an effective series resistor of an energy storage circuit that provides the stored energy of the DC-to-DC converter, thereby generating a DC voltage; an arithmetic device that adds the sense voltage and the semi-amplitude voltage, from which the DC voltage and a predetermined reference signal are subtracted; and a pulse-width modulation (PWM) generator that generates a switch control signal according to a result of the arithmetic device.

Abstract: Transient or fault conditions for a switched capacitor power converter are detected by measuring one or more of internal voltages and/or currents associated with switching elements (e.g., transistors) or phase nodes, or voltages or currents at terminals of the converter, and based on these measurements detect that a condition has occurred when the measurements deviate from a predetermined range. Upon detection of the condition fault control circuitry alters operation of the converter, for example, by using a high voltage switch to electrically disconnect at least some of the switching elements from one or more terminals of the converter, or by altering timing characteristics of the phase signals.

Abstract: A solid-state imaging device and a camera system are disclosed. The solid-state imaging device includes a pixel unit and a pixel signal readout circuit. The pixel signal readout circuit includes a plurality of comparators disposed to correspond to a pixel column array, and a plurality of counters. Each counter includes a first amplifier, a second amplifier, and a mirror circuit to from a current mirror in parallel with the second amplifier. The first amplifier includes differential transistors, initializing switches connected between gates and collectors of the differential transistors, and first and second capacitors connected to each of the gates of the differential transistors. The second amplifier includes an initializing switch and a third capacitor. The mirror circuit includes a gate input transistor whose gate is inputted with a voltage sampled by the first amplifier or a voltage sampled by the second amplifier.

Abstract: A voltage selector circuit is described. The voltage selector circuit includes a first voltage input, a second voltage input, and a voltage comparison input. The voltage selector circuit also includes a first voltage selector connected to an output. The first voltage selector is configured to compare the first voltage input and the second voltage input to the voltage comparison input. The voltage selector circuit also includes a second voltage selector connected to the output. The second voltage selector is configured to compare the first voltage input to the second voltage input using an early trigger, such that the second voltage selector is configured to switch on before the first voltage selector switches off.

Abstract: A comparator used in a clock signal generation circuit compares two input signals and generates an output signal. The comparator has first and second input transistors coupled to the input signals. First and second hysteresis transistors are coupled between the input transistors and an output stage of the comparator, and apply hysteresis to a comparison of the input signals. First and second hysteresis control transistors are coupled between the input transistors and the hysteresis transistors to isolate the hysteresis transistors from the input transistors under control of a hysteresis enable signal. The comparator is operable in a first mode or a second mode based on a hysteresis enable signal. In the first mode the comparator applies hysteresis to the comparison of the input signals and in the second mode, compares the input signals without hysteresis.

Abstract: A voltage detection circuit including a comparator circuit, a tunable gain circuit and a switch circuit is disclosed. The comparator circuit has a first input terminal and a second input terminal. The tunable gain circuit is coupled between the first input terminal and a reference signal. The tunable gain circuit has a plurality of gain configurations. The tunable gain circuit adjusts the reference signal and transmits the adjusted reference signal to the first input terminal. The switch circuit selectively transmits a signal under test or the reference signal to the second input terminal. When the voltage detection circuit is in an auto-trimming mode, the switch circuit transmits the reference signal to the second input terminal and the tunable gain circuit sequentially adopts the gain configurations until the comparator circuit detects that voltage levels of the first input terminal and the second input terminal are substantially equal.

Abstract: A ping pong comparator voltage monitoring circuit which includes first and second comparators having inputs connected to a voltage Vin to be monitored, and second inputs connected to first and second nodes, respectively. A multiplexer alternately couples the first and second comparator outputs to an output in response to a periodic control signal. A ground-referenced voltage Vref1 is provided at a third node and a voltage Vref2 referenced to Vref1 is at a fourth node. A hysteresis hyst1 is switchably connected between the third and first nodes, and a hysteresis hyst2 is switchably connected between the fourth and second nodes. Hyst1 and hyst2 are switched in when the mux output toggles due to a rising Vin, and are switched out when the mux output toggles due to a falling Vin.

Abstract: In one embodiment, an integrated circuit includes a pin and a current source for driving current through the pin into an external resistor such as a resistor on a circuit board to generate a pin voltage. The integrated circuit includes an analog-to-digital converter for converting the pin voltage into a digital value, such as an address for the integrated circuit.

Abstract: An integrated circuit device includes a reference voltage generator, which is configured to generate an adaptive reference voltage (Vref) that varies inversely relative to changes in magnitude of a data signal (DATA) received at an input thereof. This reference voltage generator includes a totem pole arrangement of at least two variable impedance elements having control terminals capacitively coupled (by respective capacitors) to the input. A current mirror is electrically coupled to the totem pole arrangement of at least two variable impedance elements. A comparator is also included. The comparator has a first input terminal that receives the adaptive reference voltage and a second input terminal that receives the data signal.

Abstract: A comparator having first and second stages can provide component offset compensation and improved dynamic range. The first stage can receive first and second input signals and produce first and second output signals. The second stage can be coupled to the first stage to receive the first and second output signals at first and second input terminals of the second stage. The second stage can provide a voltage to the first and second terminals that differs from the supply voltage by less than a voltage of a diode drop. The comparator is operable to receive input voltages that reach the supply voltage.

Abstract: A high-speed differential comparator circuit is provided with an accurately adjustable threshold voltage. Differential reference voltage signals are provided to control the threshold voltage of the comparator. The common mode voltage of the reference signals preferably tracks the common mode voltage of the differential high-speed serial data signal being processed by the comparator circuit.

Abstract: An apparatus for comparing differential input signal inputs is provided. The apparatus comprises a CMOS sense amplifier (which has having a first input terminal, a second input terminal, a first output terminal, and a second output terminal), a first output circuit (which has a first load capacitance), a second output circuit (which has a second load capacitance), and an isolation circuit. The isolation circuit is coupled between the first output terminal of the CMOS sense amplifier and the first output circuit and is coupled between the second output terminal of the CMOS sense amplifier and the second output terminal of the CMOS sense amplifier. The isolation circuit isolates the first and second load capacitances from the CMOS sense amplifier.

Abstract: A system and method for providing an accurate current reference using a low-power current source is disclosed. A preferred embodiment comprises a system comprises a first section and a second section. The first section comprises a first simple current reference, an accurate current reference, and a circuit that generates a digital error signal based upon a comparison of an output of the first simple current reference and an output of the accurate current reference. The second section comprises a second simple current reference providing a second reference current, an adjustment circuit providing an adjustment current based upon the digital error signal, and a circuit biased with current equivalent to a summation of the second reference current and the adjustment current. The first simple current reference and the second simple current reference may be equivalent circuits.

Abstract: A system for detecting a Zero Crossing point is provided. The system includes: a coupling unit connected between a high voltage side and a low voltage side of the system; and a zero crossing detector connected to the high voltage side and configured to divide a filtered mains voltage signal and to generate an output signal that indicates a zero crossing point of the filtered mains voltage signal.

Abstract: A correlated double sampling (CDS) circuit includes a correction circuit configured to receive an input pixel signal through a first node via a column line, correct the input pixel signal, and output the corrected pixel signal through a second node; and a comparator including first and second input terminals, the first input terminal being connected to the second node and being configured to receive the corrected pixel signal, and the second input terminal configured to receive a ramp signal, the comparator being configured to compare the corrected pixel signal with the ramp signal and output a comparison signal indicating a result of the comparing, wherein the correction circuit includes, a first capacitor connected between the first and second nodes, and one or more metal lines disposed adjacent to the first capacitor, and wherein at least one other capacitor is formed by the first capacitor and the metal line.

Abstract: A pseudo-differential input receiver is disclosed which is configured to support a wide-range of reference voltage Vref and a wide-range frequency interface with no parallel termination are described herein. The pseudo-differential receiver implementations described herein are very efficient in terms of area, power, and performance. A wide-frequency-range Vref-adjustable input receiver is described herein. The receiver can be configured with a Vref-monitoring PMOS helper FET or an enabled stacked PMOS helper FET to enable the receiver to work at Vref=0V like a conventional CMOS receiver. The receiver can also be configured with a Vref-monitoring NMOS helper FET to enable a Vref-based input receiver to work with programmability on bias currents & trip-point at Vref=(0.5˜0.7)Vdd, depending on the ratio of output driver's impedance and parallel on/off-die termination impedance.

Abstract: Embodiments of the present invention include an electronic circuit that reduces stress on a transistor. In one embodiment, the electronic circuit comprises a transistor and a reference generator circuit. The transistor may be a metal oxide semiconductor (MOS) transistor, for example. The MOS transistor has a gate terminal to receive an input voltage. The reference generator circuit selectively couples first and second reference voltages to a source terminal of the MOS transistor. The reference generator circuit senses the input voltage and provides the first reference voltage to the source terminal of the MOS transistor if the input voltage is greater than a threshold and the second reference voltage is coupled to the source terminal of the first MOS transistor if the input voltage is less than a threshold.

Abstract: A system and method for providing an accurate current reference using a low-power current source is disclosed. A preferred embodiment comprises a system comprises a first section and a second section. The first section comprises a first simple current reference, an accurate current reference, and a circuit that generates a digital error signal based upon a comparison of an output of the first simple current reference and an output of the accurate current reference. The second section comprises a second simple current reference providing a second reference current, an adjustment circuit providing an adjustment current based upon the digital error signal, and a circuit biased with current equivalent to a summation of the second reference current and the adjustment current. The first simple current reference and the second simple current reference may be equivalent circuits.

Abstract: A switched-capacitor circuit is disclosed. The switched-capacitor circuit includes a comparator having a first and second input, a first and second sampling capacitor, and a first and second switching circuitry. The first switching circuitry charges the first and second sampling capacitor with an input signal. The second switching circuitry selectively couples the first sampling capacitor with a reference voltage and selectively couples the second sampling capacitor and the first and second input of the comparator to a common voltage. The comparator performs a compare of the input signals against the reference voltage, and outputs a signal.

Abstract: A voltage sensing device with which high-precision voltage sensing is possible without the need to obtain a unique correction constant for each device. A pair of voltage input nodes NCk and NCk-1 is selected from voltage input nodes NC0-NCn in switch part 10, and they are connected to sensing input nodes NA and NB in two types of patterns with different polarity (forward connection, reverse connection). Sensing input nodes NA and NB are held at reference potential Vm by voltage sensing part 20, and current Ina and Inb corresponding to the voltage at voltage input nodes NCk and NCk-1 flows to input resistors RIk and RIk-1. Currents Ina and Inb are synthesized at different ratios in voltage sensing part 20, and sensed voltage signal S20 is generated according to the synthesized current Ic. Sensed voltage data S40 with low error is generated according to the difference between the two sensed voltage signals S20 generated in the two connection patterns.

Abstract: A minimum leading edge blanking (MLEB) signal generator is provided. The MLEB signal generator includes a buck unit and a signal generation unit. The buck unit receives an error amplification signal, and generates a reference blanking signal. The reference blanking signal has a voltage lower than a voltage of the error amplification signal. The signal generation unit receives the reference blanking signal, and generates the MLEB signal according to the current sensing signal. When the current sensing signal is equal to the reference blanking signal, the MLEB signal changes its voltage level. As such, the width of the MLEB signal is a time width of the high level or low level of the MLEB signal before the voltage level of the MLEB signal changes. The MLEB is provided to an external unit, such that the external unit can be prevented from misoperation, thus improving the electric performance in its entirety.

Abstract: A semiconductor device stabilizes an operation of an input buffer. A semiconductor device includes an input potential detection unit, an input buffer, and a current sink unit. The input potential detection unit outputs a detection signal in response to a level of an input signal. The input buffer buffers the input signal by differentially amplifying the input signal through a first current sink unit. The current sink unit receives the detection signal, and in response to the detection signal, performs an auxiliary differential amplifying operation with respect to the input signal buffered by the input buffer.

Abstract: A semiconductor device is capable of stably maintaining a voltage level of a shield line, even when a voltage level of an adjacent line is varied. The semiconductor device includes normal lines arranged for transfer of signals, a shield line arranged adjacently to the normal lines, a level shifting circuit for receiving an input signal swinging between a power supply voltage level and a ground voltage level, and shifting the input signal to an output signal swing between the power supply voltage level and a low voltage level lower than the ground voltage level by a predetermined level to output a shifted signal via the shield line, and a signal input unit for transferring the signal provided via the shield line to an output node.

Abstract: A semiconductor device minimizes generation of an output signal skew of an input buffer and thus stabilizes the operation of the semiconductor device. The semiconductor integrated circuit includes an input potential detection unit outputting a detection signal in response to a level of an input signal, an input buffer buffering the input signal, and an output path control unit that receives the output signal of the input buffer and the detection signal of the input potential detection unit and outputs an output driving signal in response to the level of the detection signal.

Abstract: A conversion circuit for converting a differential signal into a single-phase signal 1 has a source-follower amplifier 10 and a source-grounded amplifier 20. The source-follower amplifier 10 outputs a non-inverted signal IN of the differential signal the phase of which is not inverted. The source-grounded amplifier 20 inverts an inverted signal INX of the differential signal and adjusts its phase to that of the non-inverted signal IN. At point A, differential signals IN, INX are added and output as a single-phase signal OUT.

Abstract: Provided is a sensor circuit that is small in circuit scale, but is capable of temperature compensation. A reference voltage circuit (BL1) which compensates a temperature includes only a voltage divider circuit, and hence the sensor circuit is small in circuit scale. The sensor circuit is also capable of temperature compensation because temperature changes of a reference voltage (VTH1) and a reference voltage (VTH2) match a temperature change of an output signal (OUTA) of an amplifier circuit (AMP1) which is caused by a temperature change of an output signal of a Hall element (HAL1).

Abstract: An interface such a PCI-E interface may comprise a transmitter and a compensation circuit. In one embodiment, the transmitter may comprise a transmit driver, which may use a push-pull configuration. The transmit driver may require stable voltages such as (Vdd/2+0.25) and (Vdd/2?0.25) Volts. The compensation circuit may comprise a voltage generator circuit and a dummy driver circuit. The dummy driver may be a replica of the transmit driver. A correction module may generate correction factors based on the deviation of the voltages generated by the dummy driver from the voltages generated by the voltage generator. The voltages provided to the transmit driver are corrected based on the correction factors to compensate for the deviation.

Abstract: A switching matrix has a first number of inputs and a second number of outputs as well as a conductor arrangement and controllable switching elements by means of which the inputs can be connected with the outputs. The controllable switching elements are fashioned such that at least two independent control signals are required to trigger a switching event.

Abstract: A signal level shifting circuit, including an input stage circuit and an output signal latching circuit. The input stage circuit receives an input signal, wherein a voltage level of the input signal falls within a first predetermined voltage range. The output signal latching circuit is cascoded with the input stage circuit, and includes: a latching circuit for generating an output signal according to the input signal, wherein a voltage level of the output signal falls within a second predetermined voltage range, and the second predetermined voltage range is different from the first predetermined voltage range; and an activating circuit, coupled to the latching circuit, for selectively enabling or disabling the latching circuit, wherein when a level transition appears to the input signal, the activating circuit disables the latching circuit.

Abstract: An integrated circuit package includes a processing core for operating on a set of instructions to carry out predefined processes. A plurality of comparators perform compare operations within the integrated circuit package. At least one control register is associated with each of the plurality of comparators, and each of the plurality of comparators are software programmable to control a hysteresis of the comparators responsive to control bits established in the at least one control register of the comparator by the processing core. An amount of positive hysteresis is programmed via a first group of the control bits and an amount of negative hysteresis is programmed via a second group of the control bits.

Abstract: A comparator, comprising at least one current stage for providing a first current proportional to a difference between first and second comparator inputs, the first current being provided to an amplifier input; an amplifier for amplifying a current provided to the amplifier input and providing a comparator output; apparatus for introducing hysteresis, comprising at least one of a current source and a current sink, the current source being arranged to selectively source a source current to the amplifier input such that the comparator output changes from a first state to a second state when a difference between the first and second inputs rises above a first value, and the current sink being arranged to selectively sink a sink current from the amplifier input such that the comparator output changes from the second state to the first state when the difference between the first and second inputs falls below a second value; and apparatus for controlling at least one of the source current and the sink current to be

Abstract: The potential comparator includes input wires 3 and 4 that input a differential signal output from a test object 2, a high-threshold side divided-voltage generating section 5 that acquires the differential signal from each of the input wires 3 and 4 and generates and outputs the first divided voltage and the second divided voltage that are a divided voltage based on a predetermined high threshold potential VOH and an electric potential of the acquired differential signal, a high-threshold side potential comparator 6 that derives a magnitude relation between the first and the second divided voltages output from the high-threshold side divided-voltage generating section 5.

Abstract: Aspects of a method and system for a linear regulator with high bandwidth, PSRR, and a wide range of output current are provided. A method for isolating voltages in a circuit may comprise applying a reference voltage to an isolation resistor based on a supply voltage. An internal voltage at a reference point may be determined based on the applied reference voltage, and a maximum and/or minimum voltage may be determined based on the internal voltage. A plurality of output transistor devices may be controlled based on either the maximum voltage or minimum voltage. The reference voltage may be modified based on controlling the plurality of output transistor devices. By turning ON and OFF the output transistor devices, a much wider operating range is facilitated.

Abstract: A plurality of reference voltages are generated by a reference voltage generation circuit. A plurality of comparators is supplied respectively with an analog input voltage and any two reference voltages out of the plurality of reference voltages. A threshold voltage of each of the comparators is adjusted according to the two reference voltages. Each of the comparators compares the analog input voltage with the threshold voltage. A plurality of comparison output signals of the plurality of comparators are supplied to an encoder circuit, and digital signals which correspond to the plurality of comparison output signals are output.

Abstract: A voltage-controlled oscillator includes a plurality of variable delay circuits, wherein a first differential output signal of an adjacent previous stage is provided as a first differential input signal and a second differential output signal of a second previous stage is provided as a second differential input signal. Each variable delay circuit includes a loading circuit including first and second loading units, a first input circuit including first and second input transistors gated by the first differential input signal, a second input circuit including third and fourth input transistors gated by the second differential input signal, first and second current sources connected between a first common node and a second power source and in electrical parallel with each other, and third and fourth current sources connected between a second common node and the second power source and in electrical parallel with each other.

Abstract: A circuitry comprises a comparator for comparing a signal received on a first input to a signal received on a second input. A control register associated with the first multiplexer stores control values enabling connection of one input of the first multiplexer to the output of the first multiplexer.

Abstract: A pseudo-differential input receiver is disclosed which is configured to support a wide-range of reference voltage Vref and a wide-range frequency interface with no parallel termination are described herein. The pseudo-differential receiver implementations described herein are very efficient in terms of area, power, and performance. A wide-frequency-range Vref-adjustable input receiver is described herein. The receiver can be configured with a Vref-monitoring PMOS helper FET or an enabled stacked PMOS helper FET to enable the receiver to work at Vref=0V like a conventional CMOS receiver. The receiver can also be configured with a Vref-monitoring NMOS helper FET to enable a Vref-based input receiver to work with programmability on bias currents & trip-point at Vref=(0.5˜0.7)Vdd, depending on the ratio of output driver's impedance and parallel on/off-die termination impedance.

Abstract: A comparator includes: a CMOS inverter constituted by a combination of a first p-channel MOS transistor and a first n-channel MOS transistor; a second p-channel MOS transistor connected in parallel to the first p-channel MOS transistor in an analog input period, and disconnected from the first p-channel MOS transistor in a comparison period; and a second n-channel MOS transistor connected in parallel to the first n-channel MOS transistor in the analog input period, and disconnected from the first n-channel MOS transistor in the comparison period.

Abstract: A current-loop output circuit for an industrial controller provides for low power dissipation and reduced part count by driving current loads of different resistances directly from a switched voltage source. Proper filtering and design of a feedback loop allows the necessary transient response times to be obtained.

Abstract: A receiver for receiving a switched signal on a communication line (1), such as a LIN bus, the signal varying between first and second voltage levels (sup, ground). The receiver comprises a comparator (31, 54) responsive to the relative values of the received signal voltage level (Vlin) and an input reference voltage level (Vsup). The comparator (31, 54) comprises a current generator (40, 41) selectively operatble when the recieved signal is asserted to produce an input current (Iin) which is a function of the received signal voltage level (Vlin) and a reference current (Isup) which is a function of the input reference voltage level (Vsup), and output means (28, 32, 31; 55, 56) responsive to the relative values of the input current (Iin) and the reference current (Isup). The output means (28, 32, 31; 56) is supplied with power at a voltage (VDD) substantially lower than the difference between the first and second voltage levels (Vsup, ground).

Abstract: A circuit and a method are provided to produce a novel comparator with Schmitt trigger hysteresis character. The circuit includes a current source which controls the magnitude of current flow through this comparator circuit. It has a first logic device which is turned ON by a reference voltage, and a second logic device is turned ON by a comparator input voltage. A first feedback device is turned ON by a negative comparator output. A first parallel resistor is connected in parallel to the first feedback device. A second feedback device is turned ON by a positive comparator output. A second parallel resistor is connected in parallel to the second feedback device. The first and second parallel resistors are used to provide the differential comparator with switching voltage offsets which result in the Schmitt trigger hysteresis character.

Abstract: A differential input comparator circuit comprises an input stage comprising dual polarity input voltages and an output stage adapted to output a differential voltage based on the input voltages, wherein the differential voltage is adapted to be transmitted to a comparator and wherein the circuit has high input impedance and works with high input voltage swings.

Abstract: The invention relates to a level converter for converting a signal (in) comprising a first voltage level (Vint) and supplied to the level converter, to a signal (Out) including a second voltage level (Vsupply) differing from the first voltage level (Vint). The level converter includes an amplifier device. The level converter is additionally supplied with a signal obtained from the signal (in) and delayed for compensating for distortions contained in said signal (in).

Abstract: Aspects of a method and system for a linear regulator with high bandwidth, PSRR, and a wide range of output current are provided. A method for isolating voltages in a circuit may comprise applying a reference voltage to an isolation resistor based on a supply voltage. An internal voltage at a reference point may be determined based on the applied reference voltage, and a maximum and/or minimum voltage may be determined based on the internal voltage. A plurality of output transistor devices may be controlled based on either the maximum voltage or minimum voltage. The reference voltage may be modified based on controlling the plurality of output transistor devices. By turning ON and OFF the output transistor devices, a much wider operating range is facilitated.

Abstract: A semiconductor physical quantity sensing device to perform electrical trimming at low cost by using a CMOS manufacturing process and a small number of terminals. The semiconductor physical quantity sensing device includes a wheatstone bridge circuit, which is a sensor element, an auxiliary memory circuit, which stores provisional trimming data, a main memory circuit, which stores finalized trimming data, an adjusting circuit, which adjusts the output characteristics of the sensor element based on trimming data stored in the auxiliary memory circuit or the main memory circuit, with the elements and circuits being only configured of active elements and passive elements manufactured by way of the CMOS manufacturing process formed on a same semiconductor chip.

Abstract: Current through a wire is sensed with a shunt resistor and a sense resistor in a current divider circuit. The values of the shunt resistor and sense resistor are related to provide a specified gain ratio to increase a dynamic range of current measurement. The sense resistor is a trimmable resistor, the configuration of which can be discerned from a look-up table based on a level of precision needed for current measurement. The two resistors can also be related by thermal coefficients to improve linearity of current measurements.

Abstract: A voltage regulation scheme for an on-chip voltage generator includes a voltage sensing circuit (VSC) and a configurable buffer circuit (CBC) to regulate the on-chip voltage generator. The CBC generates an output signal that is received by the on-chip voltage generator to activate and de-activate the voltage generator. The VSC generates a voltage level detection (VLD) signal having a voltage level that is a function of the level of the on-chip generated voltage. The CBC receives a control signal that is used to dynamically configure the chip into an operational mode, as well as the VLD signal. In response to the control signal, the switch threshold of the CBC is configured to a predetermined level corresponding to the selected operational mode. The predetermined trip point causes the CBC to appropriately activate and de-activate the on-chip voltage generator to regulate the on-chip generated voltage at the level required by the configured operational mode.