Abstract: So as to compare an amplitude of a differential input signal to a threshold, a signal detection circuit includes first and second matched input signal level-shifters, a comparator threshold generation circuit, and a two-stage comparator. The differential input signal is comprised of a true input signal and a complement input signal, and the first input signal level-shifter is coupled to the true input signal, and the second input level-shifter is coupled to the complement input signal. The comparator threshold generation circuit is matched to the input signal level-shifters and outputs first and second compare voltages. The first stage of the two-stage comparator outputs a low signal if the more positive of the level-shifted input signals is greater than the more positive of the compare voltages.

Abstract: A method and structure for comparing an input signal to a reference signal using a comparator comprises a circuit for setting a trip point of a rising edge of an input signal according to a value of an external voltage reference; and at least two transistors, in the circuit, for setting a trip point of a falling edge of an input signal, according to a width-to-length ratio of the at least two transistors. Moreover, the at least two transistors comprises a first transistor of length (Lx) and a width of (Wx); and a second transistor of length (Ly) and a width of (Wy), wherein the width-to-length ratio equals (WxLy)/(WyLx). The trip point of a falling edge of an input signal increases (decreases) by increasing (decreasing) the width-to-length ratio.

Abstract: Disclosed herein is a method and system for calibrating line drive currents in systems that generate data signals by varying line drive currents and that interpret the data signals by comparing them to one or more reference voltages. The calibration includes varying the line drive current at a transmitting component. At different line drive currents, a receiver reference voltage is varied while the transmitting component transmits data to a receiving component. At each line drive current, the system records the highest and lowest receiver reference voltages at which data errors do not occur. The system then examines the recorded high and low receiver reference voltages to determine a desirable line drive current.

Abstract: A drive device for a light-emitting component including a reference source, which generates a current specification signal specifying a desired current through the light-emitting component, a current mirror circuit, which generates a current equal to a fraction of the actual current through the light-emitting component, and a regulating device having a first input and a second input, the first input being connected to the current mirror circuit and the second input being connected to the reference source. In this case, the regulating device generates a regulation signal that regulates the current through the light-emitting component in such a way that the deviation between the desired current and the actual current becomes minimal.

Abstract: A method of automatically determining a peak level of a signal propagated on a carrier medium, such as for example POTS wiring, includes detecting a traversal of a noise threshold level by a data signal. The noise threshold level is determined relative to a noise floor. A determination is then made as to whether the data signal traverses a peak level within a predetermined time interval after the detection of the traversal of the noise threshold level. The peak level is then varied in accordance with the determination of whether the data signal traversed the peak level within the predetermined time interval. For example, should the data signal not traversed the peak level within the predetermined time interval, the peak level may be lowered. Alternatively, should the data signal traversed the peak level within the predetermined time interval, the peak level may be raised.

Abstract: A method of dynamically, and automatically, varying the sensitivity of a receiver coupled to receive signals on a carrier medium, such as for example POTS wiring, includes the step of detecting whether more than a predetermined number of noise events, such as for example traversals of a noise threshold level, occur within a predetermined time. If the predetermined number of noise events occur, the sensitivity of the receiver is automatically varied by a predetermined increment. For example, the noise threshold level may be raised by a predetermined voltage to vary the sensitivity of the receiver.

Abstract: A reference voltage is moved dynamically towards a voltage level of the last received value. The movement takes place over a predetermined fraction of a bit-time. The amount of movement is limited so that successive logical values don't result in an unusable reference voltage level. When the output of a receiver changes, a state machine sequences the selection of analog reference voltage inputs to a multiplexer to move an output reference voltage towards a steady-state signal voltage level for the value that was just received. When the sequence is complete, the state machine keeps the last value selected on the output until the output of the receiver changes value.

Abstract: A reference voltage is moved dynamically towards a voltage level of the last received value. The movement takes place over a predetermined fraction of a bit-time. The amount of movement is limited so that successive logical values don't result in an unusable reference voltage level. When the output of a receiver changes, a state machine sequences the selection of analog reference voltage inputs to a multiplexer to move an output reference voltage towards a steady-state signal voltage level for the value that was just received. When the sequence is complete, the state machine keeps the last value selected on the output until the output of the receiver changes value.

Abstract: Disclosed are novel methods and apparatus for efficiently providing high-resolution single-ended source synchronous receivers. In an embodiment of the present invention, a source-synchronous receiver is disclosed. The receiver includes: a first amplifier to receive a clock signal and a data signal, the first amplifier providing a first output signal; a second amplifier to receive a complementary clock signal and the data signal, the second amplifier providing a second output signal; a third amplifier to receive the clock signal and the data signal, the third amplifier providing a third output signal, the second and third output signals being combined to provide a fifth output; and a fourth amplifier to receive the complementary clock signal and the data signal, the fourth amplifier providing a fourth output signal, the first and fourth output signals being combined to provide a sixth output signal.

Abstract: A method of processing a pulse response with an adaptive threshold and corresponding receiver. According to the method, an adaptive threshold is calculated that is a function of a maximum reached by the pulse response, noise, and a coefficient adjustable between 0 and 1. The processing only comes into operation for signals that exceed this threshold. Such a method may find application notably to digital radio-communications with spread spectrum.

Abstract: A method and apparatus for signal processing may include an electronic circuit comprising a receiver configured to receive a signal and a dynamic threshold circuit configured to process the signal. The dynamic threshold circuit is configured to compare the signal to a threshold and generate an output signal according to the comparison. The dynamic threshold circuit is also configured to change the threshold to a selected level at a selected time. In various embodiments, the selected level is selected to be a level between the level of the input signal and a midpoint of the input signal. In another embodiment, the selected time is selected to correspond to a stabilization time of the input signal.

Abstract: A programmable transducer device that includes a signal source (e.g., a sensor) and a transducer output to output a transducer output signal and to receive a control signal from an external control unit. The control signal is superposed on the transducer output signal, and is detected at the transducer output from a resultant superposition signal by a detector circuit. The transducer output signal and the control signal may co-exist on the transducer output. Advantageously, providing a programmable transducer device that is actuated by control signals conducted through the transducer output and does not need to be switched over to a special receiving state, ensures the uninterrupted transmission of transducer output signals even while the control signals are received by the programmable transducer device. In addition, no additional signal path is required for programming.

Abstract: A non-delayed input signal is provided to a first comparator input and, a delayed input signal is applied to a second comparator input. An offset voltage is applied between the delayed and non-delayed signals at the comparator inputs. When an input pulse appears on the input signal, the non-delayed input signal will rise immediately and maintain itself more positive than the delayed input, keeping the comparator output inactive. As long as the input signal is rising, the comparator output is maintained low, or inactive. When the non-delayed signal reaches its peak and turns downward, the delayed input signal is still rising and crosses over the first pulse, creating a change of state at the comparator output to a high or active state. The signal edge resulting from this change of start represents initial detection of an input pulse. The time of occurrence of this detection edge is substantially independent of the pulse amplitude.

Abstract: The present invention provides a tunable circuit for quickly optimizing an electrical field generated by the F-N tunneling operation. To optimize this electrical field, the charging of a positive charge pump is begun after the charging of a negative charge pump. The tunable circuit of the present invention provides a means to detect the optimal negative voltage at which pumping of the positive voltage should begin. The tunable circuit includes a resistor chain coupled between a first reference voltage and a negative voltage from the negative charge pump. When charging of the negative charge pump begins, a comparator compares the voltage at a node within the resistor chain to a second reference voltage. In accordance with the present invention, the node voltage within the resistor chain is equal to the second reference voltage when the negative voltage is equal to the voltage to be detected. Thus, the comparator generates a trigger signal when the voltage at the node decreases to the second reference voltage.

Abstract: The present invention provides a tunable circuit for quickly optimizing an electrical field generated by the F-N tunneling operation. To optimize this electrical field, the charging of a positive charge pump is begun after the charging of a negative charge pump. The tunable circuit of the present invention provides a means to detect the optimal negative voltage at which pumping of the positive voltage should begin. The tunable circuit includes a resistor chain coupled between a first reference voltage and a negative voltage from the negative charge pump. When charging of the negative charge pump begins, a comparator compares the voltage at a node within the resistor chain to a second reference voltage. In accordance with the present invention, the node voltage within the resistor chain is equal to the second reference voltage when the negative voltage is equal to the voltage to be detected. Thus, the comparator generates a trigger signal when the voltage at the node decreases to the second reference voltage.

Abstract: Problems associated with using bipolar differential circuits over a wide common mode voltage range are solved using first and second amplifier circuits 3 and 5, respectively operating over first and second voltage sub-ranges. The low voltage differential signal (LVDS) 1 is applied across a pair of series connected resistors 7 and 9, and to the inputs of the amplifiers 3 and 5. The common mode voltage signal 11 is fed to the inputs of third and fourth amplifiers 15 and 17. The third and fourth amplifiers 15 and 17 ensure that the LVDS receiver has a constant linear transfer characteristic over the differential input signal range and over the full common mode range, especially over the amplifier transition region.

Abstract: A current sensing circuit connected to a power supply terminal and having at least one input terminal and at least one output terminal includes at least one bipolar transistor having a base, emitter and collector, at least one current mirror amplifier connected to the power supply terminal, the current mirror amplifier having an input connected to the collector and having at least one output connected to the emitter, and a DC voltage source connected to the base.

Abstract: A differential voltage magnitude comparator to receive a differential input signal and a differential reference signal, in which a magnitude difference of the differential input signal is compared to the magnitude reference of the differential reference signal. An output state depends on the magnitude difference of the differential input signal to the magnitude difference of the differential reference signal. If the magnitude difference of the differential input signal is below the magnitude difference of the differential reference signal, the output is in one state, but if the magnitude difference of the differential input signal is above the magnitude difference of the differential reference signal, the output is in the other state. The comparison and logical operation to provide the output states are generated in single stage.

Abstract: An integrated semiconductor circuit having a first operating mode and a second operating mode has a plurality of input buffers. At least one of the input buffers serves for controlling a changeover between the operating modes. The input buffer for controlling the changeover between the operating modes has a driver circuit with an inverter circuit with low static leakage currents, which can be operated as intended in the first and second operating modes. The remaining input buffers each have a differential amplifier circuit, which is switched off in the second operating mode. A reduced minimum current consumption of the semiconductor circuit is achieved by virtue of the inverter circuit, which switches reliably even in the case of low supply voltages.

Abstract: The present invention provides a tunable circuit for quickly optimizing an electrical field generated by the F-N tunneling operation. To optimize this electrical field, the charging of the positive charge pump is begun after the charging of the negative charge pump. The tunable circuit of the present invention provides a means to detect the optimal negative voltage at which pumping of the positive voltage should begin. The tunable circuit includes a resistor chain coupled between a first reference voltage and a negative voltage from a negative charge pump. When charging of the negative charge pump begins, a comparator compares the voltage at a node within the resistor chain to a second reference voltage. In accordance with the present invention, the node voltage within the resistor chain is equal to the second reference voltage when the negative voltage is equal to the voltage to be detected.

Abstract: A comparator comparing a differential input signal (represented by INM and INP single ended signals) with a differential reference signal (REFP and REFM) to generate a comparison result. The result may be amplified by a desired high amplification factor while consuming minimal electrical power. The comparator may contain two regenerative latches, with each latch containing two terminals. The INM, INP, REFP, and REFM are provided on the four terminals via respective switches. The first and second terminals of the first regenerative latch may respectively be connected to the first and second terminals of the second regenerative latch, with a switch in the path of each connection. The switches may be operated and the regenerative latches may be enabled for a short duration, to generate an amplified comparison result.

Abstract: A comparing circuit which suppresses an electric power consumption and promptly traces a DC offset when shifting to a receiving mode. The comparing circuit which needs to trace a DC offset potential is provided with means for enabling power down control functions of a reference voltage generating part and a voltage comparing part on the output side of the part to be independently controlled. In the receiving mode of an apparatus in which the comparing circuit is installed, the reference voltage generating part and voltage comparing part are made operative. In a transmitting mode of the apparatus, only the reference voltage generating part is made operative. In a pause mode of the apparatus, the reference voltage generating part and voltage comparing part are set in a power down state.

Abstract: An integrated circuit and method utilizes a differential input receiver having a first input that receives an input signal. A reference voltage adjustment circuit produces a variable reference signal for the second input of a differential input receiver. A feedback path is provided from the output of the differential input receiver to an input of the reference voltage adjustment circuit. The reference voltage adjustment circuit dynamically varies the variable reference voltage signal to facilitate hysteresis. The variable reference voltage signal is lowered in the case of a high input signal, and raised in the case of a low input signal.

Abstract: A comparing circuit which suppresses an electric power consumption and promptly traces a DC offset when shifting to a receiving mode. The comparing circuit which needs to trace a DC offset potential is provided with means for enabling power down control functions of a reference voltage generating part and a voltage comparing part on the output side of the part to be independently controlled. In the receiving mode of an apparatus in which the comparing circuit is installed, the reference voltage generating part and voltage comparing part are made operative. In a transmitting mode of the apparatus, only the reference voltage generating part is made operative. In a pause mode of the apparatus, the reference voltage generating part and voltage comparing part are set in a power down state.

Abstract: A self-calibrating circuit of a high speed comparator, having a first negative phase logic switch, a second negative logic switch, a first positive phase logic switch, a second positive phase logic switch, a third negative phase logic switch, a fourth negative phase logic switch, a third positive phase logic switch, a fourth positive phase logic switch, a fifth positive phase logic switch, a first current source circuit, a second current source circuit and a control logic circuit. Using the first and the second current source circuits, a self-calibration can be performed while the high speed comparator is just turned on, so that the input offset voltage of the high speed comparator can be eliminated.

Abstract: A detector circuit for automatic test equipment samples and tests differential signals. The detector circuit includes a pair of impedances connected in series between first and second legs of a differential input signal. A signal is formed at the junction of the two impedances that equals the common mode voltage of the differential signal. The common mode signal is coupled to the input of a window comparator, which compares the common mode signal with predetermined thresholds. The window comparator generates an output indicative of whether the common mode signal is above, within, or below the predetermined thresholds. Using this approach, the detector circuit can detect errors in differential signals caused by mismatched amplitudes or by timing skew between the first and second input signals. According to one feature, the detector circuit also includes a differential mode detector that receives the first and second input signals.

Abstract: There is provided an input circuit with reduced electrical power consumption, which processes an input signal given thereto for removing the noise components contained therein and regulating the voltage level thereof as well, and then supplies an output signal therefrom to a subsequent semiconductor integrated circuit. The input circuit 101 is made up of the Schmitt buffer 111, a pull-down resistance 113, an N-transistor 115, a P-transistor 121, an N-transistor 122, a P-transistor 131, an N-transistor 132, an exclusive OR gate 141, and a bus driver 151. The Schmitt buffer 111 is a buffer which has two threshold levels i.e. upper and lower thresholds, and changes the level of the output signal OUT depending on whether the voltage of an input signal IN is higher or lower than these two threshold levels.

Abstract: A voltage level converter for converting an input signal at a first voltage level to an output signal at a second voltage level, the converter comprises: an input for receiving said input signal; an output for outputting said output signal; a circuit node; precharge means for charging or discharging said circuit node to a third voltage level during a first time period by connection of said circuit node to a first voltage supply; isolation means for isolating said circuit node from said first voltage supply during a second time period; input means for changing the voltage at said circuit node in dependence on the voltage at said input during a third time period; and output means arranged so that the voltage at said output depends on the voltage at said circuit node.

Abstract: A comparator with hysteresis having a simplified architecture such that the amount of hysteresis can be readily adjusted. In one aspect, a comparator with hysteresis comprises a first switch for coupling an analog input voltage to a signal node in response to a first clock signal; an inverter having an input port and an output port; a capacitor operatively coupled between the signal node and an input port of the inverter; a second switch operatively connected between the input port and the output port of the inverter, the second switch being responsive to the first clock signal; a latch having a clock port, an output signal port, an inverse output signal port, and an input data port, the input data port being coupled to the output port of the inverter; and a reference voltage control circuit for selectively outputting a first internal reference voltage and a second internal reference voltage to the signal node in response to the output signal and inverse output signal, respectively, received from the latch.

Abstract: A magnetic sensing device comprising a magnetic sensor and a digital circuit is disclosed. The magnetic sensor is operable to output an analog signal as an indication of any movement of an object. The digital circuit can include a dynamic reference threshold generator to output a reference signal in response to a detection of a signal feature of the analog signal and to a detection of a diametric signal feature of the analog signal, and an output format generator to output a digital signal in response to a comparison of the analog signal and the reference signal. The digital circuit can include a dynamic reference threshold generator to output a reference signal in response to a detection a first pair of quadrants of the analog signal and a detection of a second pair of quadrants of the analog signal, and an output format generator to output a digital signal in response to a comparison of the analog signal and the reference signal.

Abstract: A system and method for converting an analog control voltage to a PTAT current. A plurality of differential transistor pairs is provided, each differential pair including a reference transistor and a non-reference transistor, each transistor having a current path and a control electrode. A first output is coupled to a first end of the current path of each of said non-reference transistors and output means is coupled to a first end of the current path of each of the reference transistors. A plurality of current sources is provided, one current source for each differential pair, each current source having a current path coupled to an opposing end of the current path of a different one of the transistor pairs and a control electrode. A PTAT current generator is coupled to the control electrode of each of the current sources. Each differential pair is provided with a pair of electron emitting electrodes coupled together, the current source being coupled to the electron emitting electrodes.

Abstract: A variable threshold comparator receiving, on an input node, an input signal having a voltage, and providing an output signal on an output node when the voltage of the input signal exceeds a selectable threshold voltage of the comparator. The comparator includes a transistor coupled by way of its source and drain between a power supply and an output node, and having its gate coupled to the input node. Also included are a plurality of pairs of transistors coupled together by a source of a first one of the pair of transistors and drain a drain of a second one of the pair of transistors, and coupled in series between the output node and a ground, a gate of the first one of the transistors coupled to the input node, and a gate of the second one of the transistors coupled to a control signal specific to the second one of the transistors. The threshold voltage of the comparator is selectable by the application of one or more of the control signals to a respective one or more of the second ones of said transistors.

Abstract: An integrated circuit and method utilizes a differential input receiver having a first input that receives an input signal. A reference voltage adjustment circuit produces a variable reference signal for the second input of a differential input receiver. A feedback path is provided from the output of the differential input receiver to an input of the reference voltage adjustment circuit. The reference voltage adjustment circuit dynamically varies the variable reference voltage signal to facilitate hysteresis. The variable reference voltage signal is lowered in the case of a high input signal, and raised in the case of a low input signal.

Abstract: A level adjusting circuit for controlling a voltage supplied to a load such as a semiconductor device, which comprises a voltage level detecting circuit, a reference potential generating circuit for generating a pair of reference potential values to be output into the voltage level detecting circuit, and a monitor pad for drawing out the voltage supplied to the load, wherein the reference potential values are respectively used to compare with the voltage to thereby output a signal for starting supply of the voltage and a signal for ceasing the supply of the voltage under a usually used condition; and the voltage level detecting circuit is to compare either one of the reference potential values with the voltage or the other reference potential value with the voltage at a time under a testing condition, whereby the reference potential generating circuit can accurately be adjusted to change the reference potential values to render the voltage in a range permissible for operation of the load.

Abstract: A circuit for producing a reset signal includes a voltage divider at which a first voltage proportional to a supply voltage can be tapped off. A resistor and a Zener diode disposed in the reverse direction are connected between the supply voltage and ground in a series circuit at which a second voltage can be tapped off. A difference signal between the first and second voltages is supplied to a first bistable multivibrator. An output signal from the first multivibrator is supplied to a low-pass filter configuration. A difference signal between an output signal from the low-pass filter configuration and the second voltage is supplied to a second bistable multivibrator. The multivibrators each exhibit hysteresis. A reset signal can be tapped off at the second multivibrator.

Abstract: A receiver of signals on cross chip boundaries for coupling chips with different coupling requirements allows changing hysteresis settings with changeable inputs to the receiver for connections between chips of different technologies without the need for masking or making a new circuit. The chip hysteresis profile switches from one setting to another based on the input from control logic supplied by a driver output level (DOL) pin input. Thus the receiver for signals on cross chip boundaries on directly connected and for interposer connection situations where chips need to be interconnected allows customization of the hysteresis across the connection. The receiver for chip to chip transitions receives a control input from a device output level control signal. When DOL is in high state it sets for the intermediate hysteresis levels and when it is in the low state it sets for a normal hysteresis level. A receiver enable pin turns the receiver power OFF and sets the output pin at a known deterministic state.

Abstract: A comparator circuit for differential output signals which is not affected by a common mode noise on the differential signals. The comparator circuit is advantageously used for testing differential output signals from a device under test (DUT). The comparator circuit includes an offset circuit for receiving differential signals from the DUT and generating a pair of balanced output signals which is provided with a predetermined offset voltage therebetween, and a comparator for receiving the pair of output signals from the offset circuit and comparing voltages between the output signals.

Abstract: A differential input buffer (14) and method of construction are provided. The differential input buffer (14) includes a differential amplifier (54, 56, 50, 52, 62, 64) connected to receive an input signal (IN). A local reference voltage generator (68, 70, 72) is connected to the differential amplifier (54, 56, 50, 52, 62, 64) and is connected to receive an external voltage reference (BLR) and to provide a local reference voltage (VREF) to the differential amplifier (54, 56, 50, 52, 62, 64). The local reference generator (68, 70, 72) is adjustable during construction to produce a desired level for the local reference voltage (VREF). The differential input buffer (14) also includes a hysteresis element (66, 74) that is connected to provide feedback to the differential amplifier (54, 56, 50, 52, 62, 64) and includes a buffer stage (76, 78, 80, 82, 84, 86) that is connected to receive an output of the differential amplifier (54, 56, 50, 52, 62, 64) and to drive an output signal (OUT).

Abstract: A comparator circuit (100) produces a binary output voltage at an output (109) in response to a time varying input signal received at an input (108). The comparator circuit includes an output circuit (106) having a first current mirror (202), a second current mirror (204), a bias circuit (206) and a helping current source (208). Bias currents are applied in response to the state of the output voltage at the output to increase the gain and the hysteresis of the output circuit.

Abstract: In a simultaneous bidirectional transmission circuit for conducting simultaneous two-way communication between LSIs via a transmission line, an input/output circuit connected to the transmission line is included in an LSI. The input/output circuit has a driver and a receiver. The driver sends out an output signal depending on a logical signal within the LSI to the transmission line. The receiver receives a mixed signal having a mixture of a received signal and the output signal via the transmission line. The signal to be received by the receiver in an LSI has been sent out to the transmission line by the other party i.e., another LSI in communication therewith. The receiver receives the logical signal output as well. The receives derives a difference between the mixed signal and the logical signal output, thereby removing the component of the logical signal from the mixed signal, and outputs the received signal.

Abstract: To decode an attenuated multi-level signal (42) in a receive interface (120) of communication apparatus, first (134) and second (150) diode pumps co-operate with a biasing chain to ensure that threshold reference levels used by respective positive (52) and negative (54) data comparators are dynamically adjusted to a level dependent upon the attenuated multi-level signal (42) applied to the diode pumps. Particularly, a voltage divider (138-144) acts dynamically to bias differential inputs to the respective positive (52) and negative (54) data comparators, with a ratio between a biasing chain of resistors (138-144) and a common input resistor 128 determining the threshold reference levels used to assign logical levels for the reconstruction of symbols encoded within the multi-level signal (42).

Abstract: The present invention relates to a process control monitoring system and method. The system and method uses current comparator circuits for monitoring process changes. Process sensitive current sources are compared with weighted reference current sources in a manner that each output of the current comparators demonstrates the inequality of the current sources. By setting the weighted reference current sources properly, the outputs of the current comparators may be used to locate the process corner of the fabricated integrated circuit.

Abstract: For use in a processor supervisory circuit, a power-on reset circuit, a method of producing a power-on reset ("RESET") signal and a power supply including the circuit. The circuit includes: (1) an adaptive, nonlinear voltage divider having a voltage input and a voltage output, the divider dividing an unscaled, unregulated voltage received at the voltage input by a factor that varies a function of the unscaled, unregulated voltage to produce a scaled, unregulated voltage at the voltage output and (2) a comparison circuit for comparing the scaled, unregulated voltage with a scaled, regulated voltage to produce the RESET signal when the scaled, regulated voltage exceeds the scaled, unregulated voltage, the divider being adaptive and nonlinear to ensure that the comparison circuit continuously produces the RESET signal when the scaled, regulated voltage exceeds the scaled, unregulated voltage and thereby avoid premature activation of a processor couplable to the power-on reset circuit.

Abstract: A threshold detecting device including a detecting stage having a first input supplied with a monitored voltage varying between a first and second value, a second input supplied with a reference voltage by a reference source stage, and an output supplying a logic signal indicating crossover of a predetermined threshold by the monitored voltage. Initially, the reference source stage is off and the reference voltage follows the course of the monitored voltage; upon the monitored voltage exceeding a first threshold value, the reference source is turned on and causes the reference voltage to rise more slowly than the monitored voltage, so that an increasing voltage difference is present between the first and second inputs of the reference stage; and, upon the voltage difference exceeding a second threshold value, the detecting stage switches and generates the threshold crossover signal.

Abstract: An improved burn-in sensing circuit for a semiconductor device generates a signal for indicating a start of a burn-in mode when an external voltage exceeds a predetermined level of a logic threshold voltage. The circuit obtains a desired hysteresis characteristic between a burn-in entry voltage and a burn-in exit voltage by lowering a level of the logic threshold voltage, and includes an external voltage sensor for dropping and outputting an external voltage in accordance with a bias voltage applied thereto. A burn-in signal generator of the circuit generates a predetermined level of a burn-in signal, and feeds back the predetermined level of a burn-in signal to lower the logic threshold voltage when a predetermined level of dropped voltage is higher than its logic threshold voltage.

Abstract: A circuit for power arbitration, low battery voltage detection, and the operation of battery backed circuitry for systems in which the system power supply voltage range overlaps that of a battery source. A voltage regulator is used to regulate the battery voltage so that the voltage range of the battery source is below the voltage range of the system supply. The regulator is based on a silicon-bandgap referenced methodology and consumes an insignificant amount of current so that the battery life is not appreciably affected. The regulator also has a smaller variation in its output voltage than the battery. A temperature and supply voltage compensated voltage is produced by the combination of a subthreshold current source, parasitic bipolar devices, and voltage buffering, and used to provide a voltage source for the battery backed circuitry of the system. The regulated voltage is set to a value lower than the system supply and serves as the battery supply input for the power arbitration circuitry.

Abstract: A noise cancellation system which balances the photocurrents derived by a measurement signal and a reference signal of a sensor. The invention has application in any measurement device which detects a small signal in combination with high noise content and further utilizes a reference signal.

Abstract: In controlling a discrimination level V.sub.1, V.sub.1 is controlled so that discrimination results based on discrimination levels V.sub.1 +.DELTA.V and V.sub.1 -.DELTA.V each become equal to the discrimination result based on the discrimination level V.sub.1. If the discrimination result based on V.sub.1 +.DELTA.V does not agree with the discrimination result based on V.sub.1, V.sub.1 is lowered, and if the discrimination result based on V.sub.1 -.DELTA.V does not agree with the discrimination result based on V.sub.1, V.sub.1 is raised. In controlling a discrimination phase .PHI..sub.1, .PHI..sub.1 is controlled so that discrimination results based on discrimination phases .PHI..sub.1 +.DELTA..PHI. and .PHI..sub.1 -.DELTA..PHI. each become equal to the discrimination result based on the discrimination phase .PHI..sub.1. If the discrimination result based on .PHI..sub.1 +.DELTA..PHI. does not agree with the discrimination result based on .PHI..sub.1, .PHI..sub.

Abstract: A circuit for providing programmable hysteresis levels is disclosed. The circuit includes comparators for producing output signals when an input signal crosses respective set points and a hysteresis circuit for establishing a hysteresis in the output signals. When a comparator's output signal is "on", the input signal is shifted by a hysteresis differential. The output signal is terminated when the shifted input signal returns to the set point. The hysteresis circuit includes a programmable hysteresis input for adjusting the hysteresis differential to different preset and intermediate hysteresis levels.

Abstract: An asynchronous self-adjusting circuit includes an input circuit receiving an input signal and providing an output signal. The input circuit starts to switch the output signal to a first logic level based on the level of the input signal reaching a falling edge adjustable trip point, and starts to switch the output signal to a second logic level based on the level of the input signal reaching a rising edge adjustable trip point. A control circuit dynamically and asynchronously adjusts the falling and rising edge adjustable trip points as a function of a previous value of the input signal to permit the asynchronous self-adjusting circuit to respond quickly to changes in the input signal without causing oscillation of the output signal by asynchronously controlling when the output signal is permitted to again switch logic states once the output signal switches logic states.