Abstract: A method for providing programmable hysteresis levels includes producing output signals when an input signal crosses respective set points and establishing a hysteresis in the output signals. When a comparator's output signal is "on", the input signal is shifted by a hysteresis differential. The output signal is terminated when the shifted input signal returns to the set point. A programmable hysteresis input is adjusted to set the hysteresis differential to different preset and intermediate hysteresis levels.

Abstract: A comparator with hysteresis which has a bias current circuit, a differential input stage, and an output stage is disclosed. The differential input stage uses an analog switch to connect the body of a field effect transistors to either a first voltage or a second voltage. The analog switch in the preferred embodiment is a double-throw switch.

Abstract: A semiconductor integrated circuit includes memory cell blocks having memory cells arranged in matrix, sense amplifiers, each located adjacent to the memory cells, and sense amplifier control circuits, each of the sense amplifier control circuit being located on outside of the memory cell block. The sense amplifier control circuit has a standard voltage generating circuit and a control circuit for receiving the standard voltage and for transferring a driver signal to the sense amplifier to control the charging ability of the sense amplifier. The source voltage has three voltage regions, first, intermediate, and second regions. In the first voltage region, the potential of the driver signal increases with the increase of the source voltage. In the intermediate voltage region (2.7 to 3 Volt), the potential of the driver signal is changed oppose to the change of the source voltage, and in the second voltage region, the potential of the driver signal decreases with the increase of the source voltage.

Abstract: A circuit connects a circuit node to a voltage source selected between two alternative power supply voltage sources. The circuit includes two transistors, specifically a first transistor selectively connecting the circuit node to a first power supply voltage source of the two alternative power supply voltage sources and a second transistor selectively connecting the circuit node to the second power supply voltage source. The first transistor has a gate connected to the second power supply voltage source. The second transistor has a gate connected to the first power supply voltage source. The circuit passes the lowest voltage supplied by the two alternative voltage sources to the circuit node. The circuit is useful, for example, in a voltage translation and overvoltage protection circuit.

Abstract: A comparator (10) has voltage input terminals (20, 22) connected to control current flow through paths (33, 34) of first and second matched pair transistors (16, 18), and output terminals (41, 42) of an offset current control subcircuit (43) connected to control current flow through parallel paths (44, 45) of third and fourth matched pair transistors (38, 39). Subcircuit (43) includes a first voltage follower (47) connected to cause the common mode of an offset voltage differential applied at terminals (41, 42) to track the input common mode voltage applied at terminals (20, 22), and a second voltage follower (48) connected to define the value of the offset voltage differential according to a voltage applied at a reference voltage node (62).

Abstract: A comparator (10) has voltage input terminals (20, 22) connected to control current flow through paths (33, 34) of first and second matched pair transistors (16, 18), and output terminals (41, 42) of an offset current control subcircuit (43) connected to control current flow through parallel paths (44, 45) of third and fourth matched pair transistors (38, 39). Subcircuit (43) includes a first voltage follower (47) connected to cause the common mode of an offset voltage differential applied at terminals (41, 42) to track the input common mode voltage applied at terminals (20, 22), and a second voltage follower (48) connected to define the value of the offset voltage differential according to a voltage applied at a reference voltage node (62).

Abstract: An improved comparator circuit is provided for comparing two input signals and producing a resulting digital output. The comparator circuit uses a single cascode devices and current mirror circuit parallel coupled to two differential amplifier stages. One differential amplifier stage receives differential input signals and the other differential amplifier stage receives a variable reference voltage and a feedback voltage from the output of the comparator. The reference voltage is varied according to user requirements. The reference voltage can be varied to any voltage within the range of the input signals placed on the differential amplifier stage. Hysteresis differential voltage on the input differential amplifier stage can be accurately controlled by varying the biasing current and reference voltage placed on the hysteresis differential amplifier stage.

Abstract: A rate of change comparator uses an RC charging circuit and a separate RC discharging circuit to follow a transducer output. The resistor component of each RC circuit is shunted by a diode, each biased in a different orientation so that the charging circuit charges quickly through its diode but discharges slowly through its resistor and the discharging circuit discharges quickly through its diode and slowly through its resistor. The difference in output between the charging and discharging circuits is detected with a comparator, biased off by a threshold bias voltage developed from one of the circuits. The comparator is unaffected by slow changes in transducer signals due to drift, ambient condition and similar changes because the differential voltage between the circuits is minimized for transducer signal changes below the level set by a threshold bias level.

Abstract: A peak detector for use in a fiber optic receiver has a capacitor, an input amplifier driving the capacitor, and a feedback differential amplifier coupled between the capacitor and an input of the input amplifier. The input amplifier is a complementary buffer with unity gain modified to include an additional transistor on one rail that receives an inverter voltage generated by the differential amplifier. The inverter voltage equals the difference between twice the capacitor voltage and an input voltage applied to the peak detector. The input amplifier in a positive peak detector functions so that the capacitor voltage tracks the input voltage when it exceeds the inverter voltage, and equals the average of the input voltage and inverter voltage when the input voltage is less than the inverter voltage. A negative peak detector operates similarly but with opposite polarity. The peak detector also contains transistors used to reset the capacitor voltage upon assertion of a reset signal.