Abstract: A system and method for providing an accurate current reference using a low-power current source is disclosed. A preferred embodiment comprises a system comprises a first section and a second section. The first section comprises a first simple current reference, an accurate current reference, and a circuit that generates a digital error signal based upon a comparison of an output of the first simple current reference and an output of the accurate current reference. The second section comprises a second simple current reference providing a second reference current, an adjustment circuit providing an adjustment current based upon the digital error signal, and a circuit biased with current equivalent to a summation of the second reference current and the adjustment current. The first simple current reference and the second simple current reference may be equivalent circuits.

Abstract: A low voltage detector (100) includes a voltage and current reference circuit (102); a power supply voltage monitor circuit (104), coupled to the voltage and current reference circuit and to a power supply; and a voltage comparator (106), coupled to the voltage and current reference circuit and to the power supply voltage monitor circuit. The voltage and current reference circuit includes a self-cascode MOSFET structure (SCM) (110) that produces a reference voltage. The power supply voltage monitoring circuit includes another SCM (140) that produces a monitor voltage, related to the power supply voltage. The reference voltage and the monitor voltage have a same behavior with changes in temperature, thereby allowing the trip point of the low voltage detector to minimally vary with temperature. The low voltage detector is disposed on an integrated circuit (101), and the transistors of the low voltage detector consist of only CMOS transistors.

Abstract: According to one embodiment, a peak detector having extended dynamic range comprises a first differential output coupled to a supply voltage of the peak detector by a first load and coupled to ground by first and second switching devices, and a second differential output coupled to the supply voltage by a second load and coupled to ground by third and fourth switching devices. The control terminals of the first, second, third, and fourth switching devices receive a common bias voltage, and the respective first and second control terminals are configured as differential inputs of the peak detector. In some embodiments, corresponding first power terminals of the first and second switching devices share a first common node further shared by the first differential output, and corresponding first power terminals of the third and fourth switching devices share a second common node further shared by the second differential output.

Abstract: A half-power buffer amplifier is disclosed. A buffer stage includes a first-half buffer stage and a second-half buffer stage, wherein an output of the first-half buffer stage is controllably fed back to a rail-to-rail differential amplifier, and an output of the second-half buffer stage is controllably fed back to the rail-to-rail differential amplifier. The switch network controls the connection between the outputs of the buffer stage and an output node of the half-power buffer amplifier in a manner such that a same pixel, with respect to different frames, of a display panel is driven by the same rail-to-rail differential amplifier. In one embodiment, the rail-to-rail differential amplifier and the buffer stage comprise half-power transistors operated within and powered by half of a full range spanning from power to ground.

Abstract: A method for deskewing a differential signal is provided. A common-mode voltage of a differential signal and an average for the common-mode voltage of the differential signal are measured. A difference between first and second portions of the differential signal is determined, and deskew information is derived from the common-mode voltage and the average. The deskew information can then be combined with the difference to deskew the differential signal.

Abstract: A method for deskewing a differential signal is provided. A common-mode voltage of a differential signal and an average for the common-mode voltage of the differential signal are measured. A difference between first and second portions of the differential signal is determined, and deskew information is derived from the common-mode voltage and the average. The deskew information can then be combined with the difference to deskew the differential signal.

Abstract: A binarization circuit includes a comparator that outputs a signal according to a differential voltage between the input and reference voltages. The first charging-discharging circuit generates a first voltage. The second charging-discharging circuit generates a second voltage. The control circuit compares the differential voltage with the threshold voltage, and switches between turn-on and turn-off of the second charging-discharging circuit based on a difference between the differential voltage and the threshold voltage. A sum of the reference and first voltages of the preceding clock is supplied to the comparator when the second charging-discharging circuit is turned off. A sum of the reference and the first and second voltages of the preceding clock is supplied to the comparator when the second charging-discharging circuit is turned on.

Abstract: Systems and methods for current sensing are described. The described systems and methods utilize a comparator for generating a current sense signal based on comparing an output current of a circuit against a reference current. The reference current is generated by using a current sourcing circuit that is connected to a controllable current source.

Abstract: An analog-to-digital (ADC) calibration apparatus comprises a calibration buffer, a comparator and a digital calibration block. Each reference voltage is sent to a track-and-hold amplifier as well as the calibration buffer. The comparator compares the output from the track-and-hold amplifier and the output from the calibration buffer and generates a binary number. Based upon a successive approximation method, the digital calibration block finds a correction voltage for ADC offset and nonlinearity compensation. By employing the ADC calibration apparatus, each reference voltage can be calibrated and the corresponding correction voltage can be used to modify the reference voltage during an ADC process.

Abstract: A circuit includes a comparator, a resistor divider, a control circuit, a multiplexer, and a programmable gain amplifier. The comparator is operable to measure an internal voltage of the circuit based on a selected reference voltage. The resistor divider is operable to generate reference voltages. The control circuit is operable to generate a select signal based on an output signal of the comparator. The multiplexer is operable to select one of the reference voltages from the resistor divider as the selected reference voltage based on the select signal. The programmable gain amplifier is configurable to generate a compensation voltage to compensate for an offset voltage of the comparator. The compensation voltage is provided to an input of the comparator.

Abstract: According to one embodiment, a hysteresis comparator is provided with to first to third current sources, a comparison amplifying unit, a reference voltage generating unit, a current mirror circuit, first to fifth N-channel MOS transistors, and first to fifth terminals.

Abstract: According to one embodiment, a binarization circuit includes a comparator, first and second charging-discharging circuits, and a control circuit. The comparator compares an input voltage with a reference voltage and outputs a signal in accordance with a differential voltage between the input voltage and the reference voltage. The first charging-discharging circuit generates a first voltage by multiplying the differential voltage by a first charge-discharge factor. The second charging-discharging circuit generates a second voltage by multiplying a difference between the differential voltage and a threshold voltage by a second charge-discharge factor greater than the first charge-discharge factor. The control circuit compares the differential voltage with the threshold voltage, and switches between turn-on and turn-off of the second charging-discharging circuit based on a difference between the differential voltage and the threshold voltage.

Abstract: A receiving circuit includes a comparing circuit, a first storage circuit, a second storage circuit, and a voltage controlling circuit. The comparing circuit compares an input signal with a reference voltage and outputs a signal with either a first level when the input signal is larger than the reference voltage or a second level when the input signal is smaller than the reference voltage as a comparison result. The first storage circuit stores an output level of the comparing circuit for a next one cycle. The second storage circuit stores an output level of the first storage circuit for a next one cycle. The voltage controlling circuit controls a level of the reference voltage in each cycle on the basis of output levels of the first storage circuit and the second storage circuit.

Abstract: A low voltage detector (100) includes a voltage and current reference circuit (102); a power supply voltage monitor circuit (104), coupled to the voltage and current reference circuit and to a power supply; and a voltage comparator (106), coupled to the voltage and current reference circuit and to the power supply voltage monitor circuit. The voltage and current reference circuit includes a self-cascode MOSFET structure (SCM) (110) that produces a reference voltage. The power supply voltage monitoring circuit includes another SCM (140) that produces a monitor voltage, related to the power supply voltage. The reference voltage and the monitor voltage have a same behavior with changes in temperature, thereby allowing the trip point of the low voltage detector to minimally vary with temperature. The low voltage detector is disposed on an integrated circuit (101), and the transistors of the low voltage detector consist of only CMOS transistors.

Abstract: In a signal monitoring system, a circuit includes an input terminal and an output terminal. In addition, a processor coupled to the circuit is operable for calculating a parameter indicative of an error factor of the circuit by setting a level difference between an input signal at the input terminal and an output signal at the output terminal to a predetermined level.

Abstract: A semiconductor integrated circuit includes first to N-th comparators to compare an input voltage with a threshold value; and a control circuit to perform first and second operations, set a threshold value of the first comparator as a first threshold value, and set a threshold value of an M-th comparator as a second threshold value, wherein the first operation includes an operation where a value obtained by multiplying a value obtained by subtracting the threshold value of the M-th comparator from a threshold value of an (M+1)th comparator by a real number is added to the threshold value of the M-th comparator, and wherein the second operation includes an operation where a value obtained by multiplying a value obtained by subtracting the threshold value of the M-th comparator from a threshold value of an (M?1)th comparator by a real number is added to the threshold value of the M-th comparator.

Abstract: An oscillator that increases the accuracy of an output frequency, without using a charge pump, has an oscillation circuit, first and second voltage supply circuits, and a calibration value generation circuit. The first voltage supply circuit includes a resistor and a capacitor, the resistance and capacitance of which are determined so that a first voltage reaches a reference voltage within a reference time. The second voltage supply circuit includes first and second switching means, which perform switching when receiving pulse signals corresponding to the frequency of the oscillation circuit to raise the second voltage. A calibration value generation circuit provides the oscillation circuit with a calibration value that lowers the frequency when the second voltage reaches the reference voltage before the first voltage and raises the frequency when the second voltage reaches the reference voltage after the first voltage.

Abstract: A multiple supply voltage device includes an input/output (I/O) network operative at a first supply voltage, a core network coupled to the I/O network and operative at a second supply voltage, and a power-on-control (POC) network coupled to the I/O network and the core network. The POC network is configured to transmit a POC signal to the I/O network and includes an adjustable current power up/down detector configured to detect a power state of the core network. The POC network also includes processing circuitry coupled to the adjustable current power up/down detector and configured to process the power state into the POC signal, and one or more feedback circuits. For reducing the leakage current while also improving the power-up/down detection speed, the feedback circuit(s) are coupled to the adjustable current power up/down detector and configured to provide feedback signals to adjust a current capacity of the adjustable current power up/down detector.

Abstract: Methods and systems to generate a digital error indication of an input signal relative to a reference signal, using resistors, comparators, and latches. The digital error indication may indicate that the input signal is within a range of the reference signal, above the range, or below the range. The methods and systems may be implemented within a multi-phase digital voltage regulator to generate a digital error indication for each of a plurality of phase currents relative to an instantaneous average of the phase currents. The digital voltage regulator may be fabricated on an integrated circuit die with a corresponding load, such as a processor. The digital voltage regulator may include a plurality of multiplier or look-up based gain modules, each to receive a corresponding one of the digital error signals and to output one of three values. Outputs of each gain module may be integrated over time.

Abstract: A half-power buffer amplifier includes a buffer stage having a first-half buffer stage and a second-half buffer stage. An output of the first-half buffer stage is controllably fed back to a rail-to-rail differential amplifier, and an output of the second-half buffer stage is controllably fed back to the rail-to-rail differential amplifier. A switch network controls the connection between the outputs of the buffer stage and an output node of the half-power buffer amplifier in a manner such that a same pixel, with respect to different frames, of a display panel is driven by the same rail-to-rail differential amplifier.

Abstract: A comparator circuit according to an embodiment of the present invention includes a comparator configured to compare an input signal voltage with a reference voltage obtained by smoothing the input signal by use of a resistor and a capacitor, and output a result of the comparison, a discharge circuit configured to compare a first addition signal which is obtained by adding a positive first voltage to the input signal voltage, with the reference voltage, and discharge the capacitor when the first addition signal is lower than the reference voltage, and a charge circuit configured to compare a second addition signal which is obtained by adding a negative second voltage to the input signal voltage, with the reference voltage, and charge the capacitor when the second addition signal is higher than the reference voltage.

Abstract: In a signal monitoring system, a circuit includes an input terminal and an output terminal. In addition, a processor coupled to the circuit is operable for calculating a parameter indicative of an error factor of the circuit by setting a level difference between an input signal at the input terminal and an output signal at the output terminal to a predetermined level.

Abstract: In a signal monitoring system, a circuit includes an input terminal and an output terminal. In addition, a processor coupled to the circuit is operable for calculating a parameter indicative of an error factor of the circuit by setting a level difference between an input signal at the input terminal and an output signal at the output terminal to a predetermined level.

Abstract: An interpolation circuit for comparing an input voltage signal with an interpolated reference signal derived from a first reference voltage signal and a second reference voltage signal may include a transconductive circuit configured to generate a first differential current signal proportional to a difference between the first reference voltage signal and the input voltage signal and a second differential current signal proportional to a difference between the second reference voltage signal and the input voltage signal, an intermediate circuit configured to generate a third differential current signal, and a transinductive circuit configured to generate an output voltage signal having a first polarity if a value of the input voltage signal is greater than a value of the interpolated reference signal and a second polarity if the value of the input signal is less than the value of the interpolated reference signal.

Abstract: The invention relates to a monitoring system, having an output module for generating a control signal in response to an input signal, a monitoring module for generating the input signal for the output module, an output device for outputting an output signal in response to the control signal, and a feedthrough device for preventing outputting of the output signal. According to the invention, the monitoring module is designed to instruct the feedthrough device to prevent outputting of the output signal when there is a deviation between the control signal and a control signal which is expected on the basis of the input signal.

Abstract: The nonlinearity effect of a rectifying element is enhanced, and further a resonant circuit is used to enlarge the input amplitude. Furthermore, the rectifying efficiency of a detection rectifier circuit is enhanced, thereby allowing the gain of an amplifier circuit in the following stage to be set to a low value. Signals having mutually opposite phases are inputted to RF input terminals (101,102). The signal at the terminal (102) is then inputted to the gate of a transistor (M1) via a capacitor (C3), while the signal at the terminal (101) is then inputted, via a capacitor (C1), to a node (N1) to which the source of the transistor (M1) and the gate and drain of a transistor (M2) are connected, whereby a capacitor (C2) is charged with a half-wave voltage-doubled rectified current. DC biases are inputted to terminals (301,302). There are formed series resonant circuits (L1,C15;L2,C16). A plurality of half-wave voltage-doubled rectifier circuits (M1,M2,C1-C3,R1) are connected in cascade.

Abstract: A circuit can include a comparator, a resistor divider, a control circuit, and a multiplexer. The comparator compares an internal supply voltage of the circuit to a selected reference voltage. The resistor divider generates reference voltages. The control circuit receives an output signal of the comparator and generates a select signal. The multiplexer transmits one of the reference voltages from the resistor divider to the comparator as the selected reference voltage in response to the select signal.

Abstract: A full-wave rectifier circuit receives complementary signals and produces a current corresponding to an added value of differential signals at different levels. A voltage comparator performs a comparison between output signals produced and subjected to current addition and voltage conversion by the full-wave rectifier circuit. A timer detects whether an output signal of the voltage comparator is kept in the same state for a predetermined time or more, and produces a signal indicating a result of the detection. A signal detecting circuit that can accurately identify a state of digital signals of a minute amplitude transferred through a pair of complementary signal lines is achieved without complicating manufacturing steps.

Abstract: A circuit for detecting an input voltage includes a voltage-to-current converter and a current comparator. The voltage-to-current converter is operable for generating a monitoring current that varies in accordance with the input voltage. The current comparator coupled to the voltage-to-current converter is operable for comparing the monitoring current to a threshold current proportional to the temperature of the circuit, and for generating a detection signal indicating a condition of the input voltage based on a result of the comparison.

Abstract: A temperature sensing circuit that does not use an oscillator is presented. The temperature sensing circuit includes a selector and a detector. The selector is configured to select and output a reference voltage from first and second level signals in response to first and second trimming signals. The first and second level signals are relatively insensitive to temperature variations. The detector is configured to generate a detection voltage by comparing the reference voltage with a variable voltage depending on internal temperature.

Abstract: A semiconductor device includes a reference voltage generating unit configured to produce a reference voltage by dividing a voltage difference between a positive clock terminal and a negative clock terminal, and a logic determination unit configured to determine a logic level of an external signal based on the reference voltage.

Abstract: Disclosed herein is a voltage detection circuit including: a voltage detection section; a first voltage determination section; and a second voltage determination section.

Abstract: A comparator circuit for providing hysteresis comprises first and second differentially coupled transistors. The first of the differentially coupled transistors provides drain current to first and second load transistors. The second of the differentially coupled transistors provides drain current to third and fourth load transistors. In one example embodiment, the drain of the first of the differentially coupled transistors also drives the gate of the first and third load transistors, while the drain of the second of the differentially coupled transistors drives the gate of the second and fourth transistors.

Abstract: Disclosed is a signal output circuit comprising: a first transistor of an emitter follower configuration, which receives an input signal; a second transistor of an emitter follower configuration, which receives the input signal, and has an output connected to an external load (106); a comparator circuit which has an input pair connected via resistors to emitters of the first and the second transistors; a first current mirror circuit which has an input connected to an output of a first current source transistor and an output connected to an emitter of the first transistor; and a second current mirror circuit which has an input connected to a connection node of an output of a second current source transistor and an output of the comparator circuit, and has an output connected to an emitter of the second transistor.

Abstract: A test and measurement instrument including a plurality of channels, each channel configured to receive a corresponding input signal. Each channel includes a comparator configured to compare the input signal to a threshold for the channel; an edge detector configured to detect an edge of an output signal of the comparator; and a threshold controller configured to adjust the threshold for the channel in response to the edge detector.

Abstract: More accurate signal detection circuitry in serial interfaces, particularly on a programmable integrated circuit device, such as a PLD, includes a high-speed, high-resolution, high-bandwidth comparator, along with digital filtering, to reduce the effect of process, temperature or supply variations. The comparator is used to compare a direct input signal with a programmable reference voltage, and, in a preferred embodiment, can detect the signal level within 8 mV accuracy. The output of the comparator may then be digitally filtered. Preferably, both a high-pass digital filter and a low-pass analog filter may be used to eliminate glitches and low-frequency noise. Preferably, the digital filters are programmable to adjust the sensitivity to noise. The filtered output is then latched and output to indicate receipt or loss of signal. This signal detect circuitry can operate reliably at data rates as high as 7 Gbps.

Abstract: A digital bit-level repeater for joining two wired-AND buses such as the I2C bus is described. A protocol detector is used for tracking clock and data signals to determine the direction of the transfer. A state machine reads and regenerates the clock lines of both buses and provides the clock-stretching protocol feature on both buses. The repeater is designed to pass data bits from one bus to the other transparently when possible, and to latch and hold each data bit until the receiving bus can be clocked when clock-stretching occurs or when the bus is turned around.

Abstract: A signal receiver includes a first-stage circuit, a second-stage circuit, a current compensation circuit, and a biasing circuit. A first input end of the first-stage circuit receives a reference voltage, and a second end of the first-stage circuit receives an input signal. A first input end and a second input end of the second-stage circuit are respectively coupled to a first output end and a second output end of the first-stage circuit. The current compensation circuit is coupled to the first input end of the second-stage circuit for dynamically providing a compensation current to the first input end of the second-stage circuit in response to a biasing voltage, so as to stabilize its voltage level. The biasing circuit biases the first-stage circuit and the current compensation circuit and sets the biasing voltage of the current compensation circuit in response to the reference voltage.

Abstract: A signal comparison circuit is provided. The signal comparison circuit includes a first amplifier, a second amplifier, a peak detector, and a comparator. The first amplifier is a zero-peaking amplifier. The first amplifier receives and amplifies a data signal. The second amplifier receives and amplifies a reference voltage. The peak detector is coupled to the first and the second amplifiers for detecting and maintaining maximum values of the amplified data signal and the amplified reference voltage, and then outputting the maintained data signal and the maintained reference voltage. The comparator is coupled to the peak detector for comparing the maintained data signal with the maintained reference voltage and outputting a result of the comparison.

Abstract: An input voltage detecting circuit includes an input circuit, a signal processing circuit and an output circuit. The input circuit is used for processing the intensity and the waveform of an input voltage, thereby generating a first signal, wherein the first signal and the input voltage have similar time sequences. The signal processing circuit is connected to the input circuit for reducing a first delaying time of the first signal, thereby generating a second signal having a second delaying time shorter than the first delaying time. The output circuit is connected to the signal processing circuit for processing the intensity and the waveform of the second signal, thereby generating the power status signal. If the input voltage is uninterrupted, the power status signal is in an uninterrupted status. If the input voltage is interrupted, the power status signal is in an interrupted status.

Abstract: A semiconductor device includes a reference voltage generating unit configured to produce a reference voltage by dividing a voltage difference between a positive clock terminal and a negative clock terminal, and a logic determination unit configured to determine a logic level of an external signal based on the reference voltage.

Abstract: A level shifter circuit which amplifies the amplitude of an input signal, includes a CMOS inverter which is composed of a p-type transistor and an n-type transistor, a first and a second capacitor one electrode of each of which is connected to the gate of the p-type transistor and that of the n-type transistor, respectively, a first switch which supplies the input signal to the other electrodes of the first and second capacitors, a second switch which applies a direct-current voltage whose amplitude is nearly half of the amplitude of the input signal to the other electrodes of the first and second capacitors, and a third and a fourth switch which apply a first and a second preset voltage to one electrode of each of the first and second capacitors, respectively.

Abstract: A charge detection device includes: a substrate having a first conductive type of predetermined region; a second conductive type of drain region disposed in the predetermined region of the substrate; a second conductive type of source region disposed in the predetermined region of the substrate; a second conductive type of channel region disposed between the drain region and the source region; a gate formed via an insulating film on the channel region; a second conductive type of charge accumulation region disposed in the predetermined region of the substrate and changing a threshold voltage of a transistor having the drain region, the source region, and the gate by accumulating signal charges as a target to be measured; a first conductive type of channel barrier region disposed between the channel region and the charge accumulation region; and a charge sweep region sweeping away the signal charges accumulated in the charge accumulation region.

Abstract: There is provided a current detection circuit capable of preventing an excessive voltage from being applied to an input terminal of a differential amplifier, without resulting in reduction in current detection accuracy. The current detection circuit includes a power MOSFET 1 (a first semiconductor switching device), a sense MOSFET 2 (a second semiconductor switching device), a differential amplifier 3, a Zener diode 33 (a first voltage clamp device), a Zener diode 34 (a second voltage clamp device), an MOSFET 6 (a variable resistance device), a depletion type MOSFET 31 (a first MOSFET), and a depletion type MOSFET 32 (a second MOSFET).

Abstract: The present invention discloses a current-matching method comprising steps of: providing a plurality of current channels; grouping the plurality of current channels into W sets, each of which has Q channels; and matching the channels of the same set in current, where both W and Q are integers greater than or equal to 2. The present invention also discloses a current-matching circuit including hierarchical tree structure having two or more levels, each of which includes multiple matching devices, wherein each matching device at a preceding level corresponds to a predetermined number of matching devices at a next level. Respective matching devices at a last level control currents in respective current channels; the channels of the same group are matched with one another in current.

Abstract: An adaptive current limiter is coupled to a power source and which comprises a variable reference voltage generator which provides a variable reference voltage which is inversely proportional to the input voltage from the power source, which in certain embodiments is representative of the maximum allowable current level that may flow through a connected load at the present voltage provided by the power source given a fixed power limit. The current flow to the load is interrupted when the power level provided to the load exceeds predefined constant power and/or constant current limits.

Abstract: Systems and methods for determining a slicing level which is used as a threshold to determine whether timeslots of an incoming data signal contain ones or zeros. The method of one embodiment comprises receiving a data signal, identifying a maximum level of the data signal, identifying a minimum level of the data signal, determining an average of the minimum and maximum levels, and then using the average of the minimum and maximum levels as a slicing level to identify bits of a data packet embodied in the data signal.

Abstract: A semiconductor device includes a reference voltage generating unit configured to produce a reference voltage by dividing a voltage difference between a positive clock terminal and a negative clock terminal, and a logic determination unit configured to determine a logic level of an external signal based on the reference voltage.

Abstract: A method for adapting threshold values in an electronic signal processing device, involving a plurality of different threshold values being calculated and being compared with processing variables calculated in the signal processing device, involves calculation of a common correction value which is valid for the various threshold values. The threshold values are then set on the basis of the common correction value.

Abstract: An input stage of an integrated circuit, includes a comparator for comparing the voltage of an input signal of the input stage with a reference voltage, and supplying a binary output signal the value of which depends on the result of the comparison of the input signal with the reference voltage. The input stage comprises a feedback circuit measuring a parameter representative of the operation of the comparator, and raising the reference voltage while the measured parameter reveals a faulty operation of the comparator.