Abstract: The magnitude of a pulse in a signal having both positive and negative polarity pulses (for example, a ternary PDH signal) is determined by measuring the magnitude of multiple samples of the signal. A reference level for the signal is determined from a plurality of these sample magnitudes, and the magnitude of a pulse in the signal is determined from the sample magnitudes and the reference level.

Abstract: An overvoltage circuit detects differences between the supply voltage from a first circuit and the operating voltage of a second circuit. The circuit may detect when the power supply value of the first circuit is below, above, or equal to the operating voltage of the second circuit. The overvoltage circuit consumes substantially zero static current and may be used in a variety of implementations.

Abstract: In a signal read circuit including a plurality of circuit rows each having a charge amplifier connected to a photoelectric conversion element PD and a CDS circuit 2S for performing correlated double sampling for an output from the charge amplifier, a dummy circuit row DMY having the same configuration as a circuit row SLT is connected in parallel with this circuit row SLT. By calculating the difference between these circuit rows connected in parallel, offset variations generated in the two circuit rows SLT and DMY can be removed.

Abstract: An input circuit includes a comparator circuit and a multi-reference circuit. The input circuit receives an input signal and generates an output signal as a function of the input signal and a reference signal received from the multi-reference circuit. The comparator circuit detects a crossing of the input signal relative to the reference signal and causes a corresponding transition of the output signal. In response to the transition of the output signal, the multi-reference circuit provides a different reference signal to the comparator circuit. The reference signals provided by the multi-reference circuit are selected to create hysteresis in the operation of the input circuit.

Abstract: A method for error detection and error correction in the monitoring of measurement values is disclosed, in which the value to be tested is checked for plausibility in an evaluation device, for example a computer, and in the event that an implausibility is identified, the existence of an error is determined. If a further check finds that the error no longer exists, then an error correction takes place. A prerequisite for the error correction, however, is that the range of the value to be monitored in which the error has occurred is also the range in which a current error is no longer occurring. In an expanded method, a differentiation is also made between different errors and an error correction is only possible if it involves the same type of error.

Abstract: The present invention is directed at providing methods in a circuit for smoothing transitions relating to a signal processing function. A reference signal is produced that relates to a DAC output code. The reference signal is used as a starting point, and is compared to the input signal. A feedback signal is produced that is used to adjust the reference. The invention can be used to implement signal processing functions such as peak detection, noise filtering, peak suppression, and the like, in which the transitions in the signal are smoothed. The invention can implement these functions with a minimal complexity and a minimal die area.

Abstract: An apparatus and method for detecting the presence of a valid signal includes an offset generator coupled to a pair of data slicers and an XOR gate. The offset generator is configured to both add and subtract a predetermined voltage to an input voltage in its two outputs. The two outputs of the offset generator are both compared to a predetermined value in a pair of data slicers. If the outputs of the data slicers are the same (i.e., either both offset signals are positive or both are negative), then a valid signal is indicated.

Abstract: The present invention has an object to control easily the pulse width of an output by operating a limiting circuit appropriately even if the power voltage is low. A limiting circuit is provided on the input side of a hysteresis comparator circuit to prevent saturation. A limit voltage Vlimit is set by a bias circuit so as to change in accordance with the operation of the hysteresis comparator circuit. When an input voltage Vsig exceeds a hysteresis threshold voltage Vth, the limit voltage Vlimit is dropped in response to a drop of the hysteresis threshold voltage Vth. Thus, the width of the pulse width can be controlled while maintaining the condition that the limit voltage Vlimit is higher than the hysteresis threshold voltage Vth.

Abstract: A burst mode receiving apparatus having an offset compensating function and a data recovery method thereof, including an intermediate value detector to detect and output an intermediate value of an input signal input from an outside source in response to a switching control signal; an amplifier to amplify and output a difference between the input signal and a reference value; an offset compensator to generate a compensation signal having a level varied corresponding to the amplified result input from the amplifier and a compensation control signal; a summing portion to add the compensation signal and the intermediate value to output the added result as the reference value to the amplifier; and a controller to generate the switching control signal and the compensation control signal corresponding to a result obtained by analyzing the amplified result input from the amplifier and a reset signal input from the outside source.

Abstract: An anlog boundary scan compliant integrated circuit system carries out a test more reliably and cuts down on power dissipated during normal operation. To perform a test of whether or not an interconnect is connected normally between integrated circuits, multiple logic circuits with mutually different input threshold voltages are provided to detect the logical level of a potential at a terminal, thereby improving the reliability of the test. Potential fixers and power isolators are optionally provided. During normal operation, the power fixers fix the output potentials of the logic circuits, while the power isolators electrically isolate the logic circuits from the ground. As a result, no current flows through the logic circuits or other circuits in succeeding stages while no tests are carried out.

Abstract: A level discrimination circuit includes two offset compensation circuits. Each offset compensation circuit receives a differential pair of input signals, detects their peak values, and adds the peak value of each input signal to the other input signal, thereby generating an offset-compensated differential pair of output signals. The output signals of the first offset compensation circuit are used directly as the input signals of the second offset compensation circuit. The output signals of the second offset compensation circuit therefore have the correct duty cycle, and can be correctly discriminated by a comparator, even if the input signals to the first offset compensation circuit are burst signals in which each burst includes a large direct-current bias. This level discrimination circuit is suitable for receiving optical signals transmitted in bursts.

Abstract: An output driver circuit that can be used to determine whether a repeater buffer is the only device driving a bus low. According to the invention, the current through the output driver circuit of the repeater buffer is compared with a reference current. If that current is greater than the reference current, then the output driver circuit (i.e., the repeater buffer) is the only output driving the bus low. On the other hand, if that current is less than the reference current, then the output driver circuit (and thus the repeater buffer) is not the only device driving the bus low. This information can be used in an I2C repeater to determine the proper response of the repeater and prevent a latch condition.

Abstract: A sense amplifier for a memory includes a comparator and a bit line polarization circuit. The comparator receives a first signal representative of a current flowing through a memory cell and a second signal representative of a reference current. Additionally, the comparator includes a stage in a common source configuration and an active load for the stage, and the bit line polarization circuit provides a polarization voltage level that is independent of the supply voltage level. In a preferred embodiment, the sense amplifier also includes an output stage that improves switching time at high supply voltages.

Abstract: A circuit that provides the root-mean-square (RMS) value of an input signal and that detects and independently recovers from an output fault condition is provided. The circuit includes reconfigurable circuitry that changes from normal operating mode to fault recovery mode when an output fault is detected. During fault recovery mode, the circuit provides a modified output signal that allows independent recovery from an output fault condition. Once recovery is complete, the circuit returns to normal operating mode and provides a DC output signal proportional to the RMS value of an AC input signal.

Abstract: A buffer has an amplifier that receives an external signal, a reference voltage, and outputs an amplified signal. The amplified signal is responsive to the difference between the external signal and the reference voltage. An inverter receives the amplified signal and generates an inverted signal. A voltage supply circuit is configured to provide an adjusted power supply voltage to the inverter responsive to the reference voltage. A ground voltage supply circuit is configured to provide an adjusted ground voltage to the inverter responsive to the reference voltage.

Abstract: A non-delayed input signal is provided to a first comparator input and, a delayed input signal is applied to a second comparator input. An offset voltage is applied between the delayed and non-delayed signals at the comparator inputs. When an input pulse appears on the input signal, the non-delayed input signal will rise immediately and maintain itself more positive than the delayed input, keeping the comparator output inactive. As long as the input signal is rising, the comparator output is maintained low, or inactive. When the non-delayed signal reaches its peak and turns downward, the delayed input signal is still rising and crosses over the first pulse, creating a change of state at the comparator output to a high or active state. The signal edge resulting from this change of start represents initial detection of an input pulse. The time of occurrence of this detection edge is substantially independent of the pulse amplitude.

Abstract: An apparatus comprising one or more input circuits. The input circuit may be configured to generate an output signal in response to (i) an input signal and (ii) an input threshold. The input threshold may be set in response to a control input.

Abstract: A voltage-comparing device applied in a cursor-control input device is provided. The voltage-comparing device includes an analog-signal converter obtaining an initial reference voltage for the follow-up device in an operational procedure corresponding to an input voltage and a comparing circuit sending a feedback to control the input resistance device, the reference voltage and the offset voltage for preventing the voltage comparing device from the disturbance of noises.

Abstract: An apparatus and method permits quick response to a transition at an input port and subsequent propagation of the transition to the output port while being able to process a wide variety of input signal properties. A receiver apparatus comprises at least first and second receivers, each receiver accepting an input signal and tuned for optimal response to a set of known input signal properties. Either first and second primary transition propagation elements or secondary transition propagation element propagates a first transition from one of the receivers. A universal transition propagation element propagates the first transition to an output. A pass gate receives a signal based upon the output and inhibits transmission of the signal based upon the output until the first and second intermediate signals are equivalent whereupon the pass gate is placed in low impedance state permitting the signal based upon the output to be held in a storage node as the preset signal.

Abstract: A circuit which provides that a source voltage and a pad voltage are band-limited and source-followed down in order to get them into the input range of a comparator, the output of which signals an over-voltage condition on the pad. The circuit provides the ability to provide the relationship between the source voltage and pad voltage to a comparator with a very small, tightly-controlled offset. This translates to the ability to detect very small over-voltage conditions on an IO. The circuit consumes little power, is highly accurate, and requires no special, expensive process options. The circuit can be used anywhere there is a desire to compare (with a small, accurate offset) two signals that are close to a source voltage, such as VDD. The circuit can also be used to compare signals close to VSS.

Abstract: The present invention has an object to control easily the pulse width of an output by operating a limiting circuit appropriately-even if the power voltage is low. A limiting circuit is provided on the input side of a hysteresis comparator circuit to prevent saturation. A limit voltage Vlimit is set by a bias circuit so as to change in accordance with the operation of the hysteresis comparator circuit. When an input voltage Vsig exceeds a hysteresis threshold voltage Vth, the limit voltage Vlimit is dropped in response to a drop of the hysteresis threshold voltage Vth. Thus, the width of the pulse width can be controlled while maintaining the condition that the limit voltage Vlimit is higher than the hysteresis threshold voltage Vth.

Abstract: Provided is a semiconductor device including an input/output buffer or an output buffer with a buffer transistor. The device can control the switching speed of the buffer transistor into a proper value even when there is an change in process conditions and/or temperature. The device includes a control circuit for changing the size of the buffer transistor. The control circuit changes the size of the buffer transistor based on the switching speed of the buffer transistor or a detection transistor, which speed changes in accordance with process conditions and/or temperature.

Abstract: An apparatus and method permits quick response to a transition at an input port and subsequent propagation of the transition to the output port while being able to process a wide variety of input signal properties. A receiver apparatus comprises at least first and second receivers, each receiver accepting an input signal and tuned for optimal response to a set of known input signal properties. Either first and second primary transition propagation elements or secondary transition propagation element propagates a first transition from one of the receivers. A universal transition propagation element propagates the first transition to an output. A pass gate receives a signal based upon the output and inhibits transmission of the signal based upon the output until the first and second intermediate signals are equivalent whereupon the pass gate is placed in low impedance state permitting the signal based upon the output to be held in a storage node as the preset signal.

Abstract: A differential pair input receiver (30) having variable reference voltages that may be customized by the designer so as to increase and decrease noise margins of the amplifier. This input receiver (30) includes a complementary self-biased differential amplifier (10) and a dynamic hysteresis voltage reference circuit (20), wherein the complementary self-biased differential amplifier (10) has an input node (Input2), a reference output node (S2), and a dynamic voltage reference node (VDYNREF). The dynamic hysteresis voltage reference circuit (20) connects between the reference output node (S2) and the dynamic voltage reference node (VDYNREF) to provide a reference voltage (Vref) at the dynamic voltage reference node(VDYNREF). The reference voltage (Vref) serves as a threshold for the complementary self-biased differential amplifier (10), such that the output transitions from high-to-low and low-to-high when the input is equal to the reference voltage (Vref).

Abstract: The device and the method enable determining a respectively current level of a digital signal. The digital signal is compared with a threshold value that is located between the state representing the low level of the digital signal and the state representing the high level of the digital signal. The threshold value that is used is matched to the prevailing conditions, that is, the threshold value is defined taking account of the waveform of the digital signal.

Abstract: The present invention implements a signal processing function without the use of a DSP (digital signal processor) or ADC. A reference signal is produced that relates to a DAC output code. The reference signal is used as a starting point, and is compared to the input signal. A feedback signal is produced that is used to adjust the reference. The invention can be used to implement signal processing functions such as peak detection, noise filtering, peak suppression, and the like. The invention can implement these functions with a minimal complexity and a minimal die area.

Abstract: An input buffer is presented for buffering an input signal having a voltage magnitude which alternates between a first voltage level and a second voltage level, where the first and second voltage levels may vary over time. In one embodiment, the input buffer includes a first and second detector circuits, an average generator circuit, and a differential amplifier. The first detector circuit receives the input signal and produces a first signal having a magnitude indicative of the first voltage level. The second detector circuit receives the input signal and produces a second signal having a magnitude indicative of the second voltage level. The average generator circuit receives the first and second signals, and uses the magnitudes of the first and second signals to produce a third signal having a magnitude indicative of a third voltage level substantially mid way between the first voltage level and the second voltage level.

Abstract: A laser radar-proximity fuse with a laser-range measuring device and mask or camouflage discrimination, wherein for the initiation of the fuse, is no longer triggered at the beginning rather but at the end of an echo pulse configuration, even though its comparatively flat descending or falling pulse flank is or is not adapted for the determination of a clear, reproducible or controllable triggering point-in-time. By applying a Constant-Fraction-Trigger-Principle, which has heretofore been applied primarily to the rising or ascending flank of a pulse, there can be also derived a good controllable range or distance-dependent triggering pulse for the thereby optimized initiation of the fuse from the flatter rear flank of the echo pulse configuration, whereby the attacking of the target will not take place prematurely, but will be better directed toward the target center.

Abstract: A current sensing circuit connected to a power supply terminal and having at least one input terminal and at least one output terminal includes at least one bipolar transistor having a base, emitter and collector, at least one current mirror amplifier connected to the power supply terminal, the current mirror amplifier having an input connected to the collector and having at least one output connected to the emitter, and a DC voltage source connected to the base.

Abstract: An offset window detector that senses the sum of two signals and compares the result to a reference voltage for attenuating an offset voltage and producing a desired gain. The primary design issues of the detector is to achieve a very low voltage offset and a low power dissipation. The detector is part of the offset circuits in the I/Q path of a wireless receiver. The maximum input signal and the minimum input signal are the positive and negative peak values of the in-phase or the quadrature signal paths. They are generated by a peak detector. The offset signal can be estimated by the addition of the maximum input signal with the minimum input signal. This resulting offset signal is compared to the reference voltage to determine if the resulting signal is greater than a maximum reference voltage, less than a minimum reference voltage or within the maximum and minimum voltages. A reference voltage generator creates the desired voltages within a desired tolerance.

Abstract: A circuit compares a first voltage and a second voltage using a comparator. The comparator has a current divider for dividing a bias current in accordance with the values of the first and second voltages, and for providing two currents. The comparator also has a current differentiation circuit for receiving the two currents and providing an output signal dependent upon the difference between the currents. At least one of the current divider and current differentiation circuits are arranged to weight one of the two currents with respect to the other current so that the output signal is only provided when the difference between the first and second voltages exceeds an offset value. A bias generator is provided which includes a second comparator having similar components in the same configuration as the comparator.

Abstract: In the circuit for detecting the voltage level of an analog signal, a conversion circuit converts an analog signal to digital signals by comparing the voltage level of the analog signal with a plurality of reference potentials. A filter circuit matches timings of at least either rising edges or falling edges of the digital signals with each other. This prevents malfunction in the voltage level detection.

Abstract: A comparing circuit which suppresses an electric power consumption and promptly traces a DC offset when shifting to a receiving mode. The comparing circuit which needs to trace a DC offset potential is provided with means for enabling power down control functions of a reference voltage generating part and a voltage comparing part on the output side of the part to be independently controlled. In the receiving mode of an apparatus in which the comparing circuit is installed, the reference voltage generating part and voltage comparing part are made operative. In a transmitting mode of the apparatus, only the reference voltage generating part is made operative. In a pause mode of the apparatus, the reference voltage generating part and voltage comparing part are set in a power down state.

Abstract: A pulse generator for indicating a change in the magnitude of an input signal includes a comparator, a first network connected to one input of the comparator for receiving the input signal, and a second network connected to the other input of the comparator for receiving the input signal. Both the first and second networks provide output signals to the comparator which transition in response to a magnitude change of the input signal from their respective baseline magnitudes to respective peak magnitudes, and back to their respective baseline magnitudes. The component values of the networks are selected such that one of the first or second network output signals is positive relative to the other network output signal over some period of time during the transition to the peak magnitude and return to the baseline magnitude to cause the comparator to generate a pulse indicating a change in the magnitude of the input signal.

Abstract: In digital signal demodulation and detection circuits, especially digital radio signal reception and processing circuits, the signals are received in analog form and have to be converted into logic levels. This is done in practice by comparing the level of the signal with its mean level. The mean level is established by an RC lowpass filter which introduces an inconvenient delay into the preparation of the mean level. The mean level of the signal, established by an RC filter is compared and applied to an input B of a comparator COMP, at the level of the analog signal delayed by a phase-shifter and applied to another input A of the comparator. In order that the delay introduced by the phase-shifter into the analog signal may be substantially the same as the delay given to the mean value by the RC circuit, the phase-shifter is made with the same RC circuit and an amplifier mounted so as to set up a phase shift transfer function of the (1−RCp)/(1+RCp) type where p is the Laplace variable.

Abstract: A voltage comparator with hysteresis that includes a differential amplifier, voltage divider circuits and a current mirror circuit. The input terminals of the two differential amplifier circuit branches are biased at unequal potentials by the voltage divider circuits. One voltage divider output voltage is fixed and the other is variable. The input terminal of the differential amplifier circuit branch biased at the fixed potential receives an AC-coupled input signal voltage. The sum of the input signal voltage and the fixed bias voltage is compared against the variable bias voltage. A current mirror circuit, which is activated during conduction by the differential amplifier circuit branch biased at the variable potential, shunts a portion of the current used by the voltage divider circuit that generates the variable potential. This causes the variable voltage divider output voltage to change, thereby introducing hysteresis into the voltage comparison performed by the differential amplifier.

Abstract: The invention relates to a process for converting, by virtue of a threshold, a signal exhibiting alternating rising and falling transitions, into a rectangular signal, wherein the threshold is determined on each transition of the signal to be converted. A device for implementing the process comprises a delay line, whose input receives the signal to be converted by way of an impedance equal to the characteristic impedance of the line, and a comparator whose inputs are linked respectively to the input and to the output of the line.

Abstract: A CMOS amplifier includes a FET differential input stage, with the input transistors' sources connected to a common tail current. A first current mirror reflects the drain current from one input FET to the other at a first node. A pair of FETs are connected to conduct respective currents in response to the voltage at the first node. One of the currents drives a load at a second node, which is connected to one of the input stage gates such that the output voltage tracks an input voltage applied to the other input stage gate. The other current is reflected via a second current mirror to provide the common tail current. By properly sizing the FETs to achieve particular current densities, the tail current is automatically varied to adjust the operating point of the differential input stage such that, when the amplifier is in equilibrium, the drain voltages of the input FETs are kept equal over a wide range of output currents.

Abstract: A reference-corrected ratiometric current sensing circuit for sensing a current flowing through a load and a power-controlling pass device includes a sense device, a sense resistor, and a variable reference current source for providing a varying reference current. The varying reference current is varied according to a ratio of the voltage across the sense device to the voltage across the pass device. The ratiometric current sensing circuit of the present invention is capable of accurate current sensing in spite of disparities that may occur between the voltages across the sense and the pass devices. In one embodiment, the variable reference source includes a transconductance amplifier circuit that provides an output current indicative of the voltage difference at its input terminals. Furthermore, the variable reference current source includes a translinear circuit that works with the transconductance amplifier circuit to implement the prescribed arithmetic operations to generate the varying reference current.

Abstract: The sensor configuration has a sensor and a calibration circuit, which self-calibrates the system by setting its switching points. The calibration circuit is located in the output circuit of the sensor. The method utilizes the calibration circuit to set an offset in the output circuit using an offset D/A converter in such a way that the switching points coincide with reference values. The offset D/A converter is driven with a calibration logic unit.

Abstract: A method for monitoring a defined amplitude threshold value of a signal formed by alternating voltage and a circuit for carrying out such a method.

Abstract: Comparators, memory devices, comparison methods and memory reading methods are provided. One aspect provides a comparator including an input stage having a data input adapted to receive a data voltage signal, a reference input adapted to receive a reference voltage signal, and a plurality of current sources individually coupled with one of the data input and the reference input and individually configured to convert one of the data voltage signal and the reference voltage signal to a differential current signal and to output the differential current signal; and a comparator stage including a plurality of inputs configured to receive the differential current signals from the input stage and the comparator stage being configured to compare the differential current signals and to output an output signal indicative of a comparison of the differential current signals.

Abstract: A level detection circuit for monitoring the level of a power supply voltage and producing an output signal at power on for resetting various system elements powered by the supply voltage when the supply voltage reaches a predetermined level. The detection circuit, which is powered by the supply voltage includes a voltage reference circuit which produces a reference voltage having a magnitude which is relatively independent of the power supply voltage. A translator circuit functions to produce a translated voltage indicative of the supply voltage magnitude and which is comparable in magnitude to the reference voltage when the supply voltage is at a suitable level such that the system will accept a power on reset pulse. A comparator circuit functions to compare the reference voltage with the translated voltage and cause an associated output circuit to issue the reset pulse. The reset circuit typically includes a one shot circuit, the output of which is logically ORed with the amplified comparator output.

Abstract: A device for amplifying a signal includes a first amplifier which amplifies an input signal with reference to a reference voltage level to generate an amplified signal, a limiter circuit which limits an upper end of the amplified signal to a level twice as high as the reference voltage level so as to output a limited amplified signal, a second amplifier which amplifies the limited amplified signal with reference to an average of the limited amplified signal, and a comparator which compares an output of said second amplifier with the reference voltage level to output a result of the comparison.

Abstract: A voltage detection circuit is capable of detecting a low voltage without malfunctioning, and this so even if the voltage is lower than a minimum operating voltage. The voltage detection circuit includes two input terminals, a voltage selecting circuit, and a voltage-detecting integrated circuit (IC). In operation, a standard voltage is input into a first input terminal of the voltage detection circuit and the voltage to be detected is input into the second input terminal. The first terminal voltage is then divided by a voltage divider circuit. This divided voltage and the voltage to be detected are input into the voltage selecting circuit, which outputs one of the voltages to the voltage detecting IC. The voltage detecting IC compares the input voltage to a detection voltage and outputs a value accordingly.

Abstract: The invention provides adaptive threshold circuits for comparators, whereby the threshold voltage adapts to characteristics of the input signal. In one embodiment, the steady-state threshold voltage stored on a peak-detector capacitor is generated by ratioing the base-emitter voltages of two emitter-follower transistors. As the input signal varies, the threshold voltage follows the input signal. Voltage-controlled current sources sense the amplitude of the input signal, and adjust the amplitude of the threshold voltage by controlling the voltage dropped across a resistor. A feedback signal that indicates the state of the comparator output is coupled to the adaptive threshold circuit to provide hysteresis. In another embodiment, the threshold voltage is determined by the voltage drop across a first resistor. Voltage-controlled current sources sense the amplitude of the input signal, and adjust the amplitude of the threshold voltage by controlling the voltage dropped across a second resistor.

Abstract: To retrieve analog signals at high precision by a maximum or minimum position detection parallel signal processing circuit, a plurality of circuit units in each of which a gate of a transistor is connected to a signal input terminal through first capacitive means, a common connecting point of the gate and the first capacitive means is connected to one terminal side of second capacitive means, and control means, for fluctuating a voltage on the other terminal side of the second capacitive means so as to further increase or decrease a drain current in correspondence to an increase or decrease in the drain current is connected between the drain and the other terminal side of the second capacitive means are provided, a source of each transistor of the plurality of circuit units is commonly connected and is connected to a constant current source, and the maximum or minimum voltage position detection with respect to a signal voltage which is applied to each signal input terminal is performed by a voltage on the oth

Abstract: A method for detecting data outputted from an optical coupler is presented comprising the steps of setting a reference recognizing level by inputting the data in an initial state to an A/D converter; recognizing the level of the data in a noninitial state as high if the level of the data at the non-initial state is greater than the reference recognizing level; recognizing level of the data in the non-initial state as low if the level of the data at the non-initial state is less than the reference recognizing level; and setting the level of the data at the non-initial state to equal the reference recognizing level if the level of the data at the non-initial state is recognized as low.

Abstract: A delay circuit (7) delays a transfer signal (V1) transferred through a transfer signal line (1) by the first delay time (dt1) to generate the first delayed signal (V9) and delays the first delayed signal (V9) by the second delay time (dt2) to generate the second delayed signal (V10). The second current mirror differential amplifier circuit (11) receives the transfer signal (1) and the second delayed signal (V10), whose ground terminal is connected to the first delayed signal line (9). On the other hand, the first current mirror differential amplifier circuit (14) also receives the transfer signal (V1) and the second delayed signal (V10), whose power-supply terminal is connected to the first delayed signal line (9). In response to a rise of the input signal (V1), the circuit (14) starts its operation to change a level of an output signal (V6) from "L" level to "H" level, remaining thereafter.

Abstract: A precision analog circuit ensures precision matching between two or more resistive elements. In order that the two or more resistive elements are truly matched, a first electrical value, such as V.sub.DS, of the two or more resistive elements are equal and a second electrical value, such as V.sub.GS, of the two or more resistive elements are equal so that a ratio of the first resistive element to the second resistive element is a predetermined value regardless of the voltage coefficients of the resistive elements.