Abstract: A zero-power sense amplifier for implementing a wide or multiple input NOR gate for receiving a product term of a group of array cells in a programmable logic device (PLD). In a sleep mode, or low power mode, the zero-power sense amplifier latches its previous state while drawing negligible power rather than returning to one particular state, such as a low state, as in previous devices, enabling recovery time to be reduced after entering an awake mode. The zero power sense amplifier further reduces recovery time upon powering up from a sleep mode by maintaining the product term voltage close to a threshold input voltage during sleep mode while still drawing negligible power.

Abstract: A receiver squelch circuit has a programmable DC threshold level. The squelch circuit includes input circuitry that responds to an incoming signal by generating a decision signal when the DC voltage level of the incoming signal crosses a predetermined threshold level. A programmable control network selectively varies the predetermined threshold level.

Abstract: Disclosed herein is a circuit for limiting the output current I.sub.O of a power MOSFET T.sub.1. A resistor R.sub.2 converts the current I.sub.O into a low voltage V.sub.0. The low voltage V.sub.O is detected by a low-voltage detecting circuit. When the low voltage V.sub.O is higher than a predetermined value V.sub.OL, the output current I.sub.O of the power MOSFET T.sub.1 is limited. The low-voltage detecting circuit comprises bipolar transistors Q.sub.1 to Q.sub.4. The base and collector of the transistor Q.sub.1 are connected to each other. The collector of the transistor Q.sub.2 is connected to the emitter of the transistor Q.sub.1. The base and emitter of the transistor Q.sub.3 are connected to the bases of the transistors Q.sub.1 and Q.sub.2, respectively. The base and collector of the transistor Q.sub.4 are connected to the emitters of the transistors Q.sub.1 and Q.sub.3, respectively. The low voltage V.sub.O is applied to the node between the emitters of the transistors Q.sub. 2 and Q.sub.4.

Abstract: A pulse detection circuit detects one different pulse within a string of similar pulses for a once per revolution index. The pulse detection circuit comprises a DC averaging means for generating a first threshold voltage from a raw signal. An average comparator receives the first threshold voltage and generates a first output voltage indicative of signal amplitude of the raw signal, as compared to the first threshold voltage. A zero comparator receives the raw signal, compares it to zero, and generates a second output voltage indicative of a pulse. The first and second output voltages are input to a logic sequence to generate a logic output when the one different pulse within the string of similar pulses is detected.

Abstract: A rate of change comparator uses an RC charging circuit and a separate RC discharging circuit to follow a transducer output. The resistor component of each RC circuit is shunted by a diode, each biased in a different orientation so that the charging circuit charges quickly through its diode but discharges slowly through its resistor and the discharging circuit discharges quickly through its diode and slowly through its resistor. The difference in output between the charging and discharging circuits is detected with a comparator, biased off by a threshold bias voltage developed from one of the circuits. The comparator is unaffected by slow changes in transducer signals due to drift, ambient condition and similar changes because the differential voltage between the circuits is minimized for transducer signal changes below the level set by a threshold bias level.

Abstract: A pulse-signal extracting method and apparatus which are capable of generating an accurate pulse output even if the pulse input signal greatly pulsates due to a low-frequency noise component. A predetermined offset voltage is added to the input signal where the low-frequency noise component is superimposed on a pulse waveform which is the signal component so as to obtain an amplified signal. This amplified signal is inputted to a low-pass filter so as to output only the amplified flow-frequency component, and the original input signal is compared with the amplified low-frequency component in a comparator so as to extract the pulse waveform, which is the signal component, on the basis of the comparison result.

Abstract: A binary coding circuit that enables a clear image to be obtained by removing noise elements while retaining the target character and image information, improves image compression efficiency, reliably binarizes low-contrast characters and images and minimizes information loss, thereby providing clearer and more accurate binarized images of character and image information.

Abstract: A signal processing circuit is to be connected to an output stage of a charge-coupled device which includes a reference signal circuit and a CCD signal circuit that generate first and second output signals, respectively. The signal processing circuit includes a differential circuit and first and second amplifiers. The differential circuit receives the first and second output signals from the output stage of the charge-coupled device and generates a first signal corresponding to the first output signal and a second signal corresponding to the second output signal. The first amplifier has an output, a first input which receives the first signal from the differential circuit, and a second input which is connected to the output to serve as a negative feedback input thereto. The second amplifier has an output, a first input which receives the second signal from the differential circuit, and a second input which is connected to the output of the first amplifier to serve as a negative feedback input thereto.

Abstract: A maximum likelihood sequence metric calculator for use in a sequence decoder for processing sequences of sampled values from a communication channel or recording device. The metric calculator can be used in a maximum likelihood decoder, where the sequence can be based upon a 2-state trellis. This would include duobinary, dicode, or partial response class IV signalling. The survivor metrics for the two states is proportional to the peak amplitude detected for that state. Thus, the peak amplitude for a state is stored by a peak detector, until an opposite polarity amplitude is detected to switch the trellis path to the opposite polarity state. The path switching threshold to a state is determined by the opposite polarity state's peak amplitude and the maximum likelihood threshold value. Since only the peak amplitude of the state is stored, unbounded metric absolute value growth is not a problem.

Abstract: A time of arrival detector for an analog pulse signal digitizes the pulse, digitally delays the digitized signal in one path and converts the delayed signal back to a delayed analog version of the input signal. In a second path an undelayed analog version of the input signal is provided. A scaling offset is established to scale the delayed signal larger than the undelayed signal, and the delayed and undelayed signals are then compared to establish a time of arrival for the input pulse. A delta modulator is preferably used to provide the digitized signal, and also to provide the undelayed analog version of the input signal as the smoothed output of an integrator within the delta modulator. The undelayed modulator output is preferably attenuated by -3 dB, with the pulse's time of arrival obtained from the time at which the delayed analog signal rises above the undelayed but attenuated signal.

Abstract: A peak detector for use in a fiber optic receiver has a capacitor, an input amplifier driving the capacitor, and a feedback differential amplifier coupled between the capacitor and an input of the input amplifier. The input amplifier is a complementary buffer with unity gain modified to include an additional transistor on one rail that receives an inverter voltage generated by the differential amplifier. The inverter voltage equals the difference between twice the capacitor voltage and an input voltage applied to the peak detector. The input amplifier in a positive peak detector functions so that the capacitor voltage tracks the input voltage when it exceeds the inverter voltage, and equals the average of the input voltage and inverter voltage when the input voltage is less than the inverter voltage. A negative peak detector operates similarly but with opposite polarity. The peak detector also contains transistors used to reset the capacitor voltage upon assertion of a reset signal.

Abstract: An optical imaging surface inspection system and method are provided. The system comprises an illumination source for illuminating an image pattern on a surface to be inspected, a video camera for detecting a portion of the light reflected from the surface and outputting an analog video signal, a dynamic thresholding circuit for converting the analog video signal into a digital representation of the image pattern, and means to compare a known accurate digital representation of the image pattern to the digital representation provided by the dynamic thresholding circuit. The method includes the steps of illuminating the surface, scanning the surface with the video camera, separating the video signal into a black level signal component and a white level signal component, detecting successive peak levels in the white level signal component and outputting a corresponding variable peak voltage. A variable threshold voltage is determined by selecting a percentage of the variable peak voltage.

Abstract: A programmable digital delay line having N delay elements, two multiplexers connected to the output of the delay elements, and a comparator connected to the outputs of the multiplexers is disclosed. The invention teaches an apparatus and a method of delaying a signal, while reducing the number of delay elements and the number of connections to multiplexers. In a first embodiment of the invention, the delay elements are inverters or differential delay elements. In a second embodiment, the delay elements are differential delay elements.

Abstract: In an integrated microcircuit device the supply voltage is monitored by a pair of threshold detector logic circuits configured to generate a first control signal when said supply voltage crosses over a minimum level, and a second control signal when said supply voltage crosses over a maximum level. The control signals are used to configure the device into distinct modes of operation, whereby the functions of the device and the voltage level of the power supply applied to them during testing or operation may be controlled by varying the supply voltage.

Abstract: A dc-coupled packet mode digital data receiver, for use with an optical bus, uses a peak detector(s) to adaptively establish an instantaneous logic threshold at the beginning of a data burst. A reset circuit resets the peak detector(s) and other circuits of the receiver in response to an end-of-packet reset signal, thereby enabling the reception of closely-spaced burst date packets which have greatly differing power levels.

Abstract: In a highly integrated semiconductor memory device, apparatus for setting a stress mode without applying a stress voltage from the exterior is provided. A triggered time point T.sub.S to a stress mode can be set by greatly raising an internal supply voltage when the external supply voltage is raised to a voltage over the stress voltage.

Abstract: A waveform classification system uses a detector 10 for detecting an analog input x(t), as well as sampler 14 and quantizer 16 to convert this analog input into a series of digital values {J.sub.k-1, J.sub.k, J.sub.k+1 }. This series of digital values {J.sub.k-1, J.sub.k, J.sub.k+1 } is represented by a fixed number of quantized digital values. A collection of predetermined feasible values is held in a feasible set table 20. A waveform classifier 18 compares the digital series from the quantizer 16 to the predetermined series held in the feasible set table 20. The waveform classifier 18 has an output, f(Z.sub.k), that marks the data in the digital series as either high or low interest. Low interest data can either be eliminated or reduced in priority to improve the overall system performance.

Abstract: A hysteresis comparator is disclosed which utilizes an on-chip bias generator, and incorporates circuitry which renders the decision voltages V.sub.P and V.sub.N insensitive to semiconductor process variations, independent of any critical reference voltages, and proportional to absolute temperature. Current sources coupled to positive and negative bias voltages are utilized to generate precise voltages across resistors to set the magnitude of V.sub.P and V.sub.N, which magnitudes are set by the ratios of like components existing within the same integrated circuit. Hysteresis comparators with precise and repeatable decision voltages can be implemented while consuming a minimum amount of semiconductor area.