Abstract: A peak detector that compares an input signal to a first reference voltage to produce a maximum sample signal, and compares the input signal to a second reference voltage to produce a minimum sample signal, wherein the maximum and minimum sample signals produce a sampling of the current input signal thereto to produce a maximum output signal and a minimum output signal, respectively. The detector compares the previously retrieved input signal value with a current input signal value. The current input signal is used as the maximum output signal if it is greater than a previous maximum output signal and providing the current input signal as the minimum output signal if it is less than a previous minimum output signal. The output provides signal level and offset signal information which, when gated with a predetermined clock signal, produces nonoverlapping phased output signals.

Abstract: A comparator with hysteresis having a simplified architecture such that the amount of hysteresis can be readily adjusted. In one aspect, a comparator with hysteresis comprises a first switch for coupling an analog input voltage to a signal node in response to a first clock signal; an inverter having an input port and an output port; a capacitor operatively coupled between the signal node and an input port of the inverter; a second switch operatively connected between the input port and the output port of the inverter, the second switch being responsive to the first clock signal; a latch having a clock port, an output signal port, an inverse output signal port, and an input data port, the input data port being coupled to the output port of the inverter; and a reference voltage control circuit for selectively outputting a first internal reference voltage and a second internal reference voltage to the signal node in response to the output signal and inverse output signal, respectively, received from the latch.

Abstract: A voltage detection circuit is capable of detecting a low voltage without malfunctioning, and this so even if the voltage is lower than a minimum operating voltage. The voltage detection circuit includes two input terminals, a voltage selecting circuit, and a voltage-detecting integrated circuit (IC). In operation, a standard voltage is input into a first input terminal of the voltage detection circuit and the voltage to be detected is input into the second input terminal. The first terminal voltage is then divided by a voltage divider circuit. This divided voltage and the voltage to be detected are input into the voltage selecting circuit, which outputs one of the voltages to the voltage detecting IC. The voltage detecting IC compares the input voltage to a detection voltage and outputs a value accordingly.

Abstract: A transient signal detector for monitoring a signal line and generating a control signal which indicates when the magnitude of a differential signal on the line exceeds either a positive or negative threshold value. The threshold value is defined by a single current, thereby allowing for a single, simple adjustment of such threshold in both the positive and negative directions.

Abstract: A improved signal detector is provided. The signal detector includes a linear amplifier receiving the input signal and providing an amplified signal. A full-wave rectifier is coupled to the linear amplifier and provides a rectified signal. A low-pass filter is coupled to the full-wave rectifier receiving the rectified signal and providing a comparing signal. A high threshold reference and a low threshold reference respectively is applied to a first comparator and a second comparator, each receiving the comparing signal. The first comparator and the second comparator respectively provide a first compared signal and a second compared signal. A reference path providing the high threshold reference and the low threshold reference includes a linear amplifier, a full-wave rectifier and a low-pass filter providing the high threshold reference. A linear charge pump is connected at its input to the linear amplifier and connected at its output to a low-pass filter to provide the low threshold reference.

Abstract: A voltage to frequency converter using a charge pump to restore the output voltage of the input integrator. The charge pump implementation allows the voltage to frequency converter's input to sense voltage above and below ground with a single supply using a charge pump, which can provide either a positive charge or a negative charge as the restoring force to the integrator. Inclusion of an interleaved charge pump provides advantages of implementation simplicity and of high performance. The voltage to frequency converter concentrates all offset and leakage errors at the input of the integrator amplifier, which in the preferred embodiment is a chopper stabilized amplifier providing very low offset. The voltage to frequency converter is intended for realization in integrated circuit form, providing very high performance in an integrated circuit having very low power requirements.

Abstract: A multifunction reset circuit including low power bandgap, a comparator, and an open drain buffer circuit--with the inclusion of four external components (three resistors and one capacitor) to provide undervoltage monitoring, power failure indicating, manual resetting and other reset control conditions to a single integrated circuit terminal, together with hysteresis tolerance.

Abstract: A three input comparator facilitates the comparison of a signal to the greater of two different reference voltages in a manner which mitigates propagation delay. A first differential pair of transistors facilitates comparison of the two reference voltages to one another, while second and third differential pairs of transistors facilitate comparison of the signal to the higher of the two reference voltages.

Abstract: A variable threshold comparator receiving, on an input node, an input signal having a voltage, and providing an output signal on an output node when the voltage of the input signal exceeds a selectable threshold voltage of the comparator. The comparator includes a transistor coupled by way of its source and drain between a power supply and an output node, and having its gate coupled to the input node. Also included are a plurality of pairs of transistors coupled together by a source of a first one of the pair of transistors and drain a drain of a second one of the pair of transistors, and coupled in series between the output node and a ground, a gate of the first one of the transistors coupled to the input node, and a gate of the second one of the transistors coupled to a control signal specific to the second one of the transistors. The threshold voltage of the comparator is selectable by the application of one or more of the control signals to a respective one or more of the second ones of said transistors.

Abstract: When more than two terminators are on a SCSI bus the bus is said to be "over-terminated", and when less than two terminators are on the bus, the bus is said to be "under-terminated". When the SCSI bus is either under or over terminated, the bus does not function, and often the user does not know why the bus is not functioning. Apparatus and a method are provided for indicating to the user when the bus is not properly terminated. A terminator monitoring system and method operate in conjunction with the bus. A precision resistor is connectable to the bus so that a voltage drop is produced across the precision resistor. A circuit monitors the value of the produced voltage drop across the precision resistor to provide an indication of the number of terminators on the bus. A switch selectably connects the precision resistor to the bus, and there is a source of a reference voltage.

Abstract: A programmable logic device that includes a voltage input and a detection circuit coupled to the voltage input is described. The detection circuit detects whether a voltage applied to the voltage input exceeds a predetermined value. The programmable logic device also includes a configuration circuit coupled to the detection circuit. The configuration circuit configures the programmable logic device to receive a current sufficient for program and erase operations through the voltage input in response to the detection circuit detecting that the voltage exceeds the predetermined value.

Abstract: The disclosure relates to detectors of the level of supply voltage in an integrated circuit. The disclosed detector is designed to detect the crossing of low levels of supply voltage. It comprises a first arm to define a first reference voltage and a second arm to define a second reference voltage, these two reference voltages varying differently as a function of the supply voltage and their curves of variation intersecting for a value of the supply voltage located close to a desired threshold. A comparator receives the two reference voltages. The first arm has a resistive divider bridge, an intermediate connector of which constitutes the first reference voltage. The second arm comprises a resistor series-connected with a native P type MOS transistor, the point of junction of this resistor and this transistor constituting the second reference voltage. A non-linear element may be parallel-connected to the resistor which constitutes the first reference voltage.

Abstract: The present invention discloses a much higher speed interface apparatus which comprises a data driving means for decoding two-bit data signals using them as inputs to output four-level data signals; a reference voltage generating means for generating three-level reference voltages to discriminate the voltage levels of the four-level data signals; and a receiver means for comparing the four-level data signals and the three-level reference voltage signals using them as inputs and for encoding the resulting signals to output two data signals.

Abstract: A method and an apparatus for reducing baseline wander in a differential signal. In one embodiment, the differential signal is carried in first and second signal lines. If negative baseline wander is detected in the differential signal, a first pair of current sources is activated. One of the first pair of current sources thereby sources current into the first signal line and the other one of the first pair of current sources thereby sinks current from the second signal line as a result until the negative baseline wander is reduced to a level approximately equal to a preset threshold value. If positive baseline wander is detected in the differential signal, a second pair of current sources is activated.

Abstract: An input buffer of the present invention includes: a plurality of receiver circuits for performing different phase adjustments on an input signal, and outputting the differently phase-adjusted signals; a pattern detection circuit for detecting a period of time for which a voltage of the input signal has remained unchanged; and a signal selection circuit for selecting one of the output signals received from the receiver circuits based on the detection result from the pattern detection circuit.

Abstract: A level adjusting circuit for controlling a voltage supplied to a load such as a semiconductor device, which comprises a voltage level detecting circuit, a reference potential generating circuit for generating a pair of reference potential values to be output into the voltage level detecting circuit, and a monitor pad for drawing out the voltage supplied to the load, wherein the reference potential values are respectively used to compare with the voltage to thereby output a signal for starting supply of the voltage and a signal for ceasing the supply of the voltage under a usually used condition; and the voltage level detecting circuit is to compare either one of the reference potential values with the voltage or the other reference potential value with the voltage at a time under a testing condition, whereby the reference potential generating circuit can accurately be adjusted to change the reference potential values to render the voltage in a range permissible for operation of the load.

Abstract: Generally speaking, steep signal edges are required for the processing of digital signals; however, notably externally supplied signals which are conducted, for example, via long cables are liable to have comparatively flat signal edges. By selecting appropriate switching thresholds, delays between an input signal and an output signal of a circuit can be minimized. The circuit selects the first switching threshold at a low value of the input signal and switches the first threshold value to a second, higher threshold value when the input signal exceeds a further, higher threshold value. Thus, an output signal is generated comparatively quickly after the beginning of the positive-going or negative-going edge of the input signal. This can be realized by switching over the switching threshold of a comparator or by utilizing two comparators.

Abstract: A differential receiver having a precision input referred offset and a wide CMR, wherein a pair of differential-difference amplifiers are used as differential comparators. The differential-difference amplifiers are configured to allow a precision input-referred offset to be set by the use of two reference voltages. The differential comparators each have a common-mode range over a different portion of the rail-to-rail voltage range. A first one of these differential comparators is activated when the input common-mode voltage is above a threshold level. A second differential comparator is activated when the input common-mode voltage is below the threshold. The output of the differential comparator that is selected is to provide a comparison output signal, thereby achieving a wide CMR. The selection of either the first or second differential comparator is made by a selection circuit that includes a differential Schmitt Trigger and a multiplexer.

Abstract: A switched capacitor differential comparator (10) for receiving input signals which includes hysteresis circuitry (40, and 42) and a switch (43) responsive to timed clocking pulses occurring during alternating reset and comparison periods for application of a hysteresis current during a reset period of the differential comparator which current is injected into an applicable one of a pair of load devices (22, 24) to produce a hysteresis voltage offset at a selected one of the differential inputs (30, 32) which is stored during the reset period but removed during the next comparison period so that the hysteresis voltage is not canceled but remains superimposed on the stored input signals during the next comparison period to introduce hysteresis to influence the current output decision of the comparator circuit based on the decision of the comparator resulting from the previous comparison period.

Abstract: A static key interface circuit has an input terminal coupled to N key switches, where N is an integer greater than one. The N key switches are biased at different potentials, which are supplied to the input terminal when the key switches are closed. A multilevel detector in the key interface circuit detects the potential of the input terminal and generates corresponding result data. A dynamic key interface circuit has an input terminal coupled to P rows of N key switches each and scans the P rows in turn, using a similar multilevel detector. The multilevel detector increases the number of key switches connectable to a single input terminal by a factor of N.

Abstract: The present invention provides an input receiver in a differential amplifier or modified differential amplifier configuration which adjusts the input high and low voltage signals compatible with multiple input/output (I/O) interfaces, including transistor-transistor logic (TTL), Low Voltage TTL (LVTTL), and Stub Series Terminated Logic (SSTL) interfaces. Transistors in a differential amplifier or modified differential amplifier configuration that receive a reference.sub.-- voltage signal and receiver.sub.-- enable signal are adjusted in accordance to the input high signal and input low signal requirements for a selected type of interface, while other transistors remain at a relatively constant voltage. Once a particular type of interface has been selected, the gate voltages for the transistors that receive the reference.sub.-- voltage and receiver.sub.-- enable signals remain relatively constant.

Abstract: A fault tolerant communication system for transmitting a serial data signal through multiple wires regardless of whether one of the wires is open circuited, shorted to ground, shorted to a positive power supply. The system includes at least two communication lines. Each communication line is provided with identical data signals. The outputs of the communication line are adapted such that the active levels of each of the respective data signals appear within a predetermined voltage range. At least two detecting means are coupled to the communication lines. Each of the detecting means transmits one of the respective data signals only if the active levels of at least one of the respective data signals is within the predetermined voltage range. A fault is detected when the active level of any of the data signals is outside the predetermined voltage range. Combining means are coupled to each of the detecting means for combining the respective data signals from the detecting means into a single data signal.

Abstract: A transient signal detector for monitoring a signal line and generating a control signal which indicates when the magnitude of a differential signal on the line exceeds either a positive or negative threshold value. The threshold value is defined by a single current, thereby allowing for a single, simple adjustment of such threshold in both the positive and negative directions.

Abstract: A dual-threshold voltage comparator circuit utilizes a single input pin of an integrated circuit and an external resistor network. Appropriate selection of the resistors comprising the resistor network permits independent setting of the dual thresholds of the comparator.

Abstract: An input first stage circuit performing switching between activation and inactivation in response to an input signal includes a differential amplifier for comparing the input signal with a reference voltage and a switching transistor for receiving a power supply disconnection signal to control the power supplied, and a level detection circuit including a low level standby detector for detecting a low level of the input signal and a high level standby detector for detecting a high level of the input signal.

Abstract: A comparison circuit (4) is formed by a Schmidt buffer (4a) which has first and second threshold values and a buffer (4b) whose threshold value is larger than the first threshold value but smaller than the second threshold value. An integrating circuit (3) and the comparison circuit (4) function as a timer circuit which operates in accordance with comparison of the three values. An input signal (IN) decreases from a reference voltage signal (V6). A control signal becomes an H level after a time which is determined by a time constant of the integrating circuit (3) and the threshold value of the buffer (4b), and a detect signal (FO) is outputted after a time which corresponds to a difference between the second threshold value and the threshold value (which is equal to or shorter than a response time of the circuit (4)). During monitoring of a d.c.

Abstract: A buffer circuit including current sources and switches to connect and disconnect current sources to an output node. The switches are controlled by voltage detectors for comparing an input signal with a reference level. When the reference level is a predetermined value, the amplitude of an output signal swings up to V.sub.CC and swings down to V.sub.EE.

Abstract: A circuit device for selecting operating modes using a single reference pin that uses current rather than voltage in an electronic subsystem. An operating mode is selected by modulating the input bias current over a range of values. A specific range is associated with a given function so that a value of current can assume a parametric input into the subsystem. The circuit has widespread application since current can be modulated faster than voltage and it eliminates the need for multiple voltage reference points.

Abstract: A subscriber line interface circuit which includes a transient signal detector with temporal hysteresis. During steady state operation, the drive current for the subscriber loop allows the loop to respond to changes in loop conditions according to a steady state time constant of the loop filter. Upon detection of a line voltage transient which exceeds a predetermined threshold in either a positive or negative direction, the filter time constant is significantly reduced (e.g., 100:1) and held at such reduced value following the initial transient and for a predetermined time period after the line voltage has fallen back below such predetermined threshold. This allows the transient conditions to be fully compensated prior to resetting the filter time constant back from the lower transient value to the higher steady state value.

Abstract: A delay circuit having standby state and active state and designed to output at least one signal obtained by delaying an input signal. The delay circuit comprises a storage circuit and at least one amplifier circuit. In operation, the storage circuit receives an input signal, generates a first voltage when the input signal is inverted, and generates a second voltage from a difference between the first voltage and a first supply voltage. The amplifier circuit amplifies the difference between the first voltage and the second voltage.

Abstract: A logic circuit for providing hysteresis in the sensing of the temperature of an integrated circuit includes two voltage comparators and a D-type flip-flop. Each of the comparators compares a reference voltage and a respective one of two voltage signals which represent and vary in respective relations to the temperature of the integrated circuit. The resulting binary output signals of the comparators are asserted and de-asserted at different approximate temperatures, i.e., with one being higher and the other being lower with respect to one another. One comparator output signal serves as both the input data signal and output clear control signal for the flip-flop while the other serves as the clock signal. Accordingly, the output signal of the flip-flop is asserted during a time which follows an increase in the measured temperature above the higher approximate temperature value and precedes a decrease in the measured temperature below the lower approximate temperature value.

Abstract: A window comparator includes a differential circuit stage and a load circuit stage. The differential circuit stage produces a pair of differential currents from an input voltage, the differential currents varying depending on the input voltage with having a maximum and a minimum when the input voltage is a reference voltage. The load circuit stage produces an output voltage from a reference current and a current corresponding to a selected on of the differential currents. The reference current and the current are produced such that a voltage range is determined around the predetermined voltage depending on whether the second current is greater than the reference current. Since a window of the window comparator is formed based on the current and the reference current, the output voltage changes in level depending on whether the input voltage falls into the voltage range.

Abstract: A multivalued FSK demodulation window comparator includes an MSB comparator, an LSB comparator, a reception electric field strength detector, and a reference voltage generating circuit. The MSB comparator determines at least the polarity of a frequency shift of a radio frequency. The LSB comparator determines the absolute value of the frequency shift of the radio frequency. The reception electric field strength detector detects the strength of a radio signal and outputs a signal corresponding to the detected strength. The reference voltage generating circuit changes the reference voltages of the LSB comparator in accordance with an output voltage from the reception electric field strength detector. When the output voltage from the reception electric field strength detector is not higher than a predetermined level, a reference voltage from the reference voltage generating circuit changes.

Abstract: A trigger voltage controllable Schmitt trigger circuit consists of: a trigger-inverting output unit for trigger-inverting input signals in a predetermined margin; a trigger voltage control signal output unit for generating control signals for controlling trigger voltage according to external control signals, the unit including a linear differential amplifier; and first and second trigger voltage control units for changing margins of trigger performed by the trigger-inverting output unit, the units including transistors whose resistance ratios linearly change according to the control signals from the trigger voltage control signal output unit.

Abstract: A first comparison circuit compares an internally generated clock signal with a reference signal and produces a first error signal in response to timing differences between rising edges of the clock signal and the reference signal. A second comparison circuit compares the internally generated clock signal with the reference signal and produces a second error signal in response to timing differences between falling edges of the clock signal and the reference signal. The first and second error signals are applied to control inputs of a phase shifter chain to control delay in each stage to reduce the timing error with respect to each edge.

Abstract: The circuit for sensing a memory having a plurality of threshold voltages is directed to using a technique for maintaining a characteristic curve of a voltages-matched circuit and combining a characteristic curve in which the voltage is moved by a minimum value which is one half of the reference voltage with a conventional characteristic curve, so that it is possible to reduce in half the minimum distance between the voltage distributions for thereby optimizing the above distance by controlling the power voltage irrespective of the characteristic of a device.

Abstract: A comparator including one or more transconducting inverters, each inverter biased to operate in a subthreshold state so as to have a desired high transconductance. In preferred embodiments, the transconducting inverter is biased in subthreshold by a bias voltage whose value is independent of process and environmental variations (so that the subthreshold current density in the inverter remains fixed despite supply voltage variations and other process and environmental variations). The bias voltage is generated by servoing an unregulated supply voltage so that the bias voltage has lower magnitude (relative to ground potential) than the supply voltage. The reduced-magnitude, regulated bias voltage precisely regulates at least one transistor in each inverter by forcing a constant current density therein, thereby causing the cell to operate in subthreshold.

Abstract: A dual reference voltage input receiver comprises a latch, comparison logic for determining the voltage level of a data signal relative to that of first and second reference voltage levels, and selection logic for determining which of the reference voltage levels is operative for a given data interval, e.g. clock cycle. The latch couples the determined voltage level of the data signal to a subsequent stage and to the selection logic for determining the operative reference voltage level in the next data interval. In one embodiment of the invention, the comparison logic includes first and second comparators for comparing the data signal with first and second reference voltages, and the selection logic is a MUX having its data inputs coupled to the comparators' outputs and its selection input coupled to the data output of the latch.

Abstract: A comparator with a built-in offset is disclosed. The claimed comparator includes a bias current circuit, a differential input stage with the built-in of-set, and a hysteresis circuit. The built-in offset is generated by using a resistor in the differential input stage of the comparator such that the resistor is driven by the bias current as well as the current generated by the hysteresis circuit. Additionally, a reset circuit which uses the comparator with the built-in offset is claimed. The reset circuit uses a voltage divider circuit to divide a first input voltage to the comparator. A band-gap voltage reference is used to provide a second input voltage to the comparator. Therefore, the reset circuit generates a reset signal when the divided voltage reaches the value of the band-gap voltage plus the offset. In another embodiment, a comparator having a differential input stage, an output stage, and a bias circuit with a hysteresis circuit is disclosed.

Abstract: An integrated circuit chip having circuitry to adjust its threshold voltage between a plurality of threshold voltages for interfacing to integrated circuit chips having different supply voltages. The integrated circuit chip also includes circuitry for communicating its threshold voltage level to a second integrated circuit such that the second integrated circuit may set its threshold voltage prior to receiving logic communications from the integrated circuit. The present invention also discloses an integrated circuit that detects the logic level of incoming logic communications and adjusts its threshold voltage accordingly.

Abstract: An arrangement for monitoring an alternating signal with respect to its state as mark-to-space ratio or direct-current component, in which the alternating signal is modified so that its mark-to-space ratio or direct-current component can be detected by simple comparison with reference signals. Various information is then transmitted over a line, and the operation of the stage that generates the alternating signal can also be monitored.

Abstract: The present invention relates to a process control monitoring system and method. The system and method uses current comparator circuits for monitoring process changes. Process sensitive current sources are compared with weighted reference current sources in a manner that each output of the current comparators demonstrates the inequality of the current sources. By setting the weighted reference current sources properly, the outputs of the current comparators may be used to locate the process corner of the fabricated integrated circuit.

Abstract: A threshold detecting device including a detecting stage having a first input supplied with a monitored voltage varying between a first and second value, a second input supplied with a reference voltage by a reference source stage, and an output supplying a logic signal indicating crossover of a predetermined threshold by the monitored voltage. Initially, the reference source stage is off and the reference voltage follows the course of the monitored voltage; upon the monitored voltage exceeding a first threshold value, the reference source is turned on and causes the reference voltage to rise more slowly than the monitored voltage, so that an increasing voltage difference is present between the first and second inputs of the reference stage; and, upon the voltage difference exceeding a second threshold value, the detecting stage switches and generates the threshold crossover signal.

Abstract: An improved burn-in sensing circuit for a semiconductor device generates a signal for indicating a start of a burn-in mode when an external voltage exceeds a predetermined level of a logic threshold voltage. The circuit obtains a desired hysteresis characteristic between a burn-in entry voltage and a burn-in exit voltage by lowering a level of the logic threshold voltage, and includes an external voltage sensor for dropping and outputting an external voltage in accordance with a bias voltage applied thereto. A burn-in signal generator of the circuit generates a predetermined level of a burn-in signal, and feeds back the predetermined level of a burn-in signal to lower the logic threshold voltage when a predetermined level of dropped voltage is higher than its logic threshold voltage.

Abstract: An apparatus and method for controlling a variable threshold signal conditioning circuit to condition a variable amplitude periodic input signal in response to the control signals received. A plurality of transistor circuits, each responsive to a control signal, are disposed in parallel with the positive feedback resistor of a trigger circuit. The transistor circuits are controlled to adjust the upper threshold levels of the trigger circuit in order to reduce the false triggering effects of noise in the input signal. The lower threshold level is held constant at the input signal mid-line voltage while the upper threshold level is varied over a plurality of preprogrammed values. A microprocessor determines the appropriate threshold level for the circuit by comparing the timing signal output of the signal conditioning circuit to preprogrammed values stored in the microprocessor memory.

Abstract: The subject of the invention is a monitoring circuit for at least one supply voltage, having comparators that generate a first report signal if the supply voltage is below a predeterminable threshold value and a second report signal after a fixed warning time elapses. The supply voltage is supplied in a first circuit unit (4) to a first comparator (7). The first comparator is followed by a switch element, with which a capacitor (19), connected parallel to it and chargeable from an operating voltage source, can be short-circuited in order to lower the input voltage of a second comparator (13), disposed in the control unit (4), to below a second reference voltage that defines a limit value for the resetting of the report signal.

Abstract: A comparator with hysteresis which has a bias current circuit, a differential input stage, and an output stage is disclosed. The differential input stage uses a parallel transistor and an enabling transistor connected in parallel to one of the differential pair transistors to create hysteresis. The parallel transistor and enabling transistor are used to generated an effective offset voltage which must be overcome for the comparator to switch states.

Abstract: A hysteresis generator for providing a comparator with a precision hysteresis reference input. An output of the comparator controls a switch which determines whether or not a reference current is applied to a resistor. The resistor is connected between a reference voltage and an input to the comparator. A buffer amplifier provides the reference voltage to the resistor. The reference current is taken from a second resistor connected between the output of the buffer amplifier and the input of a current mirror. The current mirror applies its output current to the first resistor. A diode may be inserted between the output of the buffer amplifier and the first resistor to make the hysteresis voltage generated by the current applied to the first resistor substantially temperature independent.

Abstract: A transferred data recovery apparatus capable of recovering transferred data from a transferred data signal has a first comparator for comparing transferred data signal with a reference level R to output binary-quantized data signal representing whether or not the transferred data signal is higher than the reference level R. A sample and hold circuit is driven by a clock signal and samples the binary quantized data signal each clock period to output sampled digital data to an averaging circuit. The averaging circuit sequentially averages a predetermined number of the sampled digital data each clock period to produced averaged outputs. A second comparing circuit digitally compares the averaged outputs against an upper reference level and a lower reference level dependent upon the direction of change to produce a recovered data output. The recovered data output goes low when the averaged output goes lower than the lower reference level and goes high when the averaged output goes above the upper reference level.

Abstract: The present invention provides an AD converter which operates at high speed with low power consumption and a magnetic recording/regenerating apparatus using it.The magnetic recording/regenerating apparatus has a current controller for switching the operating current of the comparator of the AD converter and an ADC controller for receiving an instruction of the conversion speed corresponding to the regenerating frequency. When the current controller receives an instruction for decreasing the conversion speed, it puts the operation state of the AD converter into the low power consumption state.