Abstract: The disclosure relates to detectors of the level of supply voltage in an integrated circuit. The disclosed detector is designed to detect the crossing of low levels of supply voltage. It comprises a first arm to define a first reference voltage and a second arm to define a second reference voltage, these two reference voltages varying differently as a function of the supply voltage and their curves of variation intersecting for a value of the supply voltage located close to a desired threshold. A comparator receives the two reference voltages. The first arm has a resistive divider bridge, an intermediate connector of which constitutes the first reference voltage. The second arm comprises a resistor series-connected with a native P type MOS transistor, the point of junction of this resistor and this transistor constituting the second reference voltage. A non-linear element may be parallel-connected to the resistor which constitutes the first reference voltage.

Abstract: An input receiver circuit which is capable of reducing a difference between a propagation time at the rise-up and that at the fall of an input signal and is suitably used for semiconductor memory devices. The input receiving circuit comprises a node, six N channel (N-ch) MOS transistors and two P channel (P-ch) MOS transistors. The first and second N-ch transistors receive an activation signal and have grounded sources. The third and fourth N-ch transistors receive the first and second signal and have sources connected to the drains of the first and second N-ch transistors, respectively. The fifth and sixth N-ch transistors have gates connected to the node and are provided in parallel to the third and fourth N-ch transistors, respectively. Sources of the first and second P-ch transistors are supplied with the power source voltage. Drains of the first and second P-ch transistors are connected to the drains of the third and fourth N-ch transistors, respectively.

Abstract: An input buffer for use in an integrated circuit having a V.sub.CC voltage supply and a V.sub.SS voltage supply. The input buffer includes a p-channel field effect transistor (FET) having a source region coupled to the V.sub.CC voltage supply, a drain region coupled to a bias circuit, and a gate electrode coupled to an input terminal. The bias circuit maintains a voltage at the drain region of the p-channel FET which is slightly greater than the V.sub.SS supply voltage when a logic high voltage is applied to the input terminal. In an alternate embodiment, the input buffer includes an n-channel FET having a drain region coupled to the V.sub.CC voltage supply, a source region coupled to the output terminal and a gate electrode coupled to the input terminal. The bias circuit maintains a voltage at the source of the n-channel FET which is greater than the V.sub.SS supply voltage when a logic low voltage is applied to the input terminal.

Abstract: Disclosed is a power-up detection circuit of a semiconductor device which generates an output signal enabling an activation of the semiconductor device to be maintained only when an internal power voltage is more than a predetermined voltage level. In the power-up detection circuit, a level detection section is provided for detecting a level of the internal power voltage to generate a first level detection signal when the internal power voltage is less than the predetermined voltage level and to generate a second level detection signal when the internal power voltage is not less than the predetermined voltage level. And, an output driver is provided for enabling the internal circuits to be at inactive state in response to the first level detection signal, and generating the output signal having the same waveform as the internal power voltage in response to the second level detection signal.

Abstract: A constant current source (1) is provided between a power supply (.sup.V CC) and an intermediate node (N1) and supplies a reference current (IR) which is a constant current between the power supply (.sup.V CC) and the intermediate node (N1). A variable resistor (2) is provided between the intermediate node (N1) and a comparison potential (VL) and its resistance value can be set to a desired value. A current flowing in the variable resistor (2) is a comparison current (IC). An amplifier (3) has an input connected to the intermediate node (N1) and amplifies a potential from the intermediate node (N1) to output a level detection signal (GE). Having this configuration, a potential detecting circuit which ensures a stable and controllable detection level is provided.

Abstract: A negative voltage detection circuit has a detection level of which is independent from the threshold voltage of a MOS transistor incorporated into the memory device. The negative voltage detection circuit detects whether or not the output voltage of a charge pump has a desired level, and then a signal is output in accordance with the detection result. The negative voltage detection circuit detects the negative voltage by comparing the multiple of the negative voltage by -(1/n) (n is a natural number) with a the positive inner reference voltage V.sub.ref. When the multiple and the reference voltage V.sub.ref are equal to each other, the negative voltage detection circuit determines that the negative voltage has the desired level. When the level of the output is lower than the desired level, the charge pump is stopped. Otherwise, a control signal is output to operate the charge pump so as to control the negative voltage at the desired level by the feed back control.

Abstract: The CMOS comparator has four p-channel lateral high-voltage transistors (T.sub.11 -T.sub.14) which form two first current mirrors, and two n-channel lateral high-voltage transistors (T.sub.31, T.sub.32) which form a second current mirror. In the current path of the reference voltage, there is a depletion type transistor (T.sub.2) which determines the current flowing there. If the input voltage (U.sub.IN) is equal to the reference voltage (U.sub.ref), then an equal current flows in both current paths. If the input voltage (U.sub.IN) deviates from the reference voltage (U.sub.ref), however, then the output voltage changes dramatically.

Abstract: This invention relates to a voltage comparator with an input for an analog signal and an output for a digital signal, comprising an inverter which has an input coupled to the comparator input and an output coupled to the comparator output, and comprising at least two MOS transistors coupled to each other, at least one of the two MOS transistors being of the floating gate type.

Abstract: A loop control detection circuit (100) is provided for detecting feedback values in a current feedback control loop to determine if the control loop is in or out of control.

Abstract: The disclosed substrate potential detecting circuit can reduce both the power consumption and the pattern area thereof. The substrate potential detecting circuit comprises: a series circuit composed of a plurality of same-conductivity type MOS transistors. Each transistor has a source terminal connected to a substrate terminal thereof and a drain terminal connected to a gate terminal thereof. Further, the channel widths of all the MOS transistors are determined equal to each other and so selected that all the transistors can be operative in a sub-threshold region, respectively.

Abstract: An output circuit for a semiconductor device that outputs an output voltage based on a received external signal. The output circuit has an interface that receives the external signal, and a comparing unit that compares the external signal with a plurality of predetermined threshold voltages. The comparing unit outputs a voltage driving signal based on the comparison results. Also, the output circuit has an output unit that outputs the output voltage based on the voltage driving signal from the comparing unit.

Abstract: For providing a high voltage detector circuit for discriminating whether a voltage supplied to an input terminal (1) is higher or not than a power supply thereof, stably independent of its power supply fluctuation or noises and without problem of gate oxide break because of high voltage; a high voltage detector circuit of the invention comprises: a MOS transistor (P1) with its gate connected to the power supply; a first resistor (R1) connected between a source of the MOS transistor and the input terminal; a second resistor (R2) connected between a drain of the MOS transistor and a ground; and an inverter for outputting inverse logic of a drain voltage of the MOS transistor to an output terminal (OUT).

Abstract: A voltage detecting circuit and method in a synchronous DRAM is disclosed. The circuit includes first and second pull-up switching portion, first and second pull-down switching portion, first and second pull-up portion, first and second pull-down portion, ; switching transistor and a driving portion. The pull-up and pull-down switching portion are selectively turned-on according to a mode control signal, and the current paths are different for the active power down mode and the normal mode. Each pull-up portion includes a plurality of NMOS transistors connected in series and gated by the boosted voltage and each pull-down portion includes a plurality of NMOS transistors connected in series. An effective channel length of the current path selected in case of the active power down mode is longer than that selected in case of the normal operation mode.

Abstract: A circuit arrangement is disclosed which detects a signal pauses in an audio signal, The audio signal is amplified, rectified, and then sent to a control unit. The control unit periodically sets the output of the rectifier to a predetermined level below a threshold level. The control unit then waits a predetermined period of time and determines whether the signal at the output of the rectifier has exceeded the threshold. If is does not, a signal pause has occurred.

Abstract: The present invention includes a first MOS transistor whose gate and drain are connected with a first node, a second MOS transistor whose gate and drain are connected with the first node and a third node, respectively, a first resistive element which is connected between the first node and a second node, a second resistive element which is connected between the second node and a ground voltage terminal, a first NOT circuit whose input terminal is connected with the second node, whose output terminal is a fourth node, and which is connected between the third node and the ground voltage terminal, and a second NOT circuit whose input terminal is connected with the fourth node and whose output terminal is a fifth node. Consequently, the present invention can detect voltage in a stable condition with low power consumption.

Abstract: An integrated comparator circuit includes a first terminal and a second terminal for an operating voltage. An input stage has two complementary MOSFETS having main current paths connected in series defining a common connecting point therebetween. The two MOSFETS have gate terminals connected to the common connecting point. The series circuit of the MOSFETS is connected between the first terminal and a third terminal. An inverter stage has two complementary MOSFETS having main current paths connected in series defining a common connecting point therebetween forming an output terminal. The two complementary MOSFETS have gate terminals connected to the common connecting point of the input stage. The second terminal and the third terminal receive an input signal of the comparator circuit. A fourth terminal is provided for application of a reference potential to determine a switching threshold of the comparator circuit.

Abstract: A threshold detector circuit (2) suitable for use with a nuclear event detector for sensing an ionising radiation pulse has a high tolerance to ambient temperature fluctuations. The threshold detector (2) comprises an amplifier stage (3) which includes a pair of complementary transistors (Q2, Q3) and a comparator stage (6) which includes a third transistor (Q4) and a voltage reference (7). Temperature compensation is achieved by the addition of a feedback loop (5) in the amplifier stage (3) including a fourth transistor (Q1) whose temperature coefficient is closely matched to that of the third transistor (Q4).

Abstract: A test mode circuit for an integrated circuit includes a high voltage detector having an input for receiving a high voltage signal, a Schmitt trigger having an input coupled to the output of the high voltage detector, a latch having an input coupled to the output of the Schmitt trigger and an output for providing a test mode signal in a test operational mode, and additional control circuitry for disabling the high voltage detector and Schmitt trigger so that substantially all of the active current flow in the high voltage detector and Schmitt trigger is eliminated in a normal operational mode. The test mode circuit further includes circuitry for preventing a reset condition in the latch during the test mode until a power-down condition occurs. A glitch filter is also included, which is interposed between the output of the Schmitt trigger and the input to the latch.

Abstract: The circuit, in accordance with the present invention is for detecting the presence at a signal input of a high voltage higher than a predetermined value and signaling it to a signal output through a logical type signal. The circuit comprises one or more first transistors of MOS type and of a predetermined conductivity type, each being diode-connected and having its body terminal connected to the source terminal, and having principal conduction paths connected in series for current conduction between a first node and a ground input. The circuit also includes two or more second transistors of the MOS type and of the same conductivity type, with each one being diode-connected and having its body terminal connected to the source terminal and having principal conduction paths connected in series for current conduction between the signal input and the first node.

Abstract: A level detection circuit for monitoring the level of a power supply voltage and producing an output signal at power on for resetting various system elements powered by the supply voltage when the supply voltage reaches a predetermined level. The detection circuit, which is powered by the supply voltage includes a voltage reference circuit which produces a reference voltage having a magnitude which is relatively independent of the power supply voltage. A translator circuit functions to produce a translated voltage indicative of the supply voltage magnitude and which is comparable in magnitude to the reference voltage when the supply voltage is at a suitable level such that the system will accept a power on reset pulse. A comparator circuit functions to compare the reference voltage with the translated voltage and cause an associated output circuit to issue the reset pulse. The reset circuit typically includes a one shot circuit, the output of which is logically ORed with the amplified comparator output.

Abstract: A constant current source (1) is provided between a power supply (VCC) and an intermediate node (N1) and supplies a reference current (IR) which is a constant current between the power supply (VCC) and the intermediate node (N1). A variable resistor (2) is provided between the intermediate node (N1) and a comparison potential (VL) and its resistance value can be set to a desired value. A current flowing in the variable resistor (2) is a comparison current (IC). An amplifier (3) has an input connected to the intermediate node (N1) and amplifies a potential from the intermediate node (N1) to output a level detection signal (GE). Having this configuration, a potential detecting circuit which ensures a stable and controllable detection level is provided.

Abstract: A comparator circuit includes a series circuit having a first MOSFET and a second MOSFET. An inverter has a third MOSFET and a fourth MOSFET. A node between the first and second MOSFETs is connected to a gate terminal of the fourth MOSFET. An input voltage is applied between ground and the second MOSFET. A series circuit of a fifth MOSFET and a Zener diode polarized in the blocking direction is connected parallel to the fourth MOSFET. A response threshold of the comparator circuit is defined by adjusting a resistance of the Zener diode occurring in the reverse direction. The resistance is adjusted through the use of a voltage pulse that can be applied to a terminal connected to a cathode of the Zener diode.

Abstract: A high voltage detection circuit implemented in an integrated circuit which is switchable between a normal operation mode and an alternative operation mode and having contact pads for electrically connecting the integrated circuit to an external environment. One of the pads functions to provide an interface between an external environment and the integrated circuit for signals having a maximum voltage magnitude, relative to a circuit common, when the integrated circuit is in the normal operation mode. The one pad further functions to receive an external test mode signal which will cause the integrated circuit to switch to the test mode of operation, with the test mode signal having a voltage magnitude which is greater than that of maximum voltage magnitude. The detection circuit includes a first MOS transistor having either the gate or source coupled to the one pad and a second MOS transistor having a source and drain connected in series with the drain and source of the first transistor.

Abstract: The temperature of a power semiconductor component is monitored by feeding the block current of a bipolar transistor which is in thermal contact with the component to an amplifying current mirror. The output signal of the current mirror is compared with a reference current. If the mirrored current is greater than the reference current, then the system produces a corresponding output. Temperatures of the power semiconductor component below 140.degree. C. can be reliably detected.

Abstract: A substrate clamp for non-isolated integrated circuits is disclosed. The substrate clamp comprises a circuit that controls the voltage on a substrate so that the substrate is connected to a specific node if the parasitic PN diodes at all the circuit nodes are not forward biased. If a specific node is then forced with an applied voltage to forward bias, the substrate is disconnected from its original node and maintains itself at a forward biased diode voltage drop away from the powered node. Various embodiments are disclosed. In one embodiment of the invention, a set of bipolar transistors which utilize the substrate as a common base, is implemented. The emitters of these transistors are connected to a set of nodes which may be driven to voltages outside the range between that provided by the power supply and ground, or any other pair of applied voltages. The collectors of these bipolar transistors are connected together.

Abstract: An overcurrent detector circuit (21) for a power MOSFET (22) is described. The overcurrent detector circuit (21) generates a bias voltage corresponding to the drain to source voltage of the power MOSFET (22). The drain to source voltage correlates directly to the current being conducted by the power MOSFET (22). An overcurrent condition occurs when the power MOSFET (22) exceeds a predetermined current. The bias voltage is applied to a transistor (24) for generating a current. A current source (29) couples to the transistor (24). The current provided by the transistor equals the reference current of the current source (29) when the power MOSFET conducts the predetermined current. The overcurrent detector circuit (21) generates a signal indicating a overcurrent condition does not exist when the reference current is greater the current provided by the transistor.

Abstract: A circuit to detect the crossing of at least one voltage threshold by an input voltage of an integrated circuit has two arms mounted in negative feedback configuration, each comprising a forward biased diode in series with a current generator. The current generator of an arm is controlled in voltage by the other arm. An inverter calibrated to detect a crossing of a given threshold is connected at input to the connection point between the diode and the generator of one of the arms.

Abstract: A level detection circuit for monitoring the level of a power supply voltage and producing an output signal at power on for resetting various system elements powered by the supply voltage when the supply voltage reaches a predetermined level. The detection circuit, which is powered by the supply voltage includes a voltage reference circuit which produces a reference voltage having a magnitude which is relatively independent of the power supply voltage. A translator circuit functions to produce a translated voltage indicative of the supply voltage magnitude and which is comparable in magnitude to the reference voltage when the supply voltage is at a suitable level such that the system will accept a power on reset pulse. A comparator circuit functions to compare the reference voltage with the translated voltage and cause an associated output circuit to issue the reset pulse. The reset circuit typically includes a one shot circuit, the output of which is logically ORed with the amplified comparator output.

Abstract: A voltage detector for determining the high or low status of a power supply output voltage, including a front-end detector and an inverting amplifier. The front-end detector includes a number of NMOS and PMOS transistors which constitute active loads. The voltage detector is inherently independent of device fabrication condition changes, as well as on the temperature variations.

Abstract: A memory cell system is disclosed with properties of asymmetrical operation such that the occurrence of memory error due to certain environmental disturbances is detectable. The asymmetry of operation can be adjusted to set the level at which the disturbance is detected. Detection of memory error in the system can be used to shut off access to an associated memory array in order to prevent error in the array.

Abstract: An address transition detector circuit according to the present invention comprises an input terminal, a one-shot pulse generator circuit having an input electrically connected to the input terminal, a first switching device electrically connected between a first and second nodes and brought into a conducting state in response to a one-shot pulse output from the one-shot pulse generator circuit, a second switching device electrically connected between a ground potential node and the second node and driven in response to a signal input to the input terminal, a plurality of switching devices parallel-connected between the first and second nodes and respectively driven in response to a plurality of address transition one-shot pulse signals, and power source potential supplying means for supplying a power source potential to the first node.

Abstract: An improved power-on reset circuit is provided for controlling reset signal transition until after the power supply has achieved operational levels. Specifically, the reset signal is designated to transition from a high to a low state after the power supply exceeds a fixed reference voltage. The reference voltage is set at a voltage value greater than the operational voltage level of devices within a load circuit connected to the output of the power-on reset circuit. The power-on reset circuit includes numerous subcircuits used to define the reference voltage, trigger the reference voltage in relation to the power supply voltage, delay the triggered voltage, and buffer the delayed, triggered voltage to a reset value capable of driving load circuit impedances.

Abstract: A circuit (10) for enhancing logic transitions appearing on a line (34) has been provided. The circuit includes a first comparator (14) for sensing when a voltage on the line exceeds a first level and subsequently pulling the voltage on the line to a first predetermined voltage. The circuit also includes a second comparator (12) for sensing when the voltage on the line falls below a second level and subsequently pulling the voltage on the line to a second predetermined voltage.

Abstract: A semiconductor integrated circuit comprises an input signal terminal to which an input signal is supplied from an outer unit, a plurality of input voltage sensing circuits each having a different circuit threshold value and connected to the input signal terminal, for sensing whether a voltage of the input signal is higher or lower than a predetermined normal level, a power supply voltage sensing circuit for sensing whether a power supply voltage applied from another outer unit is a normal power supply voltage or a voltage different from the normal power supply voltage, a selection circuit for selecting a corresponding one from a plurality of the input voltage sensing circuits in accordance with an output of the power supply sensing circuit, and an internal circuit to which an output of a selected one of the input voltage sensing circuits is connected.

Abstract: In a semiconductor circuit device comprising a differential amplifier circuit, which is formed on a semiconductor substrate and which comprises first and second input terminals, and a circuit element formed on the semiconductor substrate and connected to one of the first and the second input terminals. A dummy circuit element is formed on the semiconductor substrate so as to adjoin the circuit element for forming between the dummy circuit element and the semiconductor substrate a dummy parasitic capacitor which is equivalent to a parasitic capacitor formed between the circuit element and the semiconductor substrate. The dummy circuit element is connected to another one of the first and the second input terminals.

Abstract: Voltage levels of an external bus are sampled with results stored to adjust both an output driver and input receiver. The resulting logic signal levels for the input/output (I/O) interface are maintained within acceptable ranges of the standard I/O signal levels.

Abstract: An address transition detector circuit according to the present invention comprises an input terminal, a one-shot pulse generator circuit having an input electrically connected to the input terminal, a first switching device electrically connected between a first and second nodes and brought into a conducting state in response to a one-shot pulse output from the one-shot pulse generator circuit, a second switching device electrically connected between a ground potential node and the second node and driven in response to a signal input to the input terminal, a plurality of switching devices parallel-connected between the first and second nodes and respectively driven in response to a plurality of address transition one-shot pulse signals, and power source potential supplying means for supplying a power source potential to the first node.

Abstract: A circuit for the detection of a high threshold supply voltage comprising a voltage divider and an inverter. The voltage divider is formed by a reverse-biased voltage breakdown device, such as a Zener diode, and a resistive element, such as a forward-biased transistor or a resistor. The use of the reverse-biased voltage breakdown device in the divider makes the detection threshold voltage (Vo) of the circuit stable and precise even with variations in threshold voltages due to temperature and manufacturing process variations.