Abstract: The power transistor circuit with high-voltage endurance includes a first power transistor, a second power transistor and an enabling circuit. The first power transistor includes a first voltage endurance and a first inner resistance, while the second power transistor includes a second voltage endurance and a second inner resistance. The first voltage endurance and the first inner resistance are smaller than the second voltage endurance and the second inner resistance, respectively. The drain of the second power transistor is connected to the drain of the first power transistor and the enabling circuit. The enabling circuit enables the second power transistor first, and when the drain voltage of the first power transistor is smaller than the first endurance, the enabling circuit then enables the first power transistor.

Abstract: A semiconductor apparatus is disclosed, including: multiple parallel monitor circuits each configured to control charge to a capacitor by controlling a transistor that bypasses, if the voltage of the capacitor exceeds a predetermined reference voltage, charge current provided to the capacitor. The semiconductor apparatus further includes high voltage side IC connection output terminals each connected to an open drain of N channel transistor; high voltage side IC connection input terminals each connected to a terminal of a high resistance component and to an inverter input terminal; low voltage side IC connection output terminal each connected to an open drain of P channel transistor; and low voltage side IC connection input terminal each connected to a terminal of a high resistance component and to an inverter input terminal.

Abstract: A voltage detection and sequencing circuit is provided, preferably on a single semiconductor chip, for applying a plurality of voltages to an electrical system in a predetermined sequence. The circuit includes a plurality of subsystems each adapted to detect one of a plurality of supply voltages at an input terminal and to supply the supply voltage to at least one output terminal in a predetermined sequence as controlled by a sequencing means.

Abstract: An apparatus comprising a first comparator circuit, a second comparator circuit, a third comparator circuit, and a difference circuit. The first comparator circuit may be configured to generate a first intermediate current in response to a first input voltage and a second input voltage. The second comparator circuit may be configured to generate a second intermediate current in response to the first input voltage and the second input voltage. The third comparator circuit may be configured to generate an intermediate reference current in response to a first reference voltage and a second reference voltage. The difference circuit may be configured to generate a first compare voltage and a second compare voltage in response to the first intermediate current, the second intermediate current, and the intermediate reference current. The apparatus may indicate a squelch condition when the first compare voltage is greater than the second compare voltage.

Abstract: Supply voltage level detectors are disclosed. The supply voltage level detector comprises a voltage source divider dividing a voltage source to generate a detection voltage, a bandgap reference voltage generator, a comparator comparing the detection voltage with a bandgap reference voltage generated by the bandgap reference voltage generator to determine if the voltage source is ready, a control circuit, and a forcing circuit. To ensure reliability of the comparison result, the control circuit disables the comparing device until the bandgap reference voltage is available. The forcing circuit is coupled to the output terminal of the comparing device and is controlled by the control circuit. When the comparing device is disabled, the forcing circuit forces the voltage level of the output terminal of the comparing device to a specific value indicating the voltage source is unready.

Abstract: An analog output buffer circuit is provided. A first transistor has a source, drain, and gate coupled to a first node, a second node, and a third node, respectively. A second transistor is coupled between the second node and the third node. The second transistor has a gate coupled to a first control line. A third transistor has a source coupled to a data line, a drain coupled to the first node, and a gate coupled to the first control line. A fourth transistor has a source coupled to the second node, a drain coupled to an output terminal, and a gate coupled to a second control line. A fifth transistor has a source coupled to the first node, a drain coupled to a first power supply, and a gate coupled to the second control line. A capacitor is coupled between the third node and the first power supply.

Abstract: Provided is a demodulator circuit allowing a tag or transponder to efficiently recover data of an input amplitude signal at very low power in a wireless communication system such as a radio frequency identification (RFID) system. The demodulator connects an output of a voltage multiplier to a low-current path by capacitive coupling, thereby recovering data. Therefore, data is recovered, at low power, from an input amplitude signal having a low modulation depth, and it is possible to increase a communication distance.

Abstract: A low voltage detection circuit includes a reference voltage generation circuit, a divider circuit, a comparator that serves as a comparison circuit, and a second constant current transistor connected in series with the divider circuit. An auxiliary current transistor as well as a first constant current transistor is connected in series with a load element. The auxiliary current transistor is controlled by a voltage at a drain of the second constant current transistor. A gate of the second constant current transistor and a gate of the first constant current transistor are connected with each other to form a current mirror. A size of the second constant current transistor is adjusted so that the second constant current transistor can provide a second constant current that is several times larger than a first constant current provided by the first constant current transistor.

Abstract: The invention relates to a sense amplifier comprising the following element: a first current mirror unit coupled to a high voltage source, outputting a first current and a second current according to a first reference current, wherein the second current is twice the first current; a second current mirror unit coupled to a high voltage source, outputting a third current according to a second reference current; a first impedor coupled to the second current and a low voltage source; a second impedor coupled to the third current and a low voltage source; a third current mirror coupled to the first, second and third currents, and the first current is regarded as the reference current of the third current mirror unit, thus, the current which flows through the first impedor is the first current, and the current which flows through the second impedor is a fourth current.

Abstract: An output signal cutting-off circuit includes a first switching element, a driving circuit and a voltage-drop-signal generating circuit. When a voltage to be monitored becomes lower than a threshold voltage, a voltage-drop-signal is generated and supplied to the driving circuit. The driving circuit turns on the first switching element based on the voltage-drop-signal to thereby cut off an output signal voltage by bringing it to a ground potential. When the voltage-drop-signal disappears, the first switching element is turned off to bring the output signal to a normal state. Preferably, a second switching element for charging a capacitor and a third switching element for discharging the capacitor are used in the driving circuit. In this case, the first switching element is turned on or off based on a voltage of the capacitor.

Abstract: The signal detection circuit of the present invention includes: a comparison section for comparing the absolute value of a voltage of an input differential signal with a threshold voltage corresponding to a first detection level adjustment signal to detect presence/absence of an input signal and outputting a detection signal indicating the detection result; a threshold adjustment control section for generating the first detection level adjustment signal in response to the detection signal and outputting the generated signal; and a detection section for detecting whether or not the level of the detection signal changes repeatedly.

Abstract: A voltage (UE1, UE2), other than a supply voltage (UV1, UV2), is monitored and controlled to avoid damage to circuit components by maintaining a required voltage level. Dissipation power losses are reduced by switching off a monitoring circuit when monitoring is not required. For this purpose a stepped down voltage is derived from the voltage to be monitored at a tap (N1) of a voltage divider connected between ground potential and the voltage to be monitored. The derived voltage is then evaluated, for example by comparing with a reference voltage. A controllable switch is connected in series with two voltage divider elements. The switch is controlled to open for switching off the voltage divider when monitoring is not needed. The switch is closed to activate the voltage divider when monitoring is needed.

Abstract: Apparatus and methods are described for providing an adaptive trip point detector circuit that receives an input signal at an input signal node and generates an output signal at an output signal node, the output signal changing from a first value to a second value when the input signal exceeds a trip point reference value. In particular, the trip point reference value is adjusted to compensate for variations in process or temperature, without requiring an externally-supplied reference signal.

Abstract: A circuit for adaptively adjusting the drive strength of output power transistors in a class D amplifier is provided. The circuit includes a driver circuit and a low-voltage detect circuit. The low-voltage detect circuit is arranged to assert a low-voltage detect signal if a low supply voltage condition is detected. The driver circuit is arranged to increase the drive strength if the low-voltage detect signal is asserted. The driver circuit includes a first driver and a second driver. The second driver is enabled if the low-voltage detect signal is asserted, and disabled if the low-voltage detect signal is unasserted.

Abstract: A voltage detection circuit, comprises a constant-current circuit, a current mirror circuit operated by the constant-current circuit, at least one diode-connected first transistor disposed between an output of the current mirror circuit and a detected voltage, and an output circuit outputting one logic voltage in response to a turn-on of the first transistor when the detected voltage is a predetermined voltage or higher, and outputting the other logic voltage in response to a turn-off of the first transistor when the detected voltage is lower than the predetermined voltage.

Abstract: A comparator includes a sampling capacitor, a first switching unit which is connected to an input end of the sampling capacitor and which applies an input signal to the input end of the sampling capacitor, a second switching unit which is connected to the input end of the sampling capacitor and which applies a reference signal to the input end of the sampling capacitor, an output transistor connected to an output end of the sampling capacitor in a source follower connection manner or an emitter follower connection manner, and a third switching unit which is connected to an output end of the sampling capacitor and which maintains maintaining a voltage at the output end of the sampling capacitor to be constant. The input signal is compared with the reference signal.

Abstract: A semiconductor integrated circuit includes a first circuit and a second circuit having a breakdown voltage higher than that of the first circuit. Operation voltages of the first and second circuits can be made equal to or different from each other. The second circuit has a level shift circuit for shifting the level of an output signal of the first circuit in accordance with an operation voltage of the second circuit, an external output buffer having an input that can receive, selectively, an output signal of the level shift circuit or an input signal that bypasses the level shift circuit. When the first and second circuits operate with a low voltage, bypass is selected. In high-voltage operation and burn-in, the level shift circuit is selected.

Abstract: A switching point detection circuit for detecting a switching point according to a fabrication condition of a MOS transistor includes a reference voltage generation circuit for generating a reference voltage, a first CMOS inverter circuit for receiving the reference voltage, and a second CMOS inverter circuit for receiving the reference voltage, wherein an NMOS transistor is a dominant transistor for the reference voltage in the first CMOS inverter circuit and a PMOS transistor is a dominant transistor for the reference voltage in the second CMOS inverter circuit.

Abstract: A method for detecting a failure in a radio frequency (RF) device (200) that includes a transistor (210) having a first terminal at an RF input (220), a second terminal at an RF output (260), and a third terminal at an RF common (230). The method includes the steps of: detecting a first voltage at the first terminal; comparing the first voltage to a reference voltage; and determining whether the RF transistor (210) is operating in a normal state or a failed state as a function of whether the first voltage falls inside or outside of a predetermined threshold value of the reference voltage.

Abstract: A control arrangement and method is provided that monitors the condition and operating parameters of a power electronic system having power electronic devices and responds to various detected abnormalities via appropriate action to optimize operation of the power electronic system. The arrangement increases reliability of operation and optimizes the continuous supply of power to a load For example, the arrangement responds to an overheated or shorted power electronic switch by switching to an alternate power electronic switch, the overheated power electronic switch being made available as a temporary alternate path. The arrangement also includes the capability for diagnosing the power electronic switches by detecting whether or not any switch is shorted in the series-connected stack of switch stages.

Abstract: A voltage level detection circuit (1) with a threshold level, which is dependent on the manufacturing process. The circuit comprises a first current generator (4), which generates a monitoring current (IM) derived from the voltage (VM) to be monitored. This monitoring current (IM) is compared with a reference current (Iref1). A switchable reference current (Iref2) provides for hysteresis. The first current generator (4) comprises an element, the resistance of which depends on the manufacturing process.

Abstract: Charging a storage cell requires the electromotive force exerted at a photogenerating cell in addition to the voltage equal to or higher than the forward on voltage developed at an backflow preventing diode. Therefore, the charging is inefficient. Moreover, the area of the backflow preventing diode must be large in consideration for a current supply from the photogenerating cell at a high intensity of illumination. A charging circuit, constructed using a differential amplifier, which has a power supply therefor separated from another power supply, is used as a direction-of-current detecting circuit that detects the direction of current from a voltage difference between two different power supplies. Consequently, a switch is logically turned on or off depending on whether charging or non-charging is under way. Thus, on voltage to be developed during charging is lowered. Moreover, the size or area of a transistor that acts as a logical circuit is made smaller than that of the backflow preventing diode.

Abstract: Within one embodiment, a voltage detector circuit detects whether a voltage supply (e.g., VDD) is in a high or low range and generates a logic output. Using this logic output, a variable RC (resistor capacitor) VDD filter may be implemented such that at high VDD the amount of resistance is increased, thereby increasing the decoupling on the VDD line and reducing the size of current spikes on VDD. This is particularly useful in circuits that function over a wide range of VDD supply. The voltage detector circuit can also be used in other embodiments as well. For example, the voltage detector circuit may be used to change the drive strength (e.g., effective W/L) of an output driver such that more drive is provided at low VDD and less at high VDD thereby having the effect of reducing rise/fall time variation and reducing the size of current spikes at high VDD.

Abstract: A VBB control circuit includes an intermediate potential generation circuit receiving a substrate potential VBB which is a negative potential and outputting a divided potential between a power supply potential INTVDD and a ground potential, and an inverter receiving the divided potential and determining whether the substrate potential is higher or lower than a desired value. A logic threshold value of the inverter is (½)×INTVDD. If a relationship of VBB=VREFB−(½)×INTVDD is satisfied, the divided potential accurately becomes (½)×INTVDD. Thereby, it is possible to realize a semiconductor device including a detection circuit which can arbitrarily select a detected potential of the VBB by changing VREFB and which is less influenced by a change in manufacturing conditions.

Abstract: The present invention realizes higher-speed external output operation synchronized with a clock signal from the viewpoint of prevention of output operation delay due to a level shift circuit and maintenance of a high breakdown voltage of an output buffer. A semiconductor integrated circuit includes a first circuit and a second circuit having a breakdown voltage higher than a breakdown voltage of the first circuit, and operation voltages of the first and second circuits can be made equal to each other or different from each other.

Abstract: A low voltage detecting circuit includes a first transistor having a first electrode electrically coupled to a reference voltage, a control electrode electrically coupled to the input power voltage, and a second electrode. The low voltage detecting circuit also has a second transistor having a first electrode electrically coupled to a logic high voltage, a control electrode electrically coupled to the second electrode of the first transistor, and a second electrode electrically coupled to a logic low voltage. When the input power voltage drops below the predetermined voltage, the voltage at the control electrode of the first transistor drops below the reference voltage to turn on the first transistor and consequently the second transistor so that a logic low signal is output from the first electrode of the second transistor.

Abstract: The present invention relates to a supply voltage level detector. The supply voltage level detector includes a reference voltage generator for generating the reference voltage of a constant level depending on a control signal, a compare voltage generator for generating a compare voltage the variation ratio of which is higher than the supply voltage supplied from the outside depending on the control signal, and a comparator for comparing the reference voltage and the compare voltage depending on the control signal to output a given signal. The present invention constructs the compare voltage generator in the supply voltage level detector so that the variation of the compare voltage depending on the variation of the supply voltage becomes great. Therefore, the present invention can improve the sensing margin of the comparator for sensing the difference between the reference voltage and the compare voltage. Also, the present invention can prevent erroneous operation by a noise to accomplish a stable operation.

Abstract: A negative supply, low-voltage supply fault detection circuit is implemented without the need for a current mirror thereby providing for the elimination of inaccuracies generally associated with a current mirror, and resulting in less power consumption when compared with known negative supply, low-voltage detection circuits that employ a current mirror and associated support circuitry.

Abstract: In an integrated circuit, a detection device detects a drop in the supply voltage of the core of the integrated circuit or an excessively slow build-up of this voltage with respect to a supply voltage of the input/output interface circuits of the integrated circuit. Outputs of the interface circuits are set to a high impedance state by the detection device to minimize their power consumption.

Abstract: A level shift circuit for shifting an input voltage to an output voltage is provided. The level shift circuit includes at least a complementary metal oxide semiconductor (CMOS) transistor formed on a p-substrate. The CMOS transistor has a PMOS transistor and an NMOS transistor. The NMOS transistor includes a gate electrode, a drain electrode having an n-well formed on the p-substrate and a first n-doped region formed inside the n-well, and a source electrode having a second N-doped region formed on the p-substrate.

Abstract: A multi-input logic circuit (e.g. a 2-input NAND circuit) mounted on a semiconductor integrated circuit comprises a plurality of voltage-activated transistors which have the same channel conduction type and are electrically connected in series between a power supply terminal and an output terminal. A source region and a body region of at least the voltage-activated transistor connected to the output terminal are electrically connected and have substantially the same potential. The semiconductor integrated circuit has either an SOI or SOS structure.

Abstract: An analog-to-digital converter includes a plurality of comparators that each have an output, two analog data inputs coupled to a differential analog data input, and two reference voltage inputs. The two reference voltage inputs are each coupled to a resistor ladder that contains a plurality of resistors coupled in series. Importantly, the two reference voltage inputs of each comparator are positively biased, meaning that the positive reference voltage input is coupled to a point on the resistor ladder at a relatively higher potential than the negative reference voltage input. The outputs of the comparators are coupled to an encoder that encodes signals at the outputs into a digital signal. By positively biasing the differential reference voltage inputs of the comparators in this manner, the differential gain, dynamic voltage range, and voltage symmetry of the comparators are advantageously improved.

Abstract: A determining circuit comprises an input section having a P-channel type MOS transistor applied with a voltage VT set based on a reference voltage applied to a gate electrode and a voltage according to a voltage of a terminal applied to a source electrode, and an output section with a voltage level that changes according to an output from a drain electrode of a P-channel-type MOS transistor of a voltage level that changes according to a further voltage. With this configuration, the determining circuit for determining switching over to a prescribed mode can be implemented which is not influenced by fluctuations in process factors by using the voltage outputted from the output section.

Abstract: A device for detecting the application of a high voltage signal to an internal node of an integrated circuit includes a high-voltage divider circuit and a threshold detection circuit. The threshold detection circuit receives a signal given by the output of the divider circuit, and provides a threshold crossing detection signal at an output thereof based upon the signal crossing a threshold. The detection circuit is connected between the logic supply voltage and ground, and further includes a negative feedback loop. The negative feedback loop is connected to the output of the divider circuit to limit the voltage build-up of the high voltage signal at the output thereof after the crossing of the detection threshold by the signal.

Abstract: In a semiconductor integral circuit having a transistor or an inverter, a leak current of the transistor or a through current of the inverter, respectively, or the like is reduced. The semiconductor integral circuit has an analog circuit which changes linearly the voltage of an input signal and causes the amount of a current flowing through the analog circuit to change in accordance with the change in the voltage of the input signal. The semiconductor integral circuit also has a logic circuit to which an input signal having a first or second voltage is input. This logic circuit outputs an output signal having the first or second voltage in response to the first or second voltage of the input signal. The absolute value of the threshold value of the MOS transistor of the analog circuit is set smaller than the absolute value of the threshold value of the MOS transistor of the logic circuit.

Abstract: A low voltage reset circuit device without being influenced by temperature and manufacturing process is formed by a first low voltage reset circuit using an energy gap circuit to generate a reference voltage, and a second low voltage reset circuit using a threshold voltage of a MOS transistor as a reference voltage. The first low voltage reset circuit is used to provide an accurate low voltage reset property,. while the circuit only works as VDD>1.2V. When VDD<1.2V, the second low voltage reset circuit still works normally for providing the desired reset signal thereby covering the low VDD voltage range.

Abstract: The disclosure relates to detectors of the level of supply voltage in an integrated circuit. The disclosed detector is designed to detect the crossing of low levels of supply voltage. It comprises a first arm to define a first reference voltage and a second arm to define a second reference voltage, these two reference voltages varying differently as a function of the supply voltage and their curves of variation intersecting for a value of the supply voltage located close to a desired threshold. A comparator receives the two reference voltages. The first arm has a resistive divider bridge, an intermediate connector of which constitutes the first reference voltage. The second arm comprises a resistor series-connected with a native P type MOS transistor, the point of junction of this resistor and this transistor constituting the second reference voltage. A non-linear element may be parallel-connected to the resistor which constitutes the first reference voltage.

Abstract: An input interface circuit which can be used whether the power supply potential is 5 volts or 3 volts. The input interface circuit includes a comparator, a detector and a controller. The comparator compares a potential level of a signal input from a signal input terminal with a predetermined threshold value, and outputs the comparison result from a signal output terminal. The detector detects whether the power supply potential to be supplied to the comparator is 5 volts or 3 volts. The controller changes the threshold value of the comparator when the detection result of the detector is 3 volts, but does not when the detection result is 5 volts. Therefore, the input interface circuit can be operated with an optimum threshold value, whether the power supply potential is 5 volts or 3 volts.

Abstract: A voltage level converter circuit includes a first node, a second node having a voltage according to an input voltage, a P channel MOS transistor connected between the second node and the first node, turned on when the input voltage attains an L level, a third node to which a first voltage is supplied, a first N channel MOS transistor connected between the third node and a fourth node, turned on when the input voltage attains an H level, a second N channel MOS transistor connected between the first node and the fourth node, and having a gate to which an alleviate signal is supplied, a third N channel MOS transistor, and a level determination circuit for providing an alleviate signal according to the level of the first voltage.

Abstract: Input and output buffer circuitry (12, 14, 16) is provided which are compatible with busses operating at different voltage levels. The buffer circuitry is self-configuring based on the type of bus to which it is coupled. The buffer circuitry includes voltage level detect circuitry (20) and pad level detect circuitry (28) which can reconfigure driver (34, 54) and level shifter circuits (24, 26) in order to protect the switching devices of the buffers.

Abstract: A resistance element and an N channel MOS transistor are connected in series between an output terminal of a voltage generation circuit in a flash memory and a line of a ground potential. A constant current is conducted to the MOS transistor, and the potential of the drain of the N channel MOS transistor is compared with a reference potential by a comparator. The voltage conversion factor becomes 1, so that the voltage detection accuracy is improved.

Abstract: A device for detecting the application of a high voltage signal to an internal node of an integrated circuit includes a high-voltage divider circuit and a threshold detection circuit. The threshold detection circuit receives a signal given by the output of the divider circuit, and provides a threshold crossing detection signal at an output thereof based upon the signal crossing a threshold. The detection circuit is connected between the logic supply voltage and ground, and further includes a negative feedback loop. The negative feedback loop is connected to the output of the divider circuit to limit the voltage build-up of the high voltage signal at the output thereof after the crossing of the detection threshold by the signal.

Abstract: A voltage level detection circuit (1) with a threshold level which is dependent on the manufacturing process. The circuit comprises a first current generator (4) which generates a monitoring current (IM) derived from the voltage (VM) to be monitored. This monitoring current (IM) is compared with a reference current (Iref1). A switchable reference current (Iref2) provides for hysteresis.

Abstract: An internal circuit of a semiconductor integrated circuit includes an inverter inputted with an input signal and is supplied with a power supply voltage during normal operation. The input terminal and the internal circuit are connected by a signal line having a resistor. A voltage determining circuit for determining whether a voltage of an input signal inputted to the input terminal is a signal voltage for use in the normal operation of the internal circuit or a high voltage for setting up an internal circuit test mode is connected to a node of the signal line. P-type MOS transistors are connected in series across a node of the signal line and the power supply voltage. The source of a first one of the P-type MOS transistors is connected to the power supply voltage together with the gate electrode and the substrate, and the drain is connected to the drain of the other P-type MOS transistor.

Abstract: A three-valued switching circuit having one control input terminal and one output terminal and including at least two transistors constituting a differential pair, and one constant current source connected to a common emitter terminal of the at least two transistors, in which a collector of one of said at least two transistors is connected to said output terminal to output three kinds of current values from said output terminal in response to a three-valued logic control signal applied to said control input terminal.

Abstract: A power supply voltage detecting circuit includes: a depletion MOS transistor having its source and gate connected to the base thereof; and an enhancement MOS transistor which is serially connected to the depletion MOS transistor, which has its source connected to its base, and which is fed an output of the voltage divider through its gate. Therefore, the production yield can be greatly improved, and the production costs can be greatly reduced.

Abstract: Current measuring device which comprises a current sense resistor (2) for generating a voltage proportional to the current to be measured. The voltage is measured by a MOS transistor (4) having its gate terminal connected to a first terminal of the current sense resistor, and having its source terminal connected to a second terminal of the current sense resistor. The drain current of the MOS transistor is coupled via a current coupling device to the source terminal of a further MOS transistor (10) having its gate and source terminals interconnected. The drain current of the MOS transistor causes a voltage across the further MOS transistor which is proportional to the current in the current sense resistor. This is true only if the voltage across the current sense resistor exceeds the threshold voltage of the MOS transistor. By introducing an offset source (6, 8), an output voltage is obtained which is proportional to the current to be measured for all current values as long as the MOS transistor is conducting.

Abstract: A current-switching method and circuit is provided for use with digital-to-analog converters (DACs) to provide improved compliance and linearity in the output current characteristic. In the current-switching circuit, an additional transistor that is set to a permanently-on state is connected at the output port of the current-switching circuit, which can help increase the output impedance of the current-switching circuit. Moreover, the problem of simultaneous switching-off of two control transistors can be eliminated by connecting the gate of one transistor to a reference voltage whose magnitude is set between the logic-high and logic-low voltage states of the input digital signal. The current-switching method and circuit can therefore meet the requirements of 3 V working voltage with 1.2 V output compliance and the requirements of 10 bits linearity in the output current characteristic.

Abstract: In a power amplifier comprising a plurality of cascaded field effect transistors (FETs), a power sensing circuit for sensing the output power of the power amplifier comprising a FET device operative in a first linear mode and second saturated mode of operation, the FET having source, gate and drain electrodes; and a low value resistor connected between the source electrode and a reference potential for generating a voltage drop between the source and the reference potential such that when the FET operates in the saturation mode, the voltage drop is indicative of the output power of the power amplifier.

Abstract: A variable threshold comparator receiving, on an input node, an input signal having a voltage, and providing an output signal on an output node when the voltage of the input signal exceeds a selectable threshold voltage of the comparator. The comparator includes a transistor coupled by way of its source and drain between a power supply and an output node, and having its gate coupled to the input node. Also included are a plurality of pairs of transistors coupled together by a source of a first one of the pair of transistors and drain a drain of a second one of the pair of transistors, and coupled in series between the output node and a ground, a gate of the first one of the transistors coupled to the input node, and a gate of the second one of the transistors coupled to a control signal specific to the second one of the transistors. The threshold voltage of the comparator is selectable by the application of one or more of the control signals to a respective one or more of the second ones of said transistors.