Abstract: A method of forming a resistor circuit, the method comprising forming a first resistor comprising a first type of resistor, forming a second resistor comprising a second type of resistor, the first type of resistor being different from the second type of resistor and simultaneously doping a first part of the first resistor and a second part of the second resistor, the first resistor and the second resistor being configured such that doping of the first part of the first resistor and the second part of the second resistor defines a temperature coefficient of the first resistor and a temperature coefficient of the second resistor, wherein the temperature coefficient of the first resistor and the temperature coefficient of the second resistor have opposite signs.

Abstract: A comparator having: a first transistor coupled to a first input terminal; a first current source coupled to the first transistor; a second transistor coupled to a second input terminal and coupled to the first current source; a third transistor coupled in series with the first transistor; a fourth transistor coupled in series with the second transistor; a fifth transistor coupled in series with the first transistor; a sixth transistor coupled in series with the second transistor; a seventh transistor coupled to the first input terminal and coupled as a source follower to the fifth transistor; and an eighth transistor coupled to the second input terminal and coupled as a source follower to the sixth transistor. The comparator also including a differential amplifier coupled to the first output terminal and coupled to the second output terminal.

Abstract: A semiconductor device includes an initial buffer signal generation circuit and a buffer signal generation circuit. The initial buffer signal generation circuit includes an initial buffer circuit which is activated if an initialization operation terminates. The initial buffer signal generation circuit generates an initial buffer signal from an external control signal in response to a first reference voltage signal. The buffer signal generation circuit includes a buffer circuit which is activated in response to the initial buffer signal. The buffer signal generation circuit generates a buffer signal from the external control signal in response to a second reference voltage signal.

Abstract: An apparatus for estimating a battery life includes a battery monitor configured to monitor an output signal from a battery; a steady state detector configured to detect a first steady state in which the output signal stays in a steady state and a second steady state differing from the first steady state; and an estimator configured to estimate a battery life from a variation of the output signal in a transient state in which the output signal transitions from the first steady state to the second steady state.

Abstract: A digital interface system that includes a first circuit that transmits a set of voltage levels and a second circuit that receives the set of voltage levels and generates a set of voltage differential levels based on the set of voltage levels. The set of voltage differential levels corresponds to a first predetermined value. Each of the voltage levels is different from another of the voltage levels.

Abstract: An open loop envelope tracking system calibration technique and circuitry are proposed. A radio frequency power amplifier receives a modulated signal. An envelope tracker power converter generates a modulated power amplifier supply voltage for the radio frequency power amplifier based on a control signal derived from the modulated signal. A first output power and a second output power of the radio frequency power amplifier are measured when the control signal is respectively delayed by a first delay period and a second delay period. A sensitivity of the output power of the radio frequency power amplifier is near a maximum near the first delay period and the second delay period. The first delay period and/or the second delay period are adjusted until the first output power substantially equals the second output power. The first delay period and the second delay period are used to obtain a calibrated fine tuning delay offset.

Abstract: A comparator is provided and the comparator includes a comparing input unit and a latching unit. Wherein, the comparing input unit has a first input receiving a first comparing signal and has a second input receiving a second comparing signal. The comparing input unit drives a first intermediate node signal at a first intermediate node depending on the first comparing signal according to a first strobe signal, and the comparing input unit drives a second intermediate node signal at a second intermediate node depending on the second comparing signal according to the first strobe signal. The latching unit determines a comparing result according to at least one of the first intermediate node signal and the second intermediate node signal. In addition, the latching unit latches the comparing result according to a second strobe signal.

Abstract: A circuit for detecting out-of-band signals is disclosed. In one embodiment, the circuit includes a first differential circuit configured to level shift and positively rectify a differential input signal to produce a first output component of a differential output signal. The detector further includes a second differential circuit configured to level shift and negatively rectify the differential input signal to produce a second output component of the differential output signal. A third differential circuit is configured to level shift and output first and second fixed voltages based on an input reference voltage and a ground voltage. The circuit is configured to provide the differential output signal and the first and second fixed voltages to an indicator circuit configured to assert an indication responsive to detecting that a differential voltage of the differential output signal is greater than a differential voltage of the first and second fixed voltages.

Abstract: A comparator comprises a differential amplifier type including input MOSFETs receiving differential input of a reference voltage and an input voltage, load MOSFETs for the input MOSFETs, and a constant current source to supply the sources of the input MOSFETs. The comparator comprises a Zener diode that is connected between the gate and source of the input MOSFETs and exhibits a breakdown voltage lower than the withstand voltage of the gate oxide film of the input MOSFET. Another comparator further comprises a feedback MOSFET that performs negative feedback of an output voltage of a main body comparator to the gates of the load MOSFETs to restrict the amplitude of the output voltage. Still another comparator further comprises a semiconductor rectifying element that exhibits a reverse-blocking characteristic higher than the power supply voltage and is interposed between the constant current source and the source of each of the input MOSFETs.

Abstract: An input buffer includes a first amplification block, a second amplification block, and a buffer block. The first amplification block is configured to be driven by an external voltage, to differentially amplify an input signal and a reference voltage in response to a bias voltage, and to subsequently generate first and second differential signals. The second amplification block is configured to be driven by an internal voltage, to differentially amplify the first and second differential signals, and to generate an output signal. The buffer block is configured to be driven by the internal voltage, to buffer the output signal, and to output an inverted output signal.

Abstract: A relaxation oscillator has a comparator that includes first through third bias current transistors coupled to a first supply rail. First and second input transistors form a pair of parallel coupled transistors connected to the first bias current transistor. A first current mirror control transistor connects the first input transistor to a second supply rail. A first current mirror output transistor is coupled to the first current mirror control transistor, and connects the second bias current transistor to the second supply rail. A second current mirror control transistor connects the second input transistor to the second supply rail. A second current mirror output transistor is coupled to the second current mirror control transistor, and connects the third bias current transistor to the second supply rail. A transition time reduction transistor, coupled across the third bias current transistor, is coupled to the second bias current transistor, and provides a comparator output.

Abstract: A comparator circuit can achieve a reduction in current consumption with a simple configuration, and can suppress an increase in current consumption accompanying a rise in power source voltage. A current mirror circuit is connected to a power source, and gates of MOSFETs of the circuit are interconnected. An input signal is applied to a gate of an NMOSFET of the circuit. By determining the value of the signal with a constant voltage device, the voltage across a tail resistor is constant, even in the event that the power source voltage and the input signal change.

Abstract: Systems and methods for driving an optical modulator are provided. In one embodiment, a modulation drive circuit comprises: a balanced impedance network having a first and a second output generated from a first input, and a third and a fourth output generated from a second input, wherein the first and second outputs are balanced with one another, and the third and fourth outputs are balanced with one another; a first differential amplifier, wherein an inverting input of the first differential amplifier couples to the first output of the distribution network and a non-inverting input of the first differential amplifier couples to the third output of the distribution network; and a second differential amplifier, wherein an inverting input of the second differential amplifier couples to the fourth output of the distribution network and a non-inverting input of the second differential amplifier couples to the second output of the distribution network.

Abstract: A coupling failure of a supply terminal or a ground terminal is easily detected. A diode is disposed between a supply terminal of a semiconductor device and a first I/O terminal so that the supply terminal is located on a cathode side, and the first I/O terminal is located on an anode side. A determination unit determines whether or not a voltage of the supply terminal is lower than a voltage of the first I/O terminal when a signal of high level equal to a supply voltage is input to the first I/O terminal.

Abstract: A semiconductor device configured that its differential pair is made operable in both states of high speed with a high consumption current and low speed with a low consumption current. A differential circuit includes differential pair transistors and a tail current source for supplying a tail current that is switchable so that an amount of current flowing in the differential pair transistors may be switched between at least two sates of different levels. The differential pair transistors have a characteristic that, with a decrease of currents flowing in the differential pair transistors, a value of ?(?I/gm) decreases monotonously, where ? denotes a standard deviation, ?I denotes a difference of the amounts of current of the differential pair transistors, and gm denotes transconductance of the differential pair transistors.

Abstract: An apparatus comprises a supply voltage divider, a state machine, two comparators and a threshold selector. The supply voltage divider divides a VCC into N states SK, and acquires the border voltages VK and VK+1 corresponding to the SK through a resistor divider. The threshold selector acquires a corresponding voltage VK from the supply voltage divider according to the current state SK outputted by the state machine and then sends the acquired VK as VH to a first comparator, and acquires a corresponding voltage VK+1 and sends the acquired VK+1 as VL to a second comparator. The state machine determines whether or not the VH and the VL are matched with the current state SK. If matched, the OSC of the state machine will be turned off, otherwise, the next state Sk+1 or Sk?1 of the SK will be outputted.

Abstract: In a power detector, a comparator for detection receives an input signal and a reference voltage, and compares the input signal to the reference voltage around the switching time of active and inactive states of the output of the comparator in accordance with an output of an input switching signal generator. Except for the switching time, an input voltage for non-use of the comparator is inputs to the comparator for detection, and the differential inputs are fixed to the same potential. Therefore, aging reduction in the accuracy of power detection caused by BT degradation is effectively mitigated.

Abstract: The present invention provides a high-side signal sensing circuit. The high-side signal sensing circuit comprises a signal-to-current converter, a second transistor and a resistor. The signal-to-current converter has a first transistor generating a mirror current in response to an input signal. The second transistor cascaded with the first transistor is coupled to receive the mirror current. The resistor generates an output signal in response to the mirror current. Wherein, the level of the output signal is corrected to the level of the input signal.

Abstract: A comparator includes a first amplifier, a second amplifier, and a level holding part. The first amplifier includes differential-pair transistors and outputs a signal of a level corresponding to a comparison result from a first output node. The differential-pair transistors compare a reference voltage with a potential of an input signal. The second amplifier gain up the signal output from the first output node of the first amplifier and outputs the signal from a second output node. The level holding part holds a level of the second output node at a predetermined level. The second amplifier includes a transistor for amplification and a transistor for a current source. The level holding part holds the level of the second output node of the second amplifier such that the transistor for the current source does not fall into a level at which a saturated operation condition is not satisfied.

Abstract: A circuit for detecting out-of-band signals is disclosed. In one embodiment, the circuit includes a first differential circuit configured to level shift and positively rectify a differential input signal to produce a first output component of a differential output signal. The first differential circuit is further configured to generate and provide a common mode voltage of the differential input signal as a second component of the differential output signal. The circuit further includes a second differential circuit configured to level shift and output first and second fixed voltages based on an input reference voltage and a ground voltage. The circuit is configured to provide the differential output signal and the first and second fixed voltages to an indicator circuit configured to assert an indication responsive to detecting that a differential voltage of the differential output signal is greater than a differential voltage of the first and second fixed voltages.

Abstract: A comparator includes: a pre-amplification module, configured to generate two amplified differential signal reference currents according to an input voltage and a reference voltage; and a differential signal obtaining module, configured to obtain a differential signal according to the two amplified differential signal reference currents. The pre-amplification module includes a differential unit, an offset unit, and an amplification unit, where the differential unit is configured to generate two direct current bias currents according to the input voltage and the reference voltage; the offset unit is configured to generate an offset current of the two direct current bias currents according to the input voltage and the reference voltage, so as to reduce magnitude of the two direct current bias currents and obtain two differential signal reference currents; the amplification unit is configured to receive the two differential signal reference currents, and amplify the two differential signal reference currents.

Abstract: A current-limited differential entry stage compares an input signal to a reference voltage generated by a current-limited transistor or diode configuration. Current limiters comprise a D-mode feedback transistor having a gate-source junction. The D-mode transistor is not conducting between the source and the drain if a gate-source voltage is more negative than a negative threshold voltage, and conducting between the source and the drain, otherwise a feedback connection connects the source of the D-mode feedback transistor to its gate via a component that generates a voltage drop.

Abstract: An apparatus of common mode compensation for voltage controlled delay circuits and method are provided. In one implementation a method includes amplifying a differential input signal to generate a differential output signal using a differential pair of transistors biased by a tail current; changing the tail current by a first amount to change a circuit delay of the differential pair of transistors; generating a first compensation current and a second compensation current by using a current mirroring such that a sum of the first compensation current and the second compensation current is of a second amount that is substantially equal to the first amount; injecting the first compensation current into the first end of the differential output signal via a first coupling resistor; and injecting the second compensation current into the second end of the differential output signal via a second coupling resistor.

Abstract: In a power detector, a comparator for detection receives an input signal and a reference voltage, and compares the input signal to the reference voltage around the switching time of active and inactive states of the output of the comparator in accordance with an output of an input switching signal generator. Except for the switching time, an input voltage for non-use of the comparator is inputs to the comparator for detection, and the differential inputs are fixed to the same potential. Therefore, aging reduction in the accuracy of power detection caused by BT degradation is effectively mitigated.

Abstract: The invention relates to an electronic device which comprises a comparator coupled to monitor a first supply voltage level at a first supply voltage node. The comparator comprises a differential input transistor stage having one input coupled to the first supply voltage node and the other input coupled to receive a reference voltage level, a first current source configured to supply a current of a first magnitude, a second current source configured to supply a current of a second magnitude, and a capacitor. The first magnitude is greater than the second magnitude and the first current source is coupled with one side to the differential input stage for supplying the differential input stage and with the other side to a first node. The second current source is coupled with one side to the first node and with the other side to a second supply voltage node having a second supply voltage level and the capacitor is coupled with one side to the first node and with the other side to the first supply voltage node.

Abstract: A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.

Abstract: A receiving circuit for a core circuit is provided and includes a first receiving-path unit. The first receiving-path unit is capable of receiving an input signal and outputting an output signal to the core circuit according to the input signal. The first receiving-path unit includes an input buffer which is capable of operating in a core power domain of the core circuit and receiving a first clamped signal. When a level of the input signal is substantially equal to or lower than a first predetermined voltage level, the input signal is passed to the input buffer to serve as the first clamped signal, and the input buffer is capable of outputting the output signal in the core power domain according to the first clamped signal. When the level of the input signal is higher than the first predetermined voltage level, the input signal is not passed to the input buffer.

Abstract: In a comparator circuit having a differential amplifier, which makes a logical judgment by comparing an input voltage with a reference voltage, generates and outputs a resulting output voltage thereof, a current source generates and supplies a bias current of a predetermined minute current to the differential amplifier, and a first inverter circuit inverts a differential voltage from the differential amplifier. An adaptive bias current generator circuit detects the bias current of the current source, and a through current of the first inverter circuit. The adaptive bias current generator circuit generates and supplies an adaptive bias current for executing adaptive bias current control to the differential amplifier to allow the differential amplifier to operate with the bias current upon no logical judgment, and to allow the differential amplifier to operate by using the adaptive bias current obtained by increasing the bias current upon logical judgment.

Abstract: A latched comparator circuit comprises an input amplification unit, a buffer unit, and a control unit. The input amplification unit comprises a first and a second input terminal for receiving a first and a second input voltage, respectively, of the latched comparator circuit. The input amplification unit further comprises a first and a second output terminal for outputting a first and a second output voltage, respectively, of the input amplification unit. In addition, the input amplification unit comprises a reset terminal arranged to receive a reset signal for resetting the input amplification unit. The buffer unit is operatively connected to the first and the second output terminal of the input amplification unit. Furthermore, the buffer unit comprises a first and a second output terminal for outputting a first and a second output voltage, respectively, of the buffer unit. The control unit is operatively connected to the input amplification unit and the buffer unit.

Abstract: A half-power buffer amplifier is disclosed. A buffer stage includes a first-half buffer stage and a second-half buffer stage, wherein an output of the first-half buffer stage is controllably fed back to a rail-to-rail differential amplifier, and an output of the second-half buffer stage is controllably fed back to the rail-to-rail differential amplifier. The switch network controls the connection between the outputs of the buffer stage and an output node of the half-power buffer amplifier in a manner such that a same pixel, with respect to different frames, of a display panel is driven by the same rail-to-rail differential amplifier. In one embodiment, the rail-to-rail differential amplifier and the buffer stage comprise half-power transistors operated within and powered by half of a full range spanning from power to ground.

Abstract: The present invention relates to a simple and small-sized circuit configuration (10) for significantly reducing resettling time of a peak or zero current comparator. This circuit configuration (10) provides the comparator input stage with an alternative current path at the comparator input submitted to a large voltage variation able to disturb the DC-settings. This circuit configuration (10) comprises a pair of small transistors (P3, P4) coupled to a differential pair of transistors (N1, N2) of the comparator input stage and having a polarity different from said pair of transistors (P3, P4). The gates of the transistors P3 and P4 share a common terminal connected to said comparator input. The currents and voltages across the comparator are always maintained close to the normal DC-setting values during the voltage transition phase. This circuit configuration (10) can be used in any current comparator for detecting a peak or a zero current, in particular, in DC-DC converters based on a switched operating mode.

Abstract: An HDMI cable carries high speed encoded data which are transmitted differentially over data channels, along with a clock. High-frequency loss and differential skew within a differential signal may be compensated by analog circuits embedded in the cable. These embedded circuits are tuned at production for best performance by observing the quality of the recovered analog signal. The embedded circuits are powered by a combination of power sources, both carried within the cable, and harvested from the high-speed signals themselves.

Abstract: An HDMI cable carries high speed encoded data which are transmitted differentially over data channels, along with a clock. High-frequency loss and differential skew within a differential signal may be compensated by analog circuits embedded in the cable. These embedded circuits are tuned at production for best performance by observing the quality of the recovered analog signal. The embedded circuits are powered by a combination of power sources, both carried within the cable, and harvested from the high-speed signals themselves. Methods are provided for deskewing, equalizing, and boosting the differential signals in the embedded circuits that are mounted on a PCB.

Abstract: A comparator is configured to generate an output voltage representing the comparison between the absolute value of the difference between two input voltages with an adjustable reference voltage. The comparator includes an input differential amplifier, receiving the two input voltages and connected to an active load network controlled by a control voltage, a control circuit that generates the control voltage representing the adjustable reference voltage, and an output stage having a logic circuit configured to produce the output voltage of the comparator as a logic combination of the output voltages of the differential amplifier.

Abstract: A switching mode power supply with improved peak current control is disclosed. A varying reference signal is adopted to limit the peak current in the energy storage component. The varying reference signal is an exponential function of a time period when a power switch is ON, wherein the power switch is coupled to the energy storage component. The varying reference signal may be generated by a circuit comprising a RC circuit and one or several voltage sources.

Abstract: An output stage includes a first transistor pair with a first conductivity type and a second transistor pair with a second conductivity type. The source connections of the first and second transistors in the first transistor pair and of the first and second transistors in the second transistor pair are respectively connected to a first and a second circuit node. The output stage further includes a first current mirror with the first conductivity type and a second current mirror with the second conductivity type. The current mirror transistors are connected to the signal output. The signal input is connected to control connections of the first transistors in the first and second transistor pairs. A second connection of the second transistor in the first transistor pair is connected to the second current mirror, and a second connection of the second transistor in the second transistor pair is connected to the first current mirror.

Abstract: A single-ended data transmission system transmits a signal having a signal voltage that is referenced to a power supply voltage and that swings above and below the power supply voltage. The power supply voltage is coupled to a power supply rail that also serves as a signal return path. The signal voltage is derived from two signal supply voltages generated by a pair of charge pumps that draw substantially same amount of current from a power supply.

Abstract: A power integration circuit includes: a first transistor having a control electrode connected to a first voltage source to be supplied with a control signal therefrom, the first transistor being connected between a switch and a ground. A sense resistor has one end connected to the ground. A second transistor has a control electrode connected to the first voltage source to be applied with a control signal therefrom, with the second transistor being connected between the switch and the other end of the sense resistor. The power integration circuit further includes: a comparator for comparing the sense voltage with the reference voltage and delivering a difference between the sense voltage and the reference voltage to a logic circuit.

Abstract: An output stage includes a first transistor pair with a first conductivity type and a second transistor pair with a second conductivity type. The source connections of the first and second transistors in the first transistor pair and of the first and second transistors in the second transistor pair are respectively connected to a first and a second circuit node. The output stage further includes a first current mirror with the first conductivity type and a second current mirror with the second conductivity type. The current mirror transistors are connected to the signal output. The signal input is connected to control connections of the first transistors in the first and second transistor pairs. A second connection of the second transistor in the first transistor pair is connected to the second current mirror, and a second connection of the second transistor in the second transistor pair is connected to the first current mirror.

Abstract: A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.

Abstract: A current source generates a reference current. A first transistor is a depletion-type MOSFET arranged such that one terminal thereof is connected to the current source and its gate is connected to its source. A second transistor is an enhancement-type MOSFET arranged such that one terminal thereof is connected to the other terminal of the first transistor, the other terminal thereof is connected to a fixed voltage terminal, and its gate and drain are connected. A third MOSFET is an enhancement-type P-channel MOSFET arranged such that one terminal thereof is connected to the current source, the other terminal thereof is connected to the fixed voltage terminal, and its gate is connected to a connection node connecting the first and second transistors. A constant voltage circuit outputs at least a voltage that corresponds to the gate voltage of the third transistor or a voltage that corresponds to the gate voltage thereof.

Abstract: A successive-approximation type AD converting circuit is provided with a comparing circuit (CMP) which judges the magnitudes of an input analog voltage and a comparison voltage, and a local DA converting circuit (DAC) which generates a voltage according to a judgment result of the comparing circuit and outputs the generated voltage as the comparison voltage. The comparing circuit is provided with at least one amplification stage (INV), a first switching element which is provided between the input terminal and the output terminal of each amplification stage, and resistance value adjusting sections (RT11-RT32) which are connected between each amplification stage and a first power source terminal or a second power source terminal, and the resistance value adjusting sections are configured to have a high resistance value when the power source voltage is high and a low resistance value when the power source voltage is low.

Abstract: A semiconductor device includes: a substrate; a transistor that has a ring-shaped gate electrode formed on the substrate; a plurality of external dummy electrodes that are arranged outside the gate electrode and are formed in the same layer as the gate electrode; and at least one internal dummy electrode that is arranged inside the gate electrode and is formed in the same layer as the gate electrode.

Abstract: Embodiments include a comparing device having hysteresis characteristics and a voltage regulator using the same. The voltage regulator includes a comparator which compares a comparison voltage with a reference voltage and outputs a result of the comparison, a switching controller which generates a plurality of switching signals in response to the comparison result, resistors connected in the form of a string to divide the comparison voltage into a plurality of voltages, and a switching box which selects one of the plural voltages as the comparison voltage in response to the switching signals.

Abstract: Receiver architectures and bias circuits for a data processor are provided. A receiver architecture includes a linear receiver having a first input node for a data (DQ) signal, a second input node for a reference voltage, and output nodes for a differential output signal. The linear receiver compares the DQ signal to the reference voltage, and generates the differential output signal in response to the comparison. A sense amplifier is coupled to the linear receiver. The sense amplifier has input nodes connected to the output nodes of the linear receiver, and an output node for a binary output signal having voltage characteristics compatible with the processor. The sense amplifier transforms the differential output signal into the binary output signal. The receiver architecture also includes a programming architecture coupled to the linear receiver to set operating characteristics of the linear receiver.

Abstract: A method and a device for canceling an offset voltage in an output of a comparator circuit include sampling a set of offset voltages; applying a set of correction voltages equal in magnitude and opposite in polarity to the set of offset voltages, the set of correction voltages being applied to an output generating arrangement of the comparator circuit; and enabling output of the output generating arrangement after the set of correction voltages is applied.

Abstract: An integrated circuit comparator comprises a differential amplifier, a source follower circuit coupled to a gate terminal of a first transistor in the differential amplifier, and an output circuit. One or more source follower circuits may be utilized in connection with the differential amplifier, and one or more source follower circuits may be utilized in connection with the output circuit.

Abstract: A transmitter expresses continuous-time signals on alternate, parallel channels with reference to different supply voltages such that the signals on alternate channels have different common-mode voltages. At the transmitter, expressing the symbols using alternate supply voltages limits the maximum supply current used to express the signals and to transition between adjacent symbol sets. Limiting supply current ameliorates problems associated with simultaneous switching noise (SSN). At the receiver, the different common-mode voltages tend to balance the current to and from termination nodes, and consequently place reduced stress on a reference voltage. Providing different common-mode voltages on alternate channels may additionally reduce cross-talk between channels.

Abstract: A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.

Abstract: A start signal detection circuit includes a wave-detection circuit 1 outputting a voltage in accordance with an envelope of a radio signal from an output point B, a reference voltage generation circuit 2 outputting a voltage at the output point B at a non-signal state as a reference voltage to a reference point C, and a differential amplification circuit 3 amplifying and outputting a voltage difference between the output point B and the reference point C.