Abstract: A CMOS output circuit including a differential error amplifier (3) is operated to provide a stable quiescent bias current in an output MOSFET by causing a first current equal to a threshold voltage of a P-channel reference MOSFET (M1) divided by the resistance of a reference resistor (R1) to flow through an N-channel current mirror control MOSFET (M4). A first N-channel current mirror output MOSFET (M6) having a gate coupled to the gate of the N-channel current mirror control MOSFET (M4) and a drain coupled to a drain of the P-channel reference MOSFET (M1) causes a second current proportional to the first current to flow through the P-channel reference MOSFET (M1). The first current is controlled in response to feedback from the P-channel reference MOSFET (M1). A bias current in an error amplifier (3) is controlled in response to the N-channel current mirror control MOSFET (M4).

Abstract: A circuit provides an output signal having a portion with a constant maximum amplitude, followed by a portion decreasing down to a constant zero value when an input voltage increases from zero. The circuit includes an asymmetrical differential stage having a low gain branch and a high gain branch, respectively controlling two branches of a symmetrical differential stage. The current of the asymmetrical differential stage corresponds to the end of the decreasing portion. The current of the symmetrical differential stage corresponds to the maximum amplitude of the signal which is provided by one of the branches of the symmetrical differential stage. The high gain branch and low gain branch are respectively controlled by the input voltage and by a voltage corresponding to the beginning of the decreasing portion.

Abstract: A semiconductor integrated circuit device is provided having a low-amplitude input/output interface for inputting or outputting an input/output signal synchronously with a clock signal and transferring the input/output signal with an amplitude corresponding to a power supply voltage to or from an external command unit. A first differential circuit to be practically continuously operated is used as an input circuit for receiving a clock signal supplied from an external clock unit. In addition, a second differential circuit is provided which is intermittently operated in accordance with the clock signal to sample an input signal in accordance with an internal clock signal generated by the first differential circuit while the second differential circuit is operated and holds the sampled signal while the second differential circuit is not operated. This second differential circuit is used as an input circuit for receiving a low-amplitude input signal inputted synchronously with the clock signal.

Abstract: A cascoded differential amplifier with a circuit for the injection of current to enhance the gain is described. The differential amplifier includes a differential pair of n-MOS FET's connected to a current source an a positive and a negative input terminal. A pair of isolation n-MOS FET's are inserted between the differential pair and a pair of current source loads. These isolate the current source loads from the differential pair. A current injector is connected to the drains of the n-MOS FET's of the differential pair. The isolation n-MOS FET's and the injected currents enhance the gain of the differential amplifier. A level translation circuit adjusts the output levels of the differential pair to levels required by circuitry attached to the output terminals of the level translation circuitry.

Abstract: A transconductance amplifier suitable for the input stage of a comparator with the capability of amplifying input signals with common mode voltage components in a range including the entirety of its operating voltage. Operation at one voltage extreme is accomplished by use of a long tailed pair connection of a pair of bulk modulated FETs with gates at the input terminals of the amplifier. Operation at the other voltage extreme is accomplished by the use of a pair of FETs in a source follower mode to drive common gate transistors of opposite polarity, the gates of the FETs also being connected to the input terminals of the amplifier. A common high impedance load for the comparator is connected to current mirrors of the drains of both pairs of FETs in the amplifier. The circuit may be implemented with bipolar transistors and additional amplification provided. Methods of comparing voltages are also disclosed.

Abstract: A level detection circuit for monitoring the level of a power supply voltage and producing an output signal at power on for resetting various system elements powered by the supply voltage when the supply voltage reaches a predetermined level. The detection circuit, which is powered by the supply voltage includes a voltage reference circuit which produces a reference voltage having a magnitude which is relatively independent of the power supply voltage. A translator circuit functions to produce a translated voltage indicative of the supply voltage magnitude and which is comparable in magnitude to the reference voltage when the supply voltage is at a suitable level such that the system will accept a power on reset pulse. A comparator circuit functions to compare the reference voltage with the translated voltage and cause an associated output circuit to issue the reset pulse. The reset circuit typically includes a one shot circuit, the output of which is logically ORed with the amplified comparator output.

Abstract: A zero current enable circuit and zero current enable method are disclosed. The integrated circuit features at least one sense circuit and a logic gate. The sensing circuit combines a broken band gap reference voltage, a voltage divider, a voltage clamp, a comparator, and a logic gate to generate an enable signal.

Abstract: A driver circuit (100) is utilized to drive a high current load (116) in an electronic device powered by a battery (118) having a terminal voltage which varies in relation to a level of energy being consumed. The driver circuit (100) includes a differential amplifier (110) which is responsive to a predetermined reference voltage and to the terminal voltage for generating a drive control signal which proportionally reduces a current supplied to the high current load (114) when the terminal voltage is substantially equal to and lower than the predetermined reference voltage. A slope control element (112) is coupled to the differential amplifier (110) to control a rate at which the drive control signal reduces proportionally the current supplied to the high current load (116). A load control element (114), coupled to the differential amplifier (100), provides the supply of current to the high current load (116).

Abstract: A circuit for providing an input offset voltage to balance a fully differential amplifier may include two field effect transistors (FETs) in parallel conductive paths for receiving a current, an amplifier current source, a resistor connecting the FETs at their drains, and a second amplifier with inputs for an offset correction voltage and for a reference voltage on which the fully differential amplifier is to be balanced and outputs for providing control inputs to the FETs. The input offset voltage for balancing the fully differential amplifier is the difference between currents in the parallel paths times the resistance of the resistor. The circuit may be used to balance a fully differential amplifier in a telephone CODEC. The correction voltage may correct the total offset from the CODEC, or the offset introduced by a sign bit integrator that provides a correction for excursions of the same polarity in the CODEC.

Abstract: In an input buffer circuit for use in a semiconductor integrated circuit, comprising a differential pair formed of a pair of MOS transistors and receiving a reference voltage and an input signal supplied from an external, a first constant current source MOS transistor connected to the differential pair, and a load circuit connected to the differential pair, a second constant current source MOS transistor is connected in parallel to the first constant current source MOS transistor. A gate voltage of the second constant current source MOS transistor is controlled by a reference voltage convening circuit which receives the reference voltage.

Abstract: An operational amplifier and a digital signal transfer circuit in which an output voltage does not decrease instantly even if an abrupt change of input signal due to noise causes a high-to-low transition to be superposed on an input signal. The operational amplifier includes a differential pair of transistors with a first transistor having a collector that is grounded and a second transistor having an emitter connected to the emitter of the first transistor; a current mirror circuit with a third transistor having a collector connected to an output node of the differential pair of transistors and a fourth transistor having a base connected to a base of the third transistor; a fifth transistor having a collector connected to an output terminal and a base connected to an output node of the current mirror circuit; and a capacitive element connected between the output node of the current mirror circuit and the output terminal.

Abstract: A cell of MOS transistors for converting a voltage into a current for forming synapses of neural nets, in particular for converting the difference between an input voltage (V.sub.IN) and a voltage (V.sub.W) for weighting the synapse into a current, realized by means of a differential stage comprising a first transistor (M1) operating as a current generator, in which a first and a second branch in parallel end, which branches respectively comprise a second (M2) and a third (M3) push-pull connected transistor, to the gate regions of which the input voltage (V.sub.IN) and the voltage (V.sub.W) for weighting the synapse, and to which a fourth (M4) and a fifth (M5) transistor are respectively connected in series, in which the fourth (M4) and the fifth (M5) transistor are P-MOS transistors having their gate regions short-circuited and said fourth (M4) P-MOS transistor is connected as a diode, and in which the output current (I.sub.

Abstract: A potential detecting circuit comprises a MOSFET, a constant current circuit, a reference potential generating circuit and a comparing circuit. A power supply potential is applied to a drain of the MOSFET and a subject potential to be detected is applied to the gate of the MOSFET. The constant current circuit is connected to a source of the MOSFET. The comparing circuit compares a reference potential output from the reference potential generating circuit with a source potential of the MOSFET. A detection output is obtained on the basis of the comparison result. The source potential of the MOSFET is increased in accordance with an increase of the subject potential. When the source potential coincides with the reference potential output from the reference potential generating circuit, the level of the source potential is detected as a detection level.

Abstract: This invention provides a semiconductor device including a circuit having a resistor element whose resistance value can be controlled via application of a control voltage, and permits the circuit to be designed stably without requiring labor and time for adjustment of the control voltage to be applied to the resistor element for precisely controlling resistance of the resistor element, and without increasing chip area. One preferred embodiment includes a reference resistor, such as a carbon film resistor or a chip resistor having a dispersion of approximately .+-.1% and having a very highly stable resistance value, and a diffused layer resistor which is used as the resistor element. The diffused layer resistor has a dispersion of approximately .+-.30% in a LSI circuit.

Abstract: Power consumption by the driving circuitry of an output stage, employing a slew-rate controlling operational amplifier, is reduced by modulating the level of the current output by the operational amplifier in function of the working conditions of the output stage. Switching delay may also be effectively reduced. An auxiliary current generator forces an additional current through the conducting one of the pair of input transistors of the operational amplifier only during initial and final phases of a transition, essentially when the slew rate control loop ceases to be effective. The boosting of the bias current through the conducting input transistor is determined by the degree of unbalance of the differential input stage of the operational amplifier, without the use of dissipative sensing elements.

Abstract: An accurate V/I conversion circuit converts an input voltage to an electric current which includes an external resistance in series with an input voltage V1. The external resistance is directly coupled to an input terminal of the V/I conversion circuit. V/I conversion circuit includes an input terminal coupled to the external resistance which is in series with the input voltage V1. V/I conversion circuit also includes (1) a resistance type voltage dividing circuit which generates a standard voltage by dividing a supply voltage, (2) a differential amplifier circuit comprising two transistors which compares a voltage of the input terminal with the standard voltage, (3) a third transistor which receives the collector voltage of one of the transistors in the differential amplifier where the third transistor is also connected between the input terminal and ground with a resistor in series, and (4) a fourth transistor which receives a collector voltage of one of the transistors of the differential amplifier.

Abstract: A differential comparator that amplifies small swing signals to full swing signals. The differential comparator comprises a current switch having a pair of inputs coupled to receive a pair of small swing complementary input signals and a pair of complementary outputs that output complementary signals. The complementary signals output by the current switch have a voltage swing that centers about a predetermined voltage in response to the complementary input signals. The differential comparator further comprises first and second inverters coupled to receive the output complementary signals, wherein each inverter has a trip point voltage equal to the predetermined voltage. The first and second inverters output full swing complementary output signals in response to the complementary signals output by the current switch.

Abstract: There is disclosed an input circuit for a semiconductor integrated circuit device wherein a level shift circuit (LS1) adds a constant voltage to an input signal from an input signal terminal (3) and a reference voltage from a reference voltage terminal (4) to output signals, which are in turn amplified by means of a plurality of cascaded, first and second differential amplifier circuits (Dif1, Dif2), and then a difference between the amplified input signal and the amplified reference voltage is applied to a CMOS inverter circuit (In1), which in turn outputs a power supply potential (V.sub.DD) or a ground potential (V.sub.SS) in accordance with the difference, thereby achieving a high-speed operation in response to the binary input signal slightly varying in signal voltage and a normal operation independent of variation of the reference voltage. (FIG.

Abstract: A clocked comparator having an input differential amplifier, a sample and hold circuit, and a load stage. The load stage including a first transistor whose channel is connected between a first terminal and a first node, a second transistor whose channel is connected between a second terminal and a second node, a third transistor whose channel is connected between the first node, a third terminal and a fourth transistor whose channel is connected between the second node and the third terminal and a switch between the first and the second terminal. The gates of the first and the fourth transistor are connected to the first terminal. The gates of the second and the third transistor are connected to the second terminal. When the switch is closed the first and the second transistor form a positive differential impedance between the first and the second terminal. When the switch is open the cross-coupled third and fourth transistors form a negative differential impedance between the first and the second terminal.

Abstract: A transconductance amplifier suitable for the input stage of a comparator with the capability of amplifying input signal with common mode voltage components in a range including the entirety of its operating voltage. Operation at one voltage extreme is accomplished by use of a long tailed pair connection of a pair of bulk modulated FETs with gates at the input terminals of the amplifier. Operation at the other voltage extreme is accomplished by the use of a pair of FETs in a source follower mode to drive common gate transistors of opposite polarity, the gates of the FETs also being connected to the input terminals of the amplifier. A common high impedance load for the comparator is connected to current mirrors of the drains of both pairs of FETs in the amplifier. The circuit may be implemented with bipolar transistors and additional amplification provided. Methods of comparing voltages are also disclosed.

Abstract: A motor current detection circuit is formed of a current detector for detecting an overloaded state of a motor by comparing a motor current value, which represents current flowing through the motor, with a predetermined reference value, and a hysteresis generating circuit for generating, in the current detector, a hysteresis characteristic corresponding to an integrated value with respect to time of an increment amount by which the motor current value exceeds the reference value. Chattering in output of the current detector is reduced so that an overloaded state of the motor can be detected quickly.

Abstract: A level detection circuit for monitoring the level of a power supply voltage and producing an output signal at power on for resetting various system elements powered by the supply voltage when the supply voltage reaches a predetermined level. The detection circuit, which is powered by the supply voltage includes a voltage reference circuit which produces a reference voltage having a magnitude which is relatively independent of the power supply voltage. A translator circuit functions to produce a translated voltage indicative of the supply voltage magnitude and which is comparable in magnitude to the reference voltage when the supply voltage is at a suitable level such that the system will accept a power on reset pulse. A comparator circuit functions to compare the reference voltage with the translated voltage and cause an associated output circuit to issue the reset pulse. The reset circuit typically includes a one shot circuit, the output of which is logically ORed with the amplified comparator output.

Abstract: The positive input terminal (1), the negative input terminal (2) and the differential amplifier (10) are connected to the voltage converting circuit (9a). The differential amplifier (10) is composed of the operational amplifier (6) and the resistors (5a, 5b, 5c and 5d). The voltage converting circuit (9a) includes NPN transistors (91, 92 and 93). The base of the transistor (91) is connected to the positive input terminal (1) and the base of the transistor (92) is connected to the reference potential input end (3) to which the reference potential (V.sub.x) is applied, respectively. The collectors of the transistors (91 and 92) are connected to the potential point (81) in common and the emitters are connected to the other end of the resistor (5a). The base of the transistor (93) is connected to the negative input terminal (2), the collector is connected to the potential point (81) and the emitter is connected to the other end of the resistor (5c).

Abstract: A hysteresis comparator circuit working with a low voltage supply and of a type which includes a composite structure incorporating first and second differential cells respectively comprised of an npn bipolar transistor pair with common emitters, on the one side, and a pair of pnp bipolar transistor pair with common emitters, on the other, such cells being coupled together through the bases of the respective transistors. The circuit includes at least one pair of variable current sources associated with each cell and tied operatively to the voltage value present on the comparator output; in addition, a voltage divider is connected between each interconnection of the bases of the transistors forming the cells.

Abstract: There is provided a potential comparing circuit of which output potential is almost equal to specific determining potential levels used in a next-stage logic circuit. The potential comparing circuit has a current-mirror circuit, a first transistor, a second transistor and an offset correcting circuit. The current-mirror circuit is connected to a first power source. The first transistor has a gate to which a first input signal is supplied. The second transistor has a gate to which a second input signal is supplied, a channel type of the second transistor being the same as a channel type of the first transistor. The offset correcting circuit is provided between a drain of the first transistor and an input point of the current-mirror circuit, for correcting a potential level obtained at a drain of the first transistor to correspond to specific potential levels related to the specific determination potential levels.

Abstract: A decision circuit compares an input voltage with a reference voltage and judges whether the input voltage is at least equal to the reference voltage. A controller in the decision circuit detects whether the input voltage or reference voltage is at least equal to the setting voltage. When both the input voltage and the reference voltage are lower than a setting voltage, which represents an operating voltage of the decision circuit, a first bias-supply circuit adds a predetermined bias voltage to the input voltage and supplies a level-shifted input voltage to the decision circuit. Similarly, a second bias-supply circuit adds the predetermined bias voltage to the reference voltage and supplies a level-shifted reference voltage to the decision circuit. Therefore, the decision circuit compares the level-shifted input voltage with the level-shifted reference voltage.

Abstract: A comparator 10 has a first stage differential amplifier 11 coupled to a second stage, single ended differential amplifier 12. The output of the second stage is coupled to a latch input stage 15 of a latch 16. A latch replica bias circuit 20 operates the second stage at a clamp voltage corresponding to the threshold voltage of latch 16. A clock signal clk switches the second stage 12 between gain and clamp modes.

Abstract: A load stage including a first transistor whose channel is connected between a first terminal and a first node, a second transistor whose channel is connected between a second terminal and a second node, a third transistor whose channel is connected between the first node, a third terminal and a fourth transistor whose channel is connected between the second node and the third terminal and a switch between the first and the second terminal. The gates of the first and the fourth transistor are connected to the first terminal. The gates of the second and the third transistor are connected to the second terminal. The load stage also includes a switch connected between the first node and the second node. When the switch is closed the first and the second transistor form a positive differential impedance between the first and the second terminal. When the switch is open the cross-coupled third and fourth transistors form a negative differential impedance between the first and the second terminal.

Abstract: An automatic trigger circuit including: a two-arm current mirror including a first arm connected between a DC electrical supply and a ground, the first arm including a first transistor including a first source connected to the DC electrical supply, a first gate, and a first drain connected to the first gate; a second transistor including a second gate connected to the DC electrical supply, a second drain connected to the first drain and a second source; a third transistor including a third drain connected to the second source, a third gate for receiving a first level reference voltage, and a third source; and a fourth transistor including a fourth drain connected to the third source and a fourth source connected to the ground; and a second arm connected between the DC electrical supply and the ground, the second arm including a fifth transistor including a fifth source connected to the DC electrical supply, a fifth gate connected to the first gate and a fifth drain; and a sixth transistor including a sixth dr

Abstract: An analog-to-digital convertor apparatus finds input signals of a comparison output to a virtual reference potential between reference potentials with significantly fewer elements in the comparator than in the prior art. A composite inverted output current and a composite in-phase output current are generated by adding the in-phase comparison output current of the first and second comparison output currents of an input signal to the first and second reference signals. Then, an interpolation output means compares the generated composite output currents with a comparison output current which is opposite in phase to these composite output signals. This enables the comparator circuit to obtain the result of comparison of the input signal to a virtual reference signal existing between the first and second reference signals.

Abstract: In a semiconductor circuit device comprising a differential amplifier circuit, which is formed on a semiconductor substrate and which comprises first and second input terminals, and a circuit element formed on the semiconductor substrate and connected to one of the first and the second input terminals. A dummy circuit element is formed on the semiconductor substrate so as to adjoin the circuit element for forming between the dummy circuit element and the semiconductor substrate a dummy parasitic capacitor which is equivalent to a parasitic capacitor formed between the circuit element and the semiconductor substrate. The dummy circuit element is connected to another one of the first and the second input terminals.

Abstract: The present invention provides an integrator 5 with switched hysteresis for inductive proximity switches comprising a reference current source IREF connected between a reference voltage supply rail and a first side of a current mirror, a second side of the current mirror being connected to a proximity switch rectifier, the first side of the current mirror being connected to a capacitor CINT and to one input of a two input comparator, the other input of the comparator being held at a threshold level, wherein a fixed hysteresis current source IHYST is provided in parallel with the current reference source IREF, the fixed hysteresis current source IHYST producing a switchable current which is a fixed proportion of the current of the current reference source IREF, the fixed hysteresis current source IHYST being switched on (off) when a target is detected and off (on) when no target is detected. This invention provides for reduction of effects detrimental to the speed of operation of the switch.

Abstract: An object of the present invention is to enable detection of a precise substrate potential even when the substrate potential of the detecting circuit is at a lower level than the substrate to be measured, and to allow free setting of the stable detection level without being affected by fluctuation in the power supply potential. To that end, there are provided an operational amplifier for differential amplification when the ground potential and the positive power supply potential are supplied, a first resistor for transmitting the substrate potential to the first input terminal of the operational amplifier, a constant voltage circuit, and a reference voltage generating circuit for supplying a positive reference voltage to the second input terminal of the operational amplifier.

Abstract: The comparison circuitry of a comparator is isolated from noise on the power supply and ground by utilizing transistors operating in the forward-active region to isolate the comparison circuitry. The comparison circuitry is further isolated from random noise spikes by utilizing delay and switching circuitry to control the duration of the comparison.

Abstract: An electronic comparator circuit having a high speed during switch phase and combining the advantages of bipolar technology with those of CMOS technology. The circuit consists of a differential stage input circuit having a differential pair of bipolar transistors forming its outputs. The output stage contains a pair of MOS transistors having gate electrodes in common. The pair of MOS transistors is connected on one side to the outputs of the input portion and on the other side to a positive supply pole via a current mirror circuit. The output contains another pair of MOS transistors with gate electrodes in common connected between the out puts of the input portion and ground. The drain electrode of the first pair of MOS transistors forms the output for the comparator.