Abstract: An arrangement and a method in an integrated circuit for tuning and setting a value comprising a comparator circuit having a reference voltage input and a variable voltage input is provided to produce a digital value on an output depending on a comparison between the reference voltage and the variable voltage. A first clocked counter circuit is connected to the comparator to increase or decrease the value of the first clocked counter depending on the digital value supplied from the comparator. The arrangement further comprises a second clocked counter circuit connected to the comparator to increase the value of the second clocked counter for each change of value of the comparator, and a locking circuit connected to the second clocked counter circuit to lock the value stored in the first clocked counter circuit from further changes when the second clocked counter reaches a first threshold value.

Abstract: Circuitry is provided for converting differential digital data to single-ended digital data. Differential data signals have complementary pairs of signals that are referenced to each other. Single-ended signals are referenced to ground. The circuitry can be used on an integrated circuit to convert incoming differential data from a high-speed communications link to single-ended data for processing by internal logic on the integrated circuit. The operation of the circuitry can be stabilized using load circuitry that reduces temperature effects and jitter in the single-ended data.

Abstract: A voltage reference circuit includes storage, programming, and test floating gate transistors. The floating gates of the storage and programming transistors are shorted, while the floating and control gates of the test transistor are shorted. The test and storage transistors are connected between an input terminal and the inputs of a comparator, with the control gate of the test transistor also being connected to the input terminal. A reference voltage is programmed by applying the reference voltage to the input terminal and increasing the net positive charge on the floating gate of the storage transistor (via the programming transistor) until its source voltage matches the source voltage of the test transistor. Then, any test voltage at the input terminal can be compared to the programmed reference voltage by comparing the source voltages of the test and storage transistors.

Abstract: An internal power supply voltage generation circuit includes a main amplifier that supplies a current from an external power supply node to an internal power supply line in accordance with the difference between a reference voltage from a reference voltage generation circuit and an internal power supply voltage on the internal power supply line. The current supply amount by the main amplifier is adjusted by a level adjust circuit, according to the difference between the external power supply voltage and the reference voltage. The internal power supply voltage generation circuit can suppress reduction in the internal power supply voltage in the vicinity of the lower limit area of the differential power supply voltage.

Abstract: A technique for reducing input currents associated with a comparator circuit during certain events includes minimizing bias currents associated with the comparator circuit when a magnitude of an input signal at a signal input of the comparator circuit is a predetermined value from a magnitude of a reference signal applied to a reference input of the comparator circuit. The bias currents are increased when the magnitude of the input signal is within the predetermined value of the magnitude of the reference signal.

Abstract: A semiconductor integrated circuit includes first and second field-effect transistors which have on/off states thereof being controlled by an incoming signal varying within a first potential range, third and fourth field-effect transistors which are controlled by the on/off states of the first and second filed-effect transistors, a node from which an output signal varying within a second potential range is output according to the on/off states of the first through fourth field-effect transistors, and a control circuit which controls a substrate-bias potential of the first field-effect transistor in response to the incoming signal.

Abstract: A differential CMOS amplifier includes two CMOS inverters and biasing circuitry providing feedback loops across the output and input of each inverter. The biasing circuitry provides linear biasing so that the inverters can apply a desired gain to a pair of high frequency input signals (i.e., a differential input signal). The biasing circuitry can include operational amplifiers (op-amps) for providing positive feedback control between the output and input of the inverters. The inputs of the inverters can be regulated by this feedback loop such that their outputs are driven to the reference voltage, thereby forcing the inverters to operate in their linear regions so that non-distorting amplification can be applied to the input AC signals.

Abstract: A sensor signal output circuit includes a first differential amplifier, a first load resistor, a first transistor, a second transistor and a limiter section. The limiter section includes at least a second differential amplifier, which includes an input end coupled to output terminal and an other input end coupled to second reference voltage setting part, a second load resistor for a second differential amplifier, and a third transistor, which includes a gate connected to an output end of the second differential amplifier and a source connected to a gate of the second transistor.

Abstract: A latch circuit includes a sample section for responding to complementary clock signals to sample complementary data signals during a sample period, a latch section for latching the sampled complementary data signals on latch output nodes to transfer the same through latch output nodes during a hold period, and a precharge section for precharging the latch output nodes during the sample period. The latch circuit has a smaller dead zone including a smaller setup time and a smaller hold time.

Abstract: A transmission channel for a subscriber line interface circuit comprises a front end, tip/ring current-sensing transimpedance stage, containing relatively low valued tip and ring sense resistors coupled in circuit with tip and ring paths of a telecommunication wireline pair. The front end transimpedance stage transforms differential tip and ring input currents sensed by the tip and ring sense resistors into a single ended voltage, which is coupled to a transconductance amplifier filter/gain stage. The filter/gain stage is configured to provide a programmable output impedance, and converts the voltage from the current-sensing transimpedance stage into an output transmission voltage for application to a selected one of a current-sense, voltage-feed, or voltage-sense, voltage-feed telecommunication circuit.

Abstract: A floating gate circuit in a read mode that includes at least one floating gate and an analog feedback circuit is disclosed. The feedback circuit causes the floating gate circuit to reach a steady state condition in the read mode such that a reference voltage is generated that is a predetermined function of an input set voltage used to set the at least one floating gate. In a preferred embodiment, the reference voltage generated is approximately equal to the input set voltage.

Abstract: A method and apparatus for setting a floating gate in a floating gate circuit using dual conduction of Fowler-Nordheim tunnel devices is disclosed. In one embodiment, the present invention comprises a floating gate circuit having a single floating gate. During a set mode, the charge level on the floating gate is modified until it is set to a predetermined charge level that is a function of an input set voltage. In another embodiment, the floating gate circuit comprises two floating gates. During a set mode the charge level on each of the floating gates is modified until the difference in charge level between the two floating gates is a predetermined function of an input set voltage that is capacitively coupled to one of the floating gates during the set mode.

Abstract: Charging a storage cell requires the electromotive force exerted at a photogenerating cell in addition to the voltage equal to or higher than the forward on voltage developed at an backflow preventing diode. Therefore, the charging is inefficient. Moreover, the area of the backflow preventing diode must be large in consideration for a current supply from the photogenerating cell at a high intensity of illumination. A charging circuit, constructed using a differential amplifier, which has a power supply therefor separated from another power supply, is used as a direction-of-current detecting circuit that detects the direction of current from a voltage difference between two different power supplies. Consequently, a switch is logically turned on or off depending on whether charging or non-charging is under way. Thus, on voltage to be developed during charging is lowered. Moreover, the size or area of a transistor that acts as a logical circuit is made smaller than that of the backflow preventing diode.

Abstract: The present invention provide an CMOS comparator outputting one bit digital signal after comparing two analog input signals through alternately performing a track mode operation and latch mode operation decided by a clock signal having a constant period, including: a latching unit having the main/sub input terminal; a first switching transistor having the clock signal as a gate input and having one end coupled to main input terminal; a first load transistor diode-connected to the other end of the first switching transistor and a ground end; a second switching transistor having a gate receiving the clock signal as a gate input and one end coupled to the sub input terminal; and a second load transistor diode-connected to the second switching transistor and to the other end of the ground terminal.

Abstract: A semiconductor device is constructed by at least one reference voltage generating circuit for generating a reference voltage, a plurality of input voltage pads for receiving input voltages, a control signal pad for receiving a control signal, and a plurality of input buffers. Each of the input buffers amplifies a difference between one of the input voltages and the reference voltage to generate an output voltage, and includes a switch connected between the reference voltage generating circuit and one of the input voltage pads and controlled by the control signal.

Abstract: A method for sensing the voltage on a floating gate in a floating gate circuit during a set mode is disclosed.

Abstract: Conventionally, a voltage detection circuit that is so configured as to make the temperature coefficient of a predetermined level used as the reference level for voltage detection equal to zero is not composed of the minimum needed circuit elements. The voltage detection circuit of the invention is composed of the minimum needed number of circuit elements and that permits the temperature characteristic of the reference level for voltage detection to be set arbitrarily.

Abstract: In a differential output signal circuit suitable for restraining voltage overshooting/undershooting at differential output terminals due to lags in input signals and realizing stable and fast switching of differential input signals, a first differential pair of PMOS transistors connected to a first current source and a second differential pair of NMOS transistors connected to a second current source are mutually connected at the differential output terminals, and a capacitor is connected between the connection nodes of the respective differential pairs and current sources. A transitional current path of the capacitor restrains voltage variations during differential input signal switching.

Abstract: A circuit and method are given, to realize a high voltage comparator, which generates an output signal for follow-up processing in the low-voltage domain. The high-voltage comparison task is essentially replaced by a current comparison, implemented as a combination of a voltage to current transforming stage with a CMOS current comparator circuit, where only very few parts are working in the high voltage domain. Using the intrinsic advantages of that solution the circuit of the invention is manufactured with standard CMOS technology and only four discrete or integrated extended drain MOS components at low cost. This solution reduces the complexity of the circuit and in consequence also power consumption and manufacturing cost.

Abstract: A buffer has an amplifier that receives an external signal, a reference voltage, and outputs an amplified signal. The amplified signal is responsive to the difference between the external signal and the reference voltage. An inverter receives the amplified signal and generates an inverted signal. A voltage supply circuit is configured to provide an adjusted power supply voltage to the inverter responsive to the reference voltage. A ground voltage supply circuit is configured to provide an adjusted ground voltage to the inverter responsive to the reference voltage.

Abstract: An Advanced Digital Antenna Module (ADAM) for receiving and exciting electromagnetic signals. The ADAM ASIC integrates a complete receiver/exciter function on a monolithic SiGe device, enabling direct digital-to-RF (Radio Frequency) and RF-to-digital transformations. The invention includes an improved analog-to-digital converter (ADC) (10) with a novel active offset method for comparators. The novel ADC architecture (10) includes a first circuit (12, 14) for receiving an input signal; a second circuit (18) for setting a predetermined number of thresholds using a predetermined number of preamplifiers (60) with weighted unit current sources (66) in each of the preamplifier outputs; and a third circuit (20) for comparing the input to the thresholds. In the preferred embodiment, the ADC (10) includes trimmable current sources (66). The ADC (10) of the present invention also includes an improved comparator circuit (62).

Abstract: One embodiment of the present invention provides a system for detecting a valid clock signal at a clock receiver. The system operates by receiving a clock signal at the clock receiver, and directing the clock signal into a control input of a voltage-controlled variable resistor. Next, the system uses the voltage-controlled variable resistor to control a first current. A current mirror is then employed to create a second current from the first current. This second current passes through a resistor to produce a control voltage, which is amplified to produce a validity signal indicating whether or not the clock signal is valid. In one embodiment of the present invention, the system additionally uses at least one capacitor to filter out periodic fluctuations in the validity signal.

Abstract: A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of the input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.

Abstract: Disclosed is an impedance comparison integrated circuit. The integrated circuit includes a current mirror part, a discharging part, a differential amplification part and a first output part. The current mirror part provides current to a first and second input terminal, respectively, during a first interval of every period. The discharging part provides a discharging path to the first and second input terminals, respectively, during a second interval of every period. The differential amplification part performs a differential amplification on signals input from the first and second input terminals, respectively, during the first interval of every period. The first output part outputs a first output signal to the first output terminal in response to the differential amplification part. Accordingly, parasitic impedance difference between each parasitic impedance of the first and second input terminals is minimized, and input offset error is reduced, so that impedance sensing with high precision is possible.

Abstract: A circuit for optimizing the operation of a comparator capable of rail-to-rail operation and relatively high speed. The optimized comparator can output relatively narrow pulses in response to an input signal swinging between the rails of the power supply. Further, the comparator can provide an indication of an under voltage condition of an input signal with respect to a reference voltage. Also, the comparator can conserve power consumption by disabling those portions of the comparator that are not currently employed to resolve a high or low swing of the input signal.

Abstract: A multiphase comparator circuit includes a first differential stage; a first switching arrangement for connecting an output of the first differential stage to an input of a load circuit; and two or more regeneration stages. Each regeneration stage is connected to a load circuit and to the first switching arrangement. A clock-controlled second switching arrangement selectively provides an operating current to the regeneration stages. The first and second switching arrangements have switches that are driven so as to operate the regeneration stages in a manner temporally offset from each other.

Abstract: A differential signal reception device and method for supporting variable threshold levels. The device flexibly makes an input to the decision circuit appear to an outside driving circuit as if the decision circuit were a purpose-built input network supporting a fixed impedance input into either a floating or fixed DC termination voltage. The device further allows the internal decision process to support a variable threshold level when deciding logical 1/0 values and to attenuate the users input signal range for the purpose of making sure the range of the user's signals do not exceed the operating range of readily available decision circuit (limiting amplifier) integrated circuits.

Abstract: The present invention is a circuit comprising two series-coupled field effect transistor (FET) devices with a resistor network coupled in parallel forming a composite device (that can be substituted directly for a single FET device). In applications such as active loads or current sources, the composite device exhibits a greater breakdown voltage and superior high-frequency characteristics. The resistor network provides optimum direct current (DC) bias for depletion mode devices and superior high-frequency loading. Bandwidth and stability are both increased. Furthermore, this circuit is compatible with depletion mode FET processes having a single fixed threshold voltage.

Abstract: A comparator is provided with a pair of transistors which are continuously in ON state, in which a switch unit constructed of a diode pair, for switching a current path in response to a high/low relationship between a voltage level of an input signal and a voltage level of a reference voltage, and a unit for converting a current into a voltage level are provided between emitter terminals of the transistor pair.

Abstract: A signal amplitude comparator which includes a first differential input circuit that is biased, is configured to receive an input voltage and is configured to generate a first output current that is a non-linear function of the input voltage, a second differential input circuit which is biased similarly to the first differential input circuit, is configured to receive a reference input voltage and is configured to generate a second output current that generally tracks process, temperature and supply variation, and a comparator which is connected to the first differential input circuit and the second differential input circuit and is configured to receive the first output current from the first differential input circuit and the second output current from the second differential input circuit. The comparator is configured to compare the first and second output currents and generate an output which indicates whether the input voltage exceeds a pre-determined threshold value.

Abstract: A signal voltage detection circuit is provided to include a differential amplifier a differential amplifier having first and second driver transistors to which a reference voltage and a signal voltage to be detected are input respectively, a current mirror circuit configured to generate an output current corresponding to a detection output of the differential amplifier, a current-to-voltage conversion circuit configured to convert a change in the output current of the current mirror circuit into a voltage and for outputting the voltage converted, a latch circuit to which an output of the current-to-voltage conversion circuit is transferred and in which the output is held, and a capacitive load element connected to an input node of the current-to-voltage conversion circuit.

Abstract: To establish whether a precharged node remains isolated or alternatively is subject to discharge, the conventional circuit allows uncertainty. For a period after evaluation starts, the conventional circuit will give a tentative result that may subsequently turn out to be wrong. During evaluation power is dissipated. A differential offset dynamic comparator and timing circuit are used to evaluate whether the node is being discharged. Because the comparator has an offset, much smaller deviations from the precharge potential can be sensed: because it is dynamic, it does not consume steady state current. The timing circuit permits precise knowledge of when to look at the output: before the timing period has elapsed, the result is known to be invalid.

Abstract: A circuit for extracting a common mode data signal applied to a plurality of component signals. The circuit including a current driver, resistance, and a common mode extraction unit connected in series. The extraction unit has an impedance substantially proportional to the average voltage of the applied input signals and may be formed of a series of matched transistors connected in parallel. In a single-path configuration, when pairs of differential signals are applied, the voltage drop across the extraction unit is proportional to the overall common mode signal level carried by the differential signal components. In a multiple path configuration, two or more extraction units may be connected to a common current driver and configured in a differential amplifier configuration.

Abstract: An input buffer circuit for use with an analog-to-digital converter is provided. The input buffer circuit comprises a first amplifier configured with a second amplifier to improve the overall gain of the input buffer circuit. The first amplifier comprises a differential pair of transistors configured with a second pair of transistors comprising a current mirror arrangement, wherein one of the differential pair of transistors of the first amplifier is configured in a diode-connected arrangement to provide a first feedback loop, while the second amplifier comprises a differential pair of transistors configured with another pair of transistors also comprising a current mirror arrangement, with the second amplifier and the current mirror arrangement of the first amplifier comprising a second feedback loop.

Abstract: A fully differential continuous-time current-mode high-speed complimentary metal oxide semiconductor comparator is disclosed. The comparator includes an input and an output; a pre-amplifier clement coupled to each respective one of the plurality of inverters; an application switch operative to couple the pre-amplifier element to the input of a corresponding one of the plurality of inverters, the application switch having a first duty cycle; a current source operative to provide a bias current; and a bias switch operative to couple the bias current to each of the plurality of inverters, the bias switch having a duty cycle that is complementary to the duty cycle of the application switch, wherein the output of each of the plurality of inverters is pulled to about one-half the maximum output voltage level before a comparison between input signals is performed.

Abstract: A CMOS ECL input buffer buffers signals from an ECL circuit to a CMOS circuit. The CMOS ECL input buffer has a CMOS differential amplifier. A CMOS input circuit is coupled between a buffer input that receives the ECL circuit and a first input of the CMOS differential amplifier. The CMOS input circuit couples an input signal to the first input of the CMOS differential amplifier, and the input signal has an input voltage swing. A reference circuit provides a reference to a second input of the CMOS differential amplifier. The reference is nominally set at substantially a midpoint of the input voltage swing. A CMOS output circuit is coupled between the output of the CMOS differential amplifier and the buffer output, and is arranged to provide an output signal to the buffer output. The output signal, in response to the CMOS differential amplifier, swings between a typical CMOS positive source voltage and ground as the input signal traverses the reference.

Abstract: A control circuit for a power MOSFET includes a voltage divider for dividing an input voltage, a fixed voltage generator for generating a fixed voltage, a comparator having a differential pair including first and second depletion transistors each receiving the divided voltage or the fixed voltage and a current mirror including first and second enhancement transistors connected in series with the first and second depletion transistors, respectively, an inverter for receiving the output from the comparator, and a power MOSFET controlled for the ON/OFF control thereof by the inverter.

Abstract: A differential circuit to be used as a latch-up for asymmetric-double-gate complementary metal oxide semiconductor (DGCMOS) devices. The differential circuit includes an asymmetric-DGCMOS device having the weak gates tied to input circuitry and strong gates that are used in cross-coupling.

Abstract: A power controlled input receiver, in accordance with the present invention, includes a receiver circuit including a first current source and a second current source. The first current source supplies current in a power down mode of the receiver and the second current source is enabled for supplying current in a normal operation mode. A signal state detection circuit is coupled to the receiver circuit for detecting an active input signal, and a control signal generator is coupled to the signal state detection circuit for generating an enable signal to enable the second current source when the active input signal is detected.

Abstract: An integrated circuit including a comparator circuit and a vertical voltage control switch element formed on a single substrate. The comparator circuit including a differential amplifier circuit having a current mirror circuit M, a differential amplifier circuit D1 with two current paths L1 and L2, and an inverter INV. The output section of the current mirror circuit M is used as a constant current source for the differential amplifier circuit. The current mirror circuit M includes a load MOS transistor 1, a MOS transistor 2 constituting an input section, and a MOS transistor 10 constituting an output section. The current path L1 of the differential amplifier circuit D1 includes a load MOS transistor 11, an amplifying depletion type MOS transistor 13, and an input terminal in1. Similarly, the current path L2 includes a load MOS transistor 12, an amplifying depletion type MOS transistor 14, and an input terminal in2. The inverter INV is constructed with a load MOS transistor 3 and a switching transistor 4.

Abstract: An input buffer having a differential amplifier 3 includes a protection circuit 4 located between an input terminal 1 and the differential amplifier. The protection circuit serves to protect a MOS transistor 5 constituting the differential amplifier when a high voltage is applied to the input terminal of the input buffer. The protection circuit is an N-channel type MOS transistor with a drain electrode connected to the input terminal, a source electrode connected to a gate terminal of the MOS transistor 5 constituting the differential amplifier 3 and a gate terminal supplied with a power source voltage Vcc. In this configuration, the input buffer prevents occurrence of an unnecessary through current.

Abstract: A comparator circuit for comparing a differential input signal to a reference signal. A differential MOS transistor pair is provided having respective gates for receiving the positive and negative components of the differential input signal. A tail current source is coupled to the common sources of the transistor pair, with the current magnitude being related to the reference signal magnitude. The first and second transistors are made differently, typically by making the sizes different, so that the gate-source voltages differ when the transistor currents are equal. A comparator stage provides a digital output which changes state when the transistor currents are equal, with the difference in gate-source voltage representing the comparator trip voltage, a trip voltage related to the magnitude of the reference signal.

Abstract: An input buffer for use in an integrated circuit having a VCC voltage supply and a VSS voltage supply. The input buffer includes a p-channel field effect transistor (FET) having a source region coupled to the VCC voltage supply, a drain region coupled to a bias circuit, and a gate electrode coupled to an input terminal. The bias circuit maintains a voltage at the drain region of the p-channel FET which is slightly greater than the VSS supply voltage when a logic high voltage is applied to the input terminal. In an alternate embodiment, the input buffer includes an n-channel FET having a drain region coupled to the VCC voltage supply, a source region coupled to the output terminal and a gate electrode coupled to the input terminal. The bias circuit maintains a voltage at the source of the n-channel FET which is greater than the VSS supply voltage when a logic low voltage is applied to the input terminal.

Abstract: This invention relates to an artificial neural network (ANN), particularly to a neuron circuit and its activation function including the derivative. The neuron circuit capable of generating an adjustable sigmoid-like function and a good approximation of its derivative, comprises: a current generator for generating a current; a current-controlled transistor for changing an output voltage according to the current from the current generator; and at least one differential pair of transistors for generating the adjustable sigmoid-like function output and the good approximation of its derivative by the changed output voltage.

Abstract: In an isolator circuit, a first differential pair circuit compares voltages of two input signals with each other, and, in accordance with the ratio of the voltages, currents flow through two resistors respectively connected to two output terminals of the first differential pair circuit. A current comparison circuit compares the currents respectively flowing through the two resistors, and outputs a voltage corresponding to a result of the comparison. A second differential pair circuit compares the voltage output from the current comparison circuit with a reference voltage, and a negative feedback is conducted so that the currents flowing through the two resistors are equal to each other. Unlike the conventional art, an isolator circuit can be configured without disposing buffer circuits.

Abstract: A differential logic gate providing complimentary input and complimentary output operation. Transistors (50,52) provide the differential input and emitter follower transistors (54,62) provide the complimentary outputs. Enhanced output high logic levels are enabled by PNP transistors (40,46). PNP transistors (40,46) supply base current drive to transistors (54,62) which boosts the output logic high voltage values presented at terminals (Q,Q-compliment) by reducing collector resistor voltage drop across resistors (42,44). PNP transistors (40,46) remain in their respective conductive states due to voltage regulators (38,48) to provide for faster operation.

Abstract: A transimpedance circuit adapted for use in a subscriber line interface circuit includes sense resistors installed in closed loop, negative feedback paths of respective sense amplifiers. Voltage drops across the sense resistors are applied to first and second differential coupling circuits for applying differential currents to complementary polarity inputs of an operational amplifier. The inputs of the amplifier are also coupled to a linearity compensator, that is configured to provide sufficient overhead voltages in the presence of worst case voltage swing conditions. The compensator has a differential amplifier configuration, that closes a negative feedback loop from the output of the amplifier and one of its inputs, relative to a reference voltage balancing path coupled to the amplifier's other (complementary) input.

Abstract: An integrated differential buffer circuit and its method of operation are described in which the buffer circuit has an internal bias line for controlling the supply of voltage to the buffer circuit. When the buffer circuit is first enabled, a start voltage is initially applied to the bias line and then removed to ensure proper operation of the buffer circuit when first enabled.

Abstract: A transimpedance circuit adapted for use in a subscriber line interface circuit includes sense resistors installed in closed loop, negative feedback paths of respective sense amplifiers. Voltage drops across the sense resistors are applied to first and second differential coupling circuits for applying differential currents to complementary polarity inputs of an operational amplifier. The inputs of the amplifier are also coupled to a linearity compensator, that is configured to provide sufficient overhead voltages in the presence of worst case voltage swing conditions. The compensator has a differential amplifier configuration, that closes a negative feedback loop from the output of the amplifier and one of its inputs, relative to a reference voltage balancing path coupled to the amplifier's other (complementary) input.

Abstract: A CMOS differential amplifier is provided comprising a current supply coupled to a first terminal of a power supply. A first CMOS transistor is provided having a first source, a first gate, and a first drain coupled to the current supply. A second CMOS transistor is also provided having a second source, a second gate, and a second drain coupled to the current supply. The first and second gates are inputs to the CMOS differential amplifier. A resistance is coupled between a second terminal of the power supply and the first source of the first transistor and the second source of the second transistor to improve common-mode and ground noise suppression.