With Differential Amplifier Patents (Class 327/96)
  • Patent number: 10459145
    Abstract: A waveguide apparatus has in combination: a light pipe with an optical axis for guiding light therethrough; a light coupling element in optical contact with an elongate portion of the reflecting surface of the light guide; and an optical waveguide in optical contact with the coupling element.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: October 29, 2019
    Assignee: DigiLens Inc.
    Inventors: Milan Momcilo Popovich, Jonathan David Waldern, Alastair John Grant
  • Patent number: 10454591
    Abstract: An embodiment includes a track and hold amplifier device. A device may include an emitter follower transistor coupled to each of an input and an output. The device may also include a charging node coupled between the output and a voltage supply, wherein the charging node is also coupled to the input via the emitter follower transistor. Further, the device may include a cascode switch coupled to each of the input and the output. The cascode switch may be configured to cause the emitter follower transistor to operate in a conductive state and charge the charging node during a track mode. The cascode switch may also be configured to cause the emitter follower transistor to operate in a non-conductive state to isolate the charging node from the input during a hold mode. The cascode switch may include a MOS-HBT transistor combination operating in class AB mode.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: October 22, 2019
    Assignee: FINISAR CORPORATION
    Inventors: Sorin Petre Voinigescu, Konstantinos Vasilakopoulos
  • Patent number: 10298216
    Abstract: A semiconductor device is provided that includes an amplification circuit, a downstream circuit, and a clipping circuit. The amplification circuit includes a sampling capacitor, a feedback capacitor, and an operational amplifier circuit. The sampling capacitor holds air input signal on which sampling is performed, as a signal whose reference is a first reference voltage. The signal that is held in the sampling capacitor is transferred to the feedback capacitor. The operational amplifier circuit amplifies the signal that is held in the sampling capacitor, according to a ratio between values of the sampling capacitor and the feedback capacitor, and outputs the amplified signal, as a signal whose reference is a second reference voltage. The clipping circuit limits a voltage of an output signal of the operational amplifier circuit to a predetermined voltage or below.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: May 21, 2019
    Assignee: OLYMPUS CORPORATION
    Inventors: Yasunari Harada, Masato Osawa, Hideki Kato
  • Patent number: 10192630
    Abstract: The track-and-hold circuit includes a switching circuit and a plurality of storage devices. The switching circuit responsive to an input signal applies a representation of the input signal to the storage devices in a track mode and blocks a signal path between the input signal and the storage device in a hold mode such that a transition from the track mode to a hold mode causes the storage devices to store a time sample of the input signal. An acquisition glitch suppression circuit includes a replica amplifier coupled to the switching circuit that senses a differential voltage across the storage devices. A switched clamping circuit clamps inputs of the switching circuit to the sensed differential voltage in the hold mode such that the initial condition of switching transistors of the switching circuit are approximately identical prior to a hold-to-track transition to mitigate differential acquisition glitch.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: January 29, 2019
    Assignee: HITTITE MICROWAVE LLC
    Inventor: Michael J. Hoskins
  • Patent number: 10103717
    Abstract: The present disclosure provides a detailed description of techniques for implementing a low power buffer with dynamic gain control. More specifically, some embodiments of the present disclosure are directed to a buffer having a gain boost configuration and a current shunt circuit to control the gain of a respective gain boosting transistor of the gain boost configuration. The current shunt circuit and resulting gain are dynamically controlled by a gain control signal such that the buffer gain can be adjusted to within an acceptable range of the target gain for the current operating and device mismatch conditions. In one or more embodiments, the gain boost configuration with dynamic gain control can be deployed in a full differential implementation. Both analog and digital dynamic calibration and control techniques can be used to provide the gain control signals to multiple current shunt circuits and multiple buffers.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: October 16, 2018
    Assignee: INPHI CORPORATION
    Inventors: James Lawrence Gorecki, Han-Yuan Tan
  • Patent number: 9837998
    Abstract: The present disclosure provides a detailed description of techniques for implementing a low power buffer with dynamic gain control. More specifically, some embodiments of the present disclosure are directed to a buffer having a gain boost configuration and a current shunt circuit to control the gain of a respective gain boosting transistor of the gain boost configuration. The current shunt circuit and resulting gain are dynamically controlled by a gain control signal such that the buffer gain can be adjusted to within an acceptable range of the target gain for the current operating and device mismatch conditions. In one or more embodiments, the gain boost configuration with dynamic gain control can be deployed in a full differential implementation. Both analog and digital dynamic calibration and control techniques can be used to provide the gain control signals to multiple current shunt circuits and multiple buffers.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: December 5, 2017
    Assignee: INPHI CORPORATION
    Inventors: James Lawrence Gorecki, Han-Yuan Tan
  • Patent number: 9519604
    Abstract: Systems and methods for frequency control on a bus through superposition are disclosed. In one embodiment, instead of adding pins or increasing the operating frequency of the bus, three signals are placed on lines within the bus using superposition. In this fashion, three bits may be sent over two conductors, effectively obviating the need for an additional pin and effectively increasing the frequency of bit transmission without having to increase the clock speed.
    Type: Grant
    Filed: April 11, 2014
    Date of Patent: December 13, 2016
    Assignee: QUALCOMM Incorporated
    Inventor: Timothy Mowry Hollis
  • Patent number: 9231542
    Abstract: A fully differential amplifier performs common-mode voltage control while having reduced sensitivity to random offsets and mismatches and improved common-mode control loop bandwidth. The amplifier disclosed comprises an additional common-mode control sub-amplifier, which senses common-mode voltage of the fully differential main amplifier at nodes within the continuous-time signal path feedback network, compares the common-mode voltage sensed with a reference voltage, and regulates depending on the result of the comparison the output common-mode voltage via the existing continuous signal path feedback network. Furthermore the internal common-mode control can be implemented in such a manner as to provide a feed-forward transconductance function in addition to common-mode control if desired. Moreover it is possible to use feedback from other amplifier stages in an amplifier chain to implement common-mode feedback.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: January 5, 2016
    Assignee: Dialog Semiconductor (UK) Limited
    Inventor: Andrew Myles
  • Patent number: 8952729
    Abstract: A sample and hold circuit and a method for sampling a signal are disclosed. The sample and hold circuit includes first and second switches, first, second, and third capacitors, and an amplifier. The amplifier receives a signal to be sampled on a first input. The first capacitor is characterized by a first capacitance and has a first terminal connected to an output of the amplifier by the first switch. The second capacitor is characterized by a second capacitance and has a second terminal connected to the output of the amplifier by the second switch. The third capacitor connects the first and second terminals. The amplifier is configured to form a capacitive transimpedance amplifier having the third capacitor as a feedback circuit when the first switch is in a non-conducting state and the second switch is in a conducting state.
    Type: Grant
    Filed: April 3, 2013
    Date of Patent: February 10, 2015
    Assignee: BAE Systems Imaging Solutions Inc.
    Inventors: Boyd Fowler, Peter Bartkovjak
  • Patent number: 8942313
    Abstract: An open loop envelope tracking system calibration technique and circuitry are proposed. A radio frequency power amplifier receives a modulated signal. An envelope tracker power converter generates a modulated power amplifier supply voltage for the radio frequency power amplifier based on a control signal derived from the modulated signal. A first output power and a second output power of the radio frequency power amplifier are measured when the control signal is respectively delayed by a first delay period and a second delay period. A sensitivity of the output power of the radio frequency power amplifier is near a maximum near the first delay period and the second delay period. The first delay period and/or the second delay period are adjusted until the first output power substantially equals the second output power. The first delay period and the second delay period are used to obtain a calibrated fine tuning delay offset.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: January 27, 2015
    Assignee: RF Micro Devices, Inc.
    Inventors: Nadim Khlat, Karl Francis Horlander
  • Patent number: 8854085
    Abstract: A compensation circuit for eliminating harmonic content resulting from a phase imbalance in a differential sampling circuit. The compensation circuit includes a pair of field effect transistors operating in saturation mode, each field effect transistor coupled in parallel with the differential switch of the sampling circuit, which operates in linear mode. The saturation region transistors across the differential switch allow the harmonic content to flow through the compensation circuit instead of the sampling capacitors of the sampling circuit.
    Type: Grant
    Filed: May 8, 2013
    Date of Patent: October 7, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Roswald Francis
  • Patent number: 8823564
    Abstract: A sampling circuit includes a continuous section which is a circuit for transmitting a continuous signal; a digital section for transmitting a signal which is sampled and quantized; and a sampling and holding section for transmitting a signal which is sampled but not quantized between the continuous section and the digital section. The sampling and holding section includes capacitors for accumulating charge generated by an input signal and plural switches for accumulating the charge in the capacitors. The plural switches receive plural clock signals having different operation timings and perform an ON/OFF operation in response to the supplied clock signals.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: September 2, 2014
    Assignee: Asahi Kasei Microdevices Corporation
    Inventors: Junya Nakanishi, Yutaka Nakanishi
  • Patent number: 8816887
    Abstract: A sampling circuit comprising: an input node; a first signal path comprising a first sampling capacitor and a first signal path switch in a signal path between the input node and a first plate of the first sampling capacitor; a second signal path comprising a second sampling capacitor and a second signal path switch in a signal path between the input node and a first plate of the second sampling capacitor, and a signal processing circuit for forming a difference between a signal sampled onto the first sampling capacitor and a signal sampled onto the second sampling capacitor.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: August 26, 2014
    Assignee: Analog Devices, Inc.
    Inventors: Christopher Peter Hurrell, Roberto Maurino
  • Patent number: 8810283
    Abstract: A circuit for sampling an analog input signal may include a transistor disposed on a substrate and a sampling capacitor coupled to one of the source and the drain of the transistor. The transistor may be disposed on a substrate that is coupled to ground. A source and a drain of the transistor may be disposed in a back gate of the transistor. The analog input may be supplied to one of the source and the drain of the transistor, and the back gate may receive a back gate voltage having a value that is lower than ground.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: August 19, 2014
    Assignee: Analog Devices, Inc.
    Inventors: Joseph M. Hensley, Franklin M. Murden
  • Publication number: 20140070971
    Abstract: A track-and-hold circuit comprises at least first and second amplifier stages, and switched capacitor circuitry coupled between the first and second amplifier stages. In a track mode of operation of the track-and-hold circuit, the switched capacitor circuitry is configured to decouple inputs of the second amplifier stage from respective outputs of the first amplifier stage and to couple the inputs of the second amplifier stage to a common mode voltage via respective first and second capacitors. In a hold mode of operation of the track-and-hold circuit, the switched capacitor circuitry is configured to couple the inputs of the second amplifier stage to the respective outputs of the first amplifier stage via the respective first and second capacitors. Multiple instances of the track-and-hold circuit may be implemented in parallel in a time-interleaved analog-to-digital converter.
    Type: Application
    Filed: September 7, 2012
    Publication date: March 13, 2014
    Applicant: LSI Corporation
    Inventor: Oleksiy Zabroda
  • Patent number: 8629695
    Abstract: The present invention discloses a multi-stage sample and hold (S/H) circuit that includes: a first S/H circuit for sampling a sensing signal of a sensor multiple times and accumulating them into a first sampled signal, and outputting the first sampled signal; and a second S/H circuit for receiving the plurality of first sampled signals and accumulating them into a second sampled signal. As a result, when one or more first sampled signals are saturated due to instantaneous noise, the second sampled signal is not saturated, thereby increasing the noise tolerance of the multi-stage S/H circuit.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: January 14, 2014
    Assignee: Egalax—Empia Technology Inc.
    Inventors: Chin-Fu Chang, Guang-Huei Lin
  • Patent number: 8624632
    Abstract: Sense amplifier-type latch circuits are provided which employ static bias currents for enhancing operating frequency. For example, a sense amplifier-type latch circuit includes a latch circuit that captures and stores data during an evaluation phase of the sense amplifier-type latch circuit, and outputs the stored data to differential output nodes. An input differential transistor pair has drains connected to the latch circuit and sources commonly connected to a coupled source node. A static bias current circuit is connected to the coupled source node to provide a static bias current which flows through the differential transistor pair and cross-coupled inverters of the latch during a precharge phase. A switch device, which is connected to the coupled source node, is turned off during the precharge phase and turned on during the evaluation phase by operation of a clock signal to increase current flow through the differential transistor pair.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: January 7, 2014
    Assignee: International Business Machines Corporation
    Inventor: John F. Bulzacchelli
  • Patent number: 8624635
    Abstract: The present invention provides a circuit for concurrent integration of multiple differential signals. The circuit comprises a plurality of Stage 1 integration circuits arranged in an array and a plurality of Stage 2 integration circuits arranged in an array. Each of the Stage 1 integration circuits is configured to concurrently integrate an input signal, and to send out a Stage 1 positive signal and a Stage 1 negative signal that is reverse to the Stage 1 positive signal. Each of the Stage 2 integration circuits is configured to integrate a differential signal from a Stage 1 positive signal sent from a corresponding Stage 1 integration circuit and a Stage 1 negative signal sent from another Stage 1 integration circuit next to the corresponding Stage 1 integration circuit to output a Stage 2 signal.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: January 7, 2014
    Assignee: Egalax—Empia Technology Inc.
    Inventors: Chin-Fu Chang, Guang-Huei Lin
  • Patent number: 8610467
    Abstract: A sample and hold circuit is provided. The circuit includes a plurality of switches, a first capacitor, an operational amplifier having a first input selectively coupled to the first capacitor and an output, a second capacitor and a third capacitor both selectively coupled to the first capacitor and both selectively coupled between the first input of the operational amplifier and the output of the operational amplifier, wherein the plurality of switches are configured to receive a plurality of control signals such that the first capacitor is configured to sample an input signal in a sample phase and to transfer a charge to one of the second capacitor and the third capacitor in a hold phase, and the second capacitor and third capacitor are configured to alternate between holding the transferred charge and resetting in any back-to-back hold phases.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: December 17, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mohammad Nizam U. Kabir, Douglas A. Garrity, Rakesh Shiwale
  • Publication number: 20130307587
    Abstract: A sample and hold circuit comprises an input stage amplifier circuit for amplifying an input signal and a hold circuit for holding an output signal of the input stage amplifier circuit, with a sampling clock signal as a trigger, is further provided with a bias current switching circuit for switching a bias current of the input stage amplifier circuit to another circuit that is functionally independent of the sample and hold circuit, in a case where the hold circuit is in a hold period, to supply the bias current to the circuit.
    Type: Application
    Filed: July 24, 2013
    Publication date: November 21, 2013
    Applicant: NEC CORPORATION
    Inventor: HIDEMI NOGUCHI
  • Patent number: 8581636
    Abstract: Sample-and-hold circuits typically operate at maximum speed when the sampling phase is much shorter than the holding phase. Thus, a device driving the sampling capacitor is disconnected most of the time. Methods and apparatus use the holding phase to store the full charge required by the sampling capacitor to track the amplifier output in at least two “boost” capacitors configured such that when the sampling capacitor is switched to the driver, the boost capacitors are also switched to the driver. Thus, the sampling capacitor is almost instantly charged to the required voltage, and the driver needs to supply only any remaining “error” charge, avoiding delays due to driver output slewing.
    Type: Grant
    Filed: December 24, 2011
    Date of Patent: November 12, 2013
    Assignee: ST-Ericsson SA
    Inventor: Paul Mateman
  • Patent number: 8575970
    Abstract: An operational circuit includes: a gain control circuit arranged to provide a gain value upon an input signal according to a set of control signals, wherein the gain control circuit includes a first resistor-based network and a second resistor-based network; an operational amplifier coupled to the gain control circuit and arranged to generate an output signal according to the input signal and the gain value; and a first capacitor coupled to the operational amplifier and arranged to hold the output signal between a first input terminal and a first output terminal of the operational amplifier, wherein when the operational circuit is operating, a first terminal of the first capacitor is consistently coupled to the first input terminal of the operational amplifier, and a second terminal of the first capacitor is consistently coupled to the first output terminal of the operational amplifier.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: November 5, 2013
    Assignee: Mediatek Inc.
    Inventors: Hung-Chieh Tsai, Yu-Hsin Lin, Chi-Lun Lo, Jong-Woei Chen
  • Patent number: 8513982
    Abstract: A sample and hold circuit is provided. The circuit includes a first switch configured to receive an input, a second switch coupled to a second end of the first switch, a first capacitor coupled to the second end of the first switch, a third switch coupled to a second end of the first capacitor, a fourth switch coupled between the second end of the first capacitor and ground, an op-amp having a first input coupled to the second end of the third switch and a second input connected to ground and an output coupled to the second end of the second switch, a fifth switch coupled to a second end of the third switch, a second capacitor coupled between the output of the op-amp and a second end of the fifth switch, and a sixth switch coupled between the second end of the second capacitor and ground.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: August 20, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Douglas A. Garrity, Ahmad H. Atriss
  • Patent number: 8508257
    Abstract: An architecture of an integrated circuit allows for the canceling of noise sampled on a capacitor in the integrated circuit, after an input signal has already been sampled. Thermal noise correlated with an arbitrary input signal may be canceled after selectively controlling a plurality of switching devices during a sequence of clock phases. An auxiliary capacitor may be used to store a voltage equal to the thermal noise and enable the cancellation of the thermal noise from the sampled signal in conjunction with a noise cancellation unit.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: August 13, 2013
    Assignee: Analog Devices, Inc.
    Inventors: Ronald A. Kapusta, Colin Lyden, Haiyang Zhu
  • Patent number: 8497731
    Abstract: A low pass filter circuit includes an amplifier having a single-ended output. A first line and a second line are arranged to receive a differential signal. A first switch selectively connects the first line to a first input of the amplifier in a first cycle of operation having a first observation window. A second switch selectively connects the second line to a second input of the amplifier in a second cycle of operation having a second observation window that is at least partially coincident with the first observation window. A signal measuring stage that is supplied with a modulated input signal generates the differential signal. The signal measuring state has an input switch to reverse a polarity of the differential signal applied to the first and second lines of the low pass filter circuit.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: July 30, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Joel C. Beckwith, Dejan Mijuskovic
  • Patent number: 8488032
    Abstract: An interface capable of suppressing parasitic capacitance effects includes an array of switches switched in response to a switching signal. The interface suppresses effects of parasitic capacitance included in a bus, which transmits a reset signal and an image signal output from an image sensor. The suppressed parasitic capacitance effects suppress distortion of a digital image signal.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: July 16, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-Sun Keel, Kwang Hyun Lee
  • Publication number: 20130162299
    Abstract: Techniques pertaining to an analog sample circuit are disclosed. One embodiment of the analog sample circuit shows characteristics of low distortion and high linearity, which can be used in many circuits including integrated circuits (IC).
    Type: Application
    Filed: December 23, 2011
    Publication date: June 27, 2013
    Inventor: Chuan GONG
  • Publication number: 20130135013
    Abstract: The present invention discloses a multi-stage sample and hold (S/H) circuit that includes: a first S/H circuit for sampling a sensing signal of a sensor multiple times and accumulating them into a first sampled signal, and outputting the first sampled signal; and a second S/H circuit for receiving the plurality of first sampled signals and accumulating them into a second sampled signal. As a result, when one or more first sampled signals are saturated due to instantaneous noise, the second sampled signal is not saturated, thereby increasing the noise tolerance of the multi-stage S/H circuit.
    Type: Application
    Filed: September 11, 2012
    Publication date: May 30, 2013
    Applicant: EGALAX_EMPIA TECHNOLOGY INC.
    Inventors: Chin-Fu Chang, Guang-Huei Lin
  • Patent number: 8415985
    Abstract: Circuits and methods for sampling differential input signals having wide input swings including voltages below ground potential, and capable of operating on a single positive supply voltage are disclosed. In an embodiment, the circuit includes a first input switch circuit and a second input switch circuit, a sample and hold circuitry and an operational amplifier. Each of the first and second input switch circuits includes serially connected PMOS switch and NMOS switch for receiving a differential input signal. The sample and hold circuitry includes a first sampling capacitor, a second sampling capacitor and a plurality of switches. The switches are configured to provide the differential input signal to the sampling capacitors for the sampling in a sample phase, and are configured to provide the sampled differential input signal at an output of the operational amplifier in a hold phase.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: April 9, 2013
    Assignee: Texas Instruments Incorporated
    Inventor: Rajesh Cheeranthodi
  • Patent number: 8368430
    Abstract: A sample and hold circuit includes an operational amplifier; a sampling capacitor configured to sample input voltages at a plurality of different timings; an adding/subtracting unit configured to perform an adding or subtracting operation of the input voltages sampled by the sampling capacitor; and an offset voltage removing unit configured to remove an input offset voltage component of the operational amplifier from a voltage obtained by the adding or subtracting operation. The operational amplifier is configured to produce an output by holding the voltage from which the input offset voltage component of the operational amplifier has been removed by the offset voltage removing unit.
    Type: Grant
    Filed: October 22, 2010
    Date of Patent: February 5, 2013
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Hikaru Watanabe
  • Patent number: 8350738
    Abstract: An exemplary differential track and hold amplifier includes a track stage including first and second linearized pairs connected in series at their respective inputs and in parallel at their respective outputs. The differential track and hold amplifier also includes a hold stage selectively coupled to the outputs of the first and second linearized pairs. The hold stage includes a unity gain buffer with feedback having a hold capacitor interconnected across its outputs. The differential track and hold amplifier also includes an output buffer coupled to the outputs of the hold stage. An exemplary analog-to-digital converter includes a differential track-and-hold amplifier, a voltage ladder, and a plurality of slices.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: January 8, 2013
    Assignee: International Business Machines Corporation
    Inventors: Mihai Adrian Tiberiu Sanduleanu, Jean-Olivier Plouchart, Zeynep Toprak Deniz
  • Publication number: 20120274363
    Abstract: An architecture of an integrated circuit allows for the canceling of noise sampled on a capacitor in the integrated circuit, after an input signal has already been sampled. Thermal noise correlated with an arbitrary input signal may be canceled after selectively controlling a plurality of switching devices during a sequence of clock phases. An auxiliary capacitor may be used to store a voltage equal to the thermal noise and enable the cancellation of the thermal noise from the sampled signal in conjunction with a noise cancellation unit.
    Type: Application
    Filed: April 28, 2011
    Publication date: November 1, 2012
    Applicant: ANALOG DEVICES, INC.
    Inventors: Ronald A. KAPUSTA, Colin LYDEN, Haiyang ZHU
  • Patent number: 8295296
    Abstract: An HDMI cable carries high speed encoded data which are transmitted differentially over data channels, along with a clock. High-frequency loss and differential skew within a differential signal may be compensated by analog circuits embedded in the cable. These embedded circuits are tuned at production for best performance by observing the quality of the recovered analog signal. The embedded circuits are powered by a combination of power sources, both carried within the cable, and harvested from the high-speed signals themselves.
    Type: Grant
    Filed: July 18, 2007
    Date of Patent: October 23, 2012
    Assignee: Redmere Technology Ltd.
    Inventors: Aidan Gerard Keady, John Anthony Keane, Judith Ann Rea, Benjamin Griffin, John Martin Horan
  • Patent number: 8254402
    Abstract: An HDMI cable carries high speed encoded data which are transmitted differentially over data channels, along with a clock. High-frequency loss and differential skew within a differential signal may be compensated by analog circuits embedded in the cable. These embedded circuits are tuned at production for best performance by observing the quality of the recovered analog signal. The embedded circuits are powered by a combination of power sources, both carried within the cable, and harvested from the high-speed signals themselves. Methods are provided for deskewing, equalizing, and boosting the differential signals in the embedded circuits that are mounted on a PCB.
    Type: Grant
    Filed: February 17, 2009
    Date of Patent: August 28, 2012
    Assignee: Remere Technology Ltd.
    Inventors: Aidan Gerard Keady, John Anthony Keane, Judith Ann Rea, Benjamin Griffin, John Martin Horan
  • Publication number: 20120188109
    Abstract: An exemplary differential track and hold amplifier includes a track stage including first and second linearized pairs connected in series at their respective inputs and in parallel at their respective outputs. The differential track and hold amplifier also includes a hold stage selectively coupled to the outputs of the first and second linearized pairs. The hold stage includes a unity gain buffer with feedback having a hold capacitor interconnected across its outputs. The differential track and hold amplifier also includes an output buffer coupled to the outputs of the hold stage. An exemplary analog-to-digital converter includes a differential track-and-hold amplifier, a voltage ladder, and a plurality of slices.
    Type: Application
    Filed: January 20, 2011
    Publication date: July 26, 2012
    Applicant: International Business Machines Corporation
    Inventors: Mihai Adrian TIberiu Sanduleanu, Jean-Olivier Plouchart, Zeynep Toprak Deniz
  • Publication number: 20120169379
    Abstract: A voltage hold circuit includes four switches, an operational amplifier and a capacitor. By turning the switches on and off, the operational amplifier functions as a unity-gain buffer. In the normal operation mode, the positive input end of the operational amplifier is coupled to a node, and the output end of the operational amplifier is coupled to the capacitor. Thus the voltage of the capacitor is equal to the voltage of the node. In the power off mode, the positive input end of the operational amplifier is coupled d to the capacitor, and the output end of the operational amplifier is coupled to the node. Thus the voltage of the node is equal to the voltage of the capacitor. Therefore, the voltage hold circuit is able to hold the voltage of the node in the power down state.
    Type: Application
    Filed: March 18, 2011
    Publication date: July 5, 2012
    Inventors: Yu-Sheng Lai, Feng-Chia Chang
  • Patent number: 8149020
    Abstract: To provide a common-mode feedback circuit that feeds back signal corresponding to common-mode components of output terminal voltage of first and second amplifiers to input terminals of the first and second amplifiers via first and second passive elements connected to a common terminal, respectively.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: April 3, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hirotomo Ishii
  • Patent number: 8138804
    Abstract: A correlated double sampling (CDS) circuit for sampling first and second pixel signals, which are respectively transmitted via first and second data lines, in a pixel array. The CDS circuit includes first and second sampling circuits, an amplifier circuit and a control circuit. The control circuit controls the first sampling circuit to sample a reset level and a data level of the first pixel signal in a first sampling period, and controls the second sampling circuit to sample a reset level and a data level of the second pixel signal in a second sampling period. The control circuit controls the amplifier circuit to output the reset level and the data level of the first pixel signal in a first output period, and output the reset level and the data level of the second pixel signal in a second output period.
    Type: Grant
    Filed: August 3, 2009
    Date of Patent: March 20, 2012
    Assignee: Novatek Microelectronics Corp.
    Inventor: Kuo-Yu Chou
  • Patent number: 8111091
    Abstract: Examples of systems and methods are provided for tracking-and-holding an input signal. The system may produce a pair of differential voltage outputs responsive to a pair of differential voltage inputs. The system may couple, in response to a clock signal, an input amplifier circuit to an output circuit or decouple the input amplifier circuit from the output circuit. The system may couple the input amplifier to an electrical ground. The system may track values of a pair of differential voltage outputs when a switching circuit is in a closed position and to hold the values of the pair of differential voltage outputs constant when the switching circuit is in an open position.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: February 7, 2012
    Assignee: Semtech Corporation
    Inventor: Kevin William Glass
  • Publication number: 20110279148
    Abstract: A sample and hold circuit includes an operational amplifier; a sampling capacitor configured to sample input voltages at a plurality of different timings; an adding/subtracting unit configured to perform an adding or subtracting operation of the input voltages sampled by the sampling capacitor; and an offset voltage removing unit configured to remove an input offset voltage component of the operational amplifier from a voltage obtained by the adding or subtracting operation. The operational amplifier is configured to produce an output by holding the voltage from which the input offset voltage component of the operational amplifier has been removed by the offset voltage removing unit.
    Type: Application
    Filed: October 22, 2010
    Publication date: November 17, 2011
    Inventor: Hikaru WATANABE
  • Patent number: 8054105
    Abstract: A sample hold circuit and a method for sampling and holding a signal are provided. The sample hold circuit includes a sample unit, a direct current (DC) voltage elimination unit, and a hold unit. When the sample hold circuit is in a first state, the sample unit samples an input signal, and the DC voltage elimination unit lowers a predetermined percentage of the DC voltage in the input signal sampled by the sample unit. When the sample hold circuit is in a second state, the DC voltage elimination unit eliminates the residual percentage of the DC voltage, and the hold unit outputs the alternating current (AC) signal in the input signal sampled by the sample unit.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: November 8, 2011
    Assignee: Himax Media Solution, Inc.
    Inventor: Chih-Haur Huang
  • Patent number: 8044950
    Abstract: A driver circuit usable for a display panel can generate an output signal in response to an input pulse signal supplied to only one input signal terminal thereof. The driver circuit includes a pulse generating circuit for generating an output signal at the output terminal. The pulse generating circuit has a first and second differential input stage for respectively driving a push-pull construction of output transistors in response to the input pulse signal supplied through the input signal terminal with respect to the push-pull output, whereby to simplify the circuitry, operate at a high slew rate, and decrease electric current consumption.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: October 25, 2011
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Masanori Satou
  • Patent number: 8035422
    Abstract: The invention relates to a transconductance amplifier, providing current variations di=k·dv when it receives voltage variations dv. The amplifier comprises a first MOS transistor (MN4) whose drain provides differential currents (I?di, I+di). It comprises an output stage having a second transistor (MP5) of a type opposite to the first, whose source is linked to the drain of the first, whose gate is biased at a constant potential (Vref), and whose drain receives the current variations which are provided by the first transistor and which must be applied to a sampling capacitor.
    Type: Grant
    Filed: January 15, 2008
    Date of Patent: October 11, 2011
    Assignee: Commissariat A l'Energie Atomique
    Inventor: James Wei
  • Publication number: 20110210764
    Abstract: A double switched track-and-hold circuit includes an input buffer having a first switched amplifier circuit for passing an input signal in a track mode and isolating the input signal from a buffer output in a hold mode, and a track-and-hold core circuit responsive to the input buffer and having a second switched amplifier circuit for tracking the input signal in a track mode and isolating the input signal from a track-and-hold output in a hold mode. The first and second switching amplifier circuits turn off approximately simultaneously during the hold mode to provide enhanced isolation.
    Type: Application
    Filed: August 17, 2010
    Publication date: September 1, 2011
    Inventor: Michael J. Hoskins
  • Patent number: 7990185
    Abstract: According to one embodiment of the invention, a programmable finite impulse response (FIR) filter is implemented with differential isolation circuits to isolate parasitic capacitance from attenuating an output signal at both first and second differential output terminals of the FIR filter. The FIR includes a track and hold circuit and a summing circuit that provides operational advantages to the FIR filter.
    Type: Grant
    Filed: May 12, 2008
    Date of Patent: August 2, 2011
    Assignee: Menara Networks
    Inventors: Kelvin Tran, Matthias Bussmann, Lloyd Linder, Salam Elahmadi, Harry Tan
  • Patent number: 7983362
    Abstract: Receiver architectures and bias circuits for a data processor are provided. A receiver architecture includes a linear receiver having a first input node for a data (DQ) signal, a second input node for a reference voltage, and output nodes for a differential output signal. The linear receiver compares the DQ signal to the reference voltage, and generates the differential output signal in response to the comparison. A sense amplifier is coupled to the linear receiver. The sense amplifier has input nodes connected to the output nodes of the linear receiver, and an output node for a binary output signal having voltage characteristics compatible with the processor. The sense amplifier transforms the differential output signal into the binary output signal. The receiver architecture also includes a programming architecture coupled to the linear receiver to set operating characteristics of the linear receiver.
    Type: Grant
    Filed: April 10, 2008
    Date of Patent: July 19, 2011
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Shawn Searles, Grace Chuang, Christopher M. Kurker, Curtis M. Brody
  • Patent number: 7982526
    Abstract: Exemplary embodiments of the disclosure include adaptively generating a bias current for a switched-capacitor circuit. An exemplary apparatus includes a first phase signal and a second phase signal operating at a sampling rate. An asserted time of the first phase signal and an asserted time of the second phase signal are separated by a predefined non-overlap time. The apparatus also includes a switched-capacitor circuit with a plurality of switched capacitors operably coupled to the first phase signal and the second phase signal. An amplifier is operably coupled to the switched-capacitor circuit and has a response time inversely proportional to an adaptive bias current. A bias generator is coupled to the amplifier and operates to modify the adaptive bias current responsive to the asserted time of the first phase signal.
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: July 19, 2011
    Assignee: QUALCOMM, Incorporated
    Inventor: Chun C. Lee
  • Patent number: 7973570
    Abstract: A sample-and-hold circuit (100) is provided that that includes a sample-and-hold switch (125), an integrator circuit (180) designed to generate an output voltage (VOUT) signal, and a bias voltage (VBIAS) source (185). The sample-and-hold switch (125) incldues a first switch (130), a second switch (140), and a third switch (150). The first switch (130) has a first gate (132), a first source (134) and a first drain (134), the second switch (140) has a second gate (142), a second source (144) electrically coupled to a bulk region (147), and a second drain (146), and the third switch (150) has a third gate (152), a third drain (154), and a third source (156) coupled to the first source (136). The integrator circuit (180) includes an output operational amplifier (170) having an inverting input (V?) (172) coupled to the second drain (146) and a non-inverting input (V+).
    Type: Grant
    Filed: August 14, 2009
    Date of Patent: July 5, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: John M. Pigott, Sergey S. Ryabchenkov
  • Patent number: 7965110
    Abstract: The invention relates to sample-and hold modules, and notably those which are intended to be placed upstream of an analog-digital converter. The sample-and-hold module conventionally comprises a differential pair of transistors, a follower transistor and a storage capacitor. The follower transistor is turned on during a sampling phase by the application of an emitter current by means of a first current switch and can be disabled during a hold phase by the application of a disabling voltage to its base. The sample-and-hold module operates according to the invention with a hold phase beginning at the same time as the end of a sampling phase and terminating before the start of a new sampling phase. Switching spikes are thus avoided at the transition between the end of a hold phase and the start of a new sampling phase.
    Type: Grant
    Filed: March 3, 2008
    Date of Patent: June 21, 2011
    Assignee: E2V Semiconductors
    Inventor: Richard Morisson
  • Patent number: 7932767
    Abstract: A technique for increasing the charge storage capacity of a charge storage device without changing its inherent charge transfer function. The technique may be used to implement a charge domain signal processing circuits such as Analog to Digital Converters (ADCs) used in digital radio frequency signal receivers.
    Type: Grant
    Filed: December 8, 2008
    Date of Patent: April 26, 2011
    Assignee: Kenet, Inc.
    Inventors: Edward Kohler, Michael P. Anthony