Having Selection Between Plural Continuous Waveforms Patents (Class 327/99)
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Patent number: 12081200Abstract: Provided is a clock switching device including a first latch circuit, a second latch circuit, and a switching circuit. The first latch circuit latches a first selection signal based on triggering of a first clock signal. The second latch circuit latches a second selection signal based on triggering of a second clock signal. A reset terminal of the second latch circuit is coupled to the first latch circuit. The second latch circuit is selectively reset based on an output of the first latch circuit. The switching circuit is coupled to an output terminal of the first latch circuit and an output terminal of the second latch circuit. The switching circuit selects one of the clock signals as an output clock signal of the clock switching device based on the selection signals.Type: GrantFiled: September 7, 2022Date of Patent: September 3, 2024Assignee: Nuvoton Technology CorporationInventor: Chun-Wei Lin
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Patent number: 12072731Abstract: An electronic device comprising one or more subcircuits configured to receive a clock signal, the clock signal configured to switch from a reference clock signal to a second clock signal based on a clock bypass signal, a timer configured to receive the reference clock signal and output an alignment signal based on the reference clock signal, wherein a frequency of the alignment signal is determined based on clock frequencies of the one or more subcircuits; a clock alignment module coupled to the timer and the one or more subcircuits and configured to receive the clock bypass signal, determine that the clock bypass signal has changed to switch the one or more subcircuits to the reference clock signal from the second clock signal, block the clock signal from being received by the one or more subcircuits, receive the alignment signal, and unblock the clock signal based on the alignment signal.Type: GrantFiled: May 15, 2023Date of Patent: August 27, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Varun Singh, Rejitha Nair, John Chrysostom Apostol, Venkateswar Reddy Kowkutla, Santhanagopal Raghavendra
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Patent number: 12020773Abstract: The present disclosure discloses a memory access interface device. A clock generation circuit generates a reference clock signal. A fake data strobe signal generation circuit receives the reference clock signal and delays a read enable signal from a memory access controller to enable an output of the reference clock signal to generate a fake data strobe signal. A real data strobe signal generation circuit receives a data strobe signal from a memory device and delays the read enable signal to enable an output of the data strobe signal to generate a real data strobe signal. A data reading circuit samples a data signal from the memory device according to a sampling signal to generate a read data signal to the memory access controller. A selection circuit selects the fake and the real data strobe signals as the sampling signal respectively under a single and a double data rate modes.Type: GrantFiled: June 2, 2022Date of Patent: June 25, 2024Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventor: Fu-Chin Tsai
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Patent number: 11996686Abstract: In a described example, a circuit includes a synchronization control circuit having a sync input and a sync control output, in which the sync input is coupled to a sync terminal configured to receive an external clock signal. An internal clock generator circuit has a control input and an output. The control input is coupled to the sync control output. An output circuit has first and second signal inputs, a mode control input and a clock output. The first signal input is coupled to the sync input, and the second signal input of the output circuit is coupled to the output of the internal clock generator circuit. The mode control input is coupled to the sync control output, and the clock output adapted to be coupled to a controller.Type: GrantFiled: November 30, 2021Date of Patent: May 28, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Chung San Roger Chan, John Mitchell Perry, Ari Arie Levy, Nghia Trong Tang
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Patent number: 11764770Abstract: A clock selector circuit receives a first input clock signal (CLK1) having a first frequency, and a second input clock signal (CLK2) having a second frequency. A phase difference detector is configured to detect when a phase difference occurs, over time, between the first input clock signal (CLK1) and the second input clock signal (CLK2), determined using when a clock edge crosses zero, and to signal this zero crossing to switching circuitry. The switching circuitry is configured, in response to receiving a zero-crossing signal from the phase difference detector, to detect an edge of opposite type to the predetermined type in the first input clock signal (CLK1) or in the second input clock signal (CLK2), and, in response to detecting said edge of opposite type, to switch an output clock signal (CLK_OUT) between the first input clock signal (CLK1) and the second input clock signal (CLK2).Type: GrantFiled: December 16, 2020Date of Patent: September 19, 2023Assignee: Nordic Semiconductor ASAInventors: Bartosz Gajda, Frode Pedersen
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Patent number: 11609600Abstract: A glitch detector includes a metastability detector circuit, a reference storage circuit, and a pattern comparison circuit. The metastability detector circuit is configured to generate state signals at each cycle of the clock signal. The reference storage circuit is configured to store a logic state of each state signal based on a delayed version of the clock signal, and generate reference signals. A logic state of each reference signal is equal to a logic state of a corresponding state signal generated during a previous cycle of the clock signal. The pattern comparison circuit is configured to receive the state signals generated during a current cycle of the clock signal, the reference signals, and first and second values, and generate clock and voltage glitch signals based on first and second patterns that are associated with the state signals generated during the current cycle and the reference signals, respectively.Type: GrantFiled: July 22, 2022Date of Patent: March 21, 2023Assignee: NXP USA, Inc.Inventors: Rohit Kumar Sinha, Garima Sharda, Vandana Sapra, Amol Agarwal, Stefan Doll, Andreas Lentz
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Patent number: 11303426Abstract: An apparatus include a baseband processor configured to receive digital samples of a first wireless local area network (WLAN) signal demodulated with a first phase locked loop (PLL). The baseband processor is configured to determine whether to switch from using the first PLL to demodulate the first WLAN signal to a second PLL to demodulate the first WLAN signal. The apparatus further includes a selection circuit coupled to the first PLL and the second PLL. The selection switch is configured to switch from the first PLL to the second PLL based on the determination. The baseband processor is configured to receive additional digital samples of the first WLAN signal demodulated with the second PLL.Type: GrantFiled: September 29, 2017Date of Patent: April 12, 2022Assignee: Intel CorporationInventors: Roy Amel, Eran Segev, Shahar Gross
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Patent number: 11146272Abstract: A semiconductor device includes a selection signal generation circuit configured to generate a selection signal by comparing a first input signal and a second input signal. The semiconductor device also includes a comparison signal generation circuit configured to output a comparison signal by selecting one of the first input signal and the second input signal based on the selection signal.Type: GrantFiled: June 17, 2020Date of Patent: October 12, 2021Assignee: SK hynix Inc.Inventor: Chang Hyun Kim
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Patent number: 10771067Abstract: A system and a method for hitless clock switching are provided. In the system, a sampling circuitry group samples a primary reference clock signal and a secondary reference clock signal to obtain first and second sampling information, respectively. A phase detector group obtains a phase difference between the primary and secondary reference clock signals with the first and second sampling information. A compensator group adds the phase difference to a phase of the secondary reference clock signal to obtain a backup reference clock signal. When the primary reference clock signal is abnormal or missing, the signal selector determines the backup reference clock signal as a target reference clock signal and sends it to a phase-locked loop. The phase-locked loop performs loop control on the target reference clock signal, thereby implementing hitless switching of reference clock signals.Type: GrantFiled: June 21, 2019Date of Patent: September 8, 2020Assignee: NEWCOSEMI (BEIJING) TECHNOLOGY CO., LTDInventors: Deyi Pi, Chang Liu, Jinliang Liu
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Patent number: 10374734Abstract: Devices and methods to design and use network interfaces compliant with time-synchronization protocols via a multi-tier architecture are provided. This architecture allows for independent development between circuitry related to the time-synchronization protocols and circuitry responsible for channel access, reducing redundancies in the design process.Type: GrantFiled: March 31, 2016Date of Patent: August 6, 2019Assignee: ALTERA CORPORATIONInventors: Sita Rama Chandrasekhar Mallela, Seng Kuan Yeow
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Patent number: 10355680Abstract: A frequency adjusting device includes a voltage droop detector and a frequency divider. The voltage droop detector compares a supply voltage with a lower threshold voltage to output a comparison result. When the supply voltage is greater than the threshold voltage, the frequency divider outputs a result of dividing a basic clock signal by a first value as a clock signal. When the supply voltage is smaller than the threshold voltage, the frequency divider outputs a result of dividing the basic clock signal by a second value as the clock signal.Type: GrantFiled: March 8, 2017Date of Patent: July 16, 2019Assignee: MSTAR SEMICONDUCTOR, INC.Inventor: Meng-Tse Weng
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Patent number: 10198026Abstract: In a system having a first clock domain with a first clock and a second clock domain with a second clock, the first and second clocks are monitored to determine whether one or both clocks are active. The first clock is selected to be an output clock if the first clock is active and the second clock is disabled irrespective of the clock selection signal. The second clock is selected to be the output clock if the second clock is active and the first clock is disabled irrespective of the clock selection signal. If both the first clock and the second clock are active, either the first clock or the second clock is selected according to a received clock selection signal.Type: GrantFiled: March 30, 2017Date of Patent: February 5, 2019Assignee: Amazon Technologies, Inc.Inventors: Guy Nakibly, Usama Nassir, Saar Gross, Nafea Bshara, Barak Wasserstrom, Daniel Joseph Grey
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Patent number: 9936262Abstract: A coupling device for use in a hybrid fiber coaxial (HFC) network may be configured to detect a control message and determine from the message a period for which a cable modem downstream is to be transmitting a desired transmission, disable an upstream path through it when there is only noise incident on the upstream path, and enable the upstream path during the period when a desired transmission from a cable modem downstream of the coupling device is incident on the upstream path. The coupling device may be a trunk amplifier, a distribution amplifier, or a splitter. The coupling device may comprise a single upstream interface coupled to a plurality of downstream interfaces. The enabling and/or disabling may be in response to a signal strength indicated by the SSI being below a threshold.Type: GrantFiled: January 17, 2017Date of Patent: April 3, 2018Assignee: Maxlinear, Inc.Inventors: Curtis Ling, Sridhar Ramesh, Timothy Gallagher
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Patent number: 9748959Abstract: Circuits, apparatuses, and methods are disclosed for frequency division. In one such example circuit, a frequency divider is configured to alternate between providing a common frequency clock signal as an output clock signal through a first circuit responsive to a reference clock signal and providing a reduced frequency clock signal as the output clock signal through a second circuit responsive to the reference clock signal. The first and second circuits share a shared circuit through which the output clock signal is provided. An enable circuit is configured to cause the frequency divider to alternate between providing the common frequency clock signal as the output clock signal through the first circuit and the reduced frequency clock signal as the output clock signal through the second circuit.Type: GrantFiled: March 12, 2012Date of Patent: August 29, 2017Assignee: Micron Technology, Inc.Inventor: Tyler J. Gomm
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Patent number: 9612611Abstract: In a system having a first clock domain with a first clock and a second clock domain with a second clock, the first and second clocks are monitored to determine whether one or both clocks are active. The first clock is selected to be an output clock if the first clock is active and the second clock is disabled irrespective of the clock selection signal. The second clock is selected to be the output clock if the second clock is active and the first clock is disabled irrespective of the clock selection signal. If both the first clock and the second clock are active, either the first clock or the second clock is selected according to a received clock selection signal.Type: GrantFiled: September 29, 2015Date of Patent: April 4, 2017Assignee: Amazon Technologies, Inc.Inventors: Guy Nakibly, Usama Nassir, Saar Gross, Nafea Bshara, Barak Wasserstrom, Daniel Joseph Grey
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Patent number: 9270282Abstract: A clock signal for use by a circuit can be switched between clocks glitchlessly. A series of delay devices are connected in series based on an integral timing ratio. The integral timing ratio can be based on a ratio of the one of the clock's frequency or period to the other's frequency or period. When a clock select signal is received, the select signal is qualified and then delayed an amount of time based on the integral timing ratio, using the delay devices. The number of delay devices in each series can be the next largest integer to the integral timing ratio, plus one. The clock signal can then be glitchlessly switched from one clock to the other.Type: GrantFiled: December 23, 2013Date of Patent: February 23, 2016Assignee: Google Inc.Inventors: Clemenz Portmann, Donald Charles Stark
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Patent number: 9261936Abstract: A network terminal includes: an oscillator circuit; a communication processing unit which transmits and receives communication data through a transmission path, using the clock; a controller unit which controls a function of the network terminal, using the clock; a clock control unit which causes the oscillator circuit to start or stop oscillating, and supply the clock; and a signal detecting unit which monitors a wave detection signal communicated through the transmission path in the case where the communication processing unit is not operating, and generates an activation signal according to which the clock control unit causes the oscillator circuit to start oscillating at a time when the wave detection signal exceeds a threshold value. The signal detecting unit is operable without using the clock, and the controller unit switches a detectable wave detection signal by changing a circuit constant of the signal detecting unit.Type: GrantFiled: February 5, 2014Date of Patent: February 16, 2016Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventor: Osamu Katou
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Patent number: 9118458Abstract: A clock generation circuit is operative to disable and enable a plurality of output clock signals while maintaining predetermined phase relationships between the clock signals. A reference clock signal is divided by a factor of at least two, to generate a master clock signal. A plurality of phase circuits, each independently enabled, generates a plurality of output clock signals by dividing the reference clock signal. The output clock signals have predetermined phase relationships relative to each other. Each phase circuit is enabled synchronously to a synchronization edge of the master clock signal. A synchronization circuit associated with each phase circuit ensures synchronization with the master clock signal by outputting a phase circuit enable signal only upon the conditions of a clock enable signal associated with the output clock being asserted and the receipt of a predetermined number of master clock signal synchronizing edges.Type: GrantFiled: April 24, 2014Date of Patent: August 25, 2015Assignee: Telefonaktiebolaget L M Ericsson (publ)Inventors: Mikko Lintonen, Jukka Kohola, Marko Pessa, Olli Varkki
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Patent number: 9059687Abstract: A method of operating a circuit includes receiving a first data signal at a first node. The first node is coupled to a second node to couple the first data signal to the second node. After coupling the first node to the second node, an inversion is enabled from the second node to a third node. An inversion from the third node to the fourth node is provided. After the enabling the inversion from the second node to the third node, the first node is decoupled from the second node. After the enabling the inversion from the second node to the third node, the second node is coupled to the third node. An inversion from the fourth node to the third node is enabled and the second node is decoupled from the fourth node.Type: GrantFiled: June 26, 2014Date of Patent: June 16, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Ravindraraj Ramaraju, Prashant U. Kenkare
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Patent number: 9041432Abstract: A system on chip (SOC) includes a clock generator to provide one or more on-chip reference clocks to a number of physical medium attachments (PMAs) across a common clock bus. The clock generator receives one or more external, off-chip clock lines, from which it generates the on-chip reference clocks. Each of the PMAs may operate data input/output (I/O) channels under a variety of different communications protocols, which can have common or distinct reference clock frequencies. Accordingly, the on-chip reference clocks are generated to provide the required reference clocks to each of the PMAs.Type: GrantFiled: September 30, 2013Date of Patent: May 26, 2015Assignee: Cavium, Inc.Inventors: Scott Meninger, Rohan Arora
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Patent number: 9024661Abstract: Apparatus for glitch-free switching between two clock sources on an integrated circuit. Clock gaters provide a clock from a single source that can be turned on and off without causing partial pulses to be created. Control circuitry going to the individual clock gaters provides the ability to shut all clocks off for a period of time equal to the longest clock period. By combining the clocks with an OR gate and gating all clocks off before switching from one clock to another, a glitch-free train of clock pulses can be created from individual clock inputs. Since clock glitches can cause erratic behavior in integrated circuits, this invention allows one to switch between different (unrelated) clocks without causing erratic behavior.Type: GrantFiled: January 9, 2014Date of Patent: May 5, 2015Assignee: The United Sates of America as represented by the Secretary of the Air ForceInventor: John W. Rooks
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Patent number: 9013227Abstract: A system includes a control board, a controlled board, and a connector connecting the control board to the controlled board. The control board includes a processing unit that configures the reference voltage signals, a non-volatile memory that stores information about the reference voltage signals, and a DAC that outputs the reference voltage signals in accordance with instructions from the processing unit. The controlled board includes: first and second voltage reference devices that receive first and second reference voltage signals, respectively, and a radio-frequency device that receives a first frequency signal and a second frequency signal and outputs a third frequency signal based on one of the first and second reference voltage signals. The connector includes an analog line for providing reference voltage signals to the first and second voltage reference devices and a digital line for providing control signals to activate one of the first and second voltage reference devices.Type: GrantFiled: January 22, 2014Date of Patent: April 21, 2015Assignee: ZTE (USA) Inc.Inventors: Aleksandr Semenyshev, Shawn Walsh, Ying Shen, Thanh Hung Nguyen, Hong Hu
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Patent number: 8994407Abstract: A system includes an ADC that, based on a first clock signal, converts an analog signal into a digital signal. A first circuit generates a second clock signal based on the digital signal. An interpolator generates a phase delayed version of the second clock signal and a third clock signal. The third clock signal is generated based on the second clock signal and the phase delayed version and includes transitioning from the second clock signal to the phase delayed version. The third clock signal includes pulses each having a first pulse width and a pulse having a second pulse width. The second pulse width is different than the first pulse width due to the transition from the second clock signal to the third clock signal. A second circuit removes the pulse having the second pulse width from the third clock signal to generate the first clock signal.Type: GrantFiled: October 11, 2013Date of Patent: March 31, 2015Assignee: Marvell International Ltd.Inventors: Chi Fung Cheng, Pantas Sutardja
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Patent number: 8994432Abstract: A semiconductor integrated circuit and a method operating the same are provided. The semiconductor integrated circuit includes a first clock network configured to divide a clock signal into first output clock signals with a high frequency, a second clock network configured to divide the clock signal into second output clock signals with a non-high frequency, a plurality of selection circuits configured to be connected between the first clock network and the second clock network, and configured to output one of the first output clock signals and the second output clock signals, according to a power mode, and a plurality of clock sinks configured to sink output clock signals respectively output from the selection circuits.Type: GrantFiled: August 23, 2013Date of Patent: March 31, 2015Assignee: Samsung Electronics Co., Ltd.Inventor: Hoi Jin Lee
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Patent number: 8957704Abstract: A digital phase selector circuit that switches an output clock between N input clock phases is described. The phase selector utilizes a special output mux and switches clock phases during a safe zone to avoid glitches. The phase selector is used in the feedback path of a PLL to implement functions such as spread spectrum or fractional reference clocks. An example with N=4 and an optimized latch mux is shown.Type: GrantFiled: September 6, 2013Date of Patent: February 17, 2015Assignee: Synopsys, Inc.Inventors: Skye Wolfer, David A. Yokoyama-Martin
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Patent number: 8941415Abstract: Circuits and methods are provided for generating clock signals and correcting duty cycle distortion in clock signals. A circuit for generating a clock signal includes a multiplexer circuit and an edge-triggered flip-flop circuit. The multiplexer circuit selectively outputs one of a plurality of input clock signals. The edge-triggered flip-flop detects a transitioning edge of the input clock signal that is selectively output from the multiplexer circuit, and in response to the detection, samples a logic level of a received data signal, and generates a transition of an output clock signal at an output port of the edge-triggered flip-flop. The multiplexer circuit selectively outputs one of the plurality of input clock signals to a clock signal port of the edge-triggered flip-flop, based on a logic level of the output clock signal at the output port of the edge-triggered flip-flop, which is input to a select control port of the multiplexer circuit.Type: GrantFiled: January 10, 2014Date of Patent: January 27, 2015Assignee: International Business Machines CorporationInventors: John F. Bulzacchelli, Ankur Agrawal
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Patent number: 8890596Abstract: A clock signal generating apparatus includes a first frequency generating circuit, a second frequency generating circuit, and an output circuit. The first frequency generating circuit is arranged to generate a first clock signal having a first oscillation frequency. The second frequency generating circuit is arranged to generate a second clock signal having a second oscillation frequency. The output circuit is arranged to receive the first and second clock signals. The output circuit is able to output one of the first and second clock signals as an output clock signal according to an oscillation frequency control setting provided by an external bounding pad included within the clock signal generating apparatus.Type: GrantFiled: June 25, 2012Date of Patent: November 18, 2014Assignee: MediaTek Singapore Pte. Ltd.Inventor: Xiao-Fei Chen
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Patent number: 8872551Abstract: An integrated circuit includes a clock control unit configured to selectively output an external clock or a delayed clock acquired by delaying the external clock as an input clock in response to a divided clock generated by dividing the external clock, when a test mode is entered; and an internal circuit operating in response to the input clock.Type: GrantFiled: March 3, 2012Date of Patent: October 28, 2014Assignee: SK Hynix Inc.Inventor: Hoon Choi
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Publication number: 20140313836Abstract: Techniques are presented to improve the performance, accuracy and power consumption of on-chip voltage biasing and transmission for highly loaded RC networks (such as wordlines or bitlines in NAND or 3D memory arrays) that are otherwise limited by the physics of RC time constant. When transitioning the near-end voltage of the network, an under-drive or over-drive level is applied, combined with feedback control to estimate when the far-end voltage approaches the desired level.Type: ApplicationFiled: April 22, 2013Publication date: October 23, 2014Inventors: Feng Pan, Shankar Guhados
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Patent number: 8860468Abstract: A clock multiplexer includes first and second input stages for outputting first and second clock signals, respectively. The first and second input stages each include a flip-flop, a latch and a first logic gate. Reset terminals of the flip-flops receive a select signal based on which the first and second input stages output the first and second clock signals. A second logic gate is connected to the first and second input stages for selectively providing the first and second clock signals as an output clock signal.Type: GrantFiled: June 6, 2013Date of Patent: October 14, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Amitesh Khandelwal, Gaurav Jain, Abhishek Mahajan
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Patent number: 8854086Abstract: Integrated circuit devices include first and second periodic signal generators and a power down detection circuit. The first periodic signal generator is configured to generate at least a first periodic signal having a first frequency at an output thereof and the second periodic signal generator is configured to generate a second periodic signal having a second frequency less than the first frequency at an output thereof. The power down detection circuit is configured to selectively provide one or the other of the first and second periodic signals to an output terminal of the integrated circuit device, in response to monitoring a status of a signal received at an input terminal of the integrated circuit device. This received signal reflects a power down status of an external device that receives the selected one of the first and second periodic signals.Type: GrantFiled: March 12, 2013Date of Patent: October 7, 2014Assignee: Integrated Device Technology, Inc.Inventors: Jagdeep Bal, Cheng Wen Hsiao
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Patent number: 8836379Abstract: The invention provides a clock select circuit and method which uses feedback arrangements between latches in different branches, with each branch for coupling an associated clock signal to the circuit output. An override circuit is provided in one of the feedback arrangements for preventing a latching delay in that feedback arrangement. This enables rapid switching between clocks in both directions.Type: GrantFiled: February 7, 2014Date of Patent: September 16, 2014Assignee: NXP B.V.Inventors: Surendra Guntur, Ghiath Al-kadi, Rinze Ida Mechtildis Peter Meijer, Jan Hoogerbrugge, Hamed Fatemi
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Patent number: 8829944Abstract: In an integrated circuit having input circuitry whose positive and/or negative input signals are gated by one or more clocked input switches, the switch clock signal CLK_SW used to clock the input switch(es) is automatically generated based on the higher of the IC's power supply voltage VDD and the positive input signal voltage Vplus. In one embodiment, a clock level shifter shifts an input clock signal CLK_VDD from the VDD voltage domain to generate a level-shifted clock signal CLK_VPLUS in the Vplus voltage domain. Based on a control signal VSEL, a clock selector selects either the input clock signal or the level-shifted clock signal to be the switch clock signal. An over-voltage detector generates both the logic state and the voltage domain of the control signal based on the higher of VDD and Vplus, such that the input switches are appropriately clocked even during over-voltage conditions in which Vplus>VDD.Type: GrantFiled: September 30, 2013Date of Patent: September 9, 2014Assignee: Lattice Semiconductor CorporationInventor: Edward E. Miller
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Patent number: 8810300Abstract: Embodiments provide systems and methods for dynamically regulating the clock frequency of an integrated circuit (IC) based on the IC supply voltage. By doing so, the clock frequency is no longer constrained by a worst-case voltage level, and a higher effective clock frequency can be supported, increasing the IC performance. Embodiments include a wave clocking system which uses a plurality of delay chains configured to match substantially the delays of respective logic paths of the IC. As the delays of the logic paths vary with supply voltage and temperature changes, the delay chains matched to the logic paths experience substantially similar changes and are used to regulate the clock frequency of the IC.Type: GrantFiled: December 20, 2011Date of Patent: August 19, 2014Assignee: Broadcom CorporationInventor: Tim Sippel
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Publication number: 20140225639Abstract: One feature pertains to an integrated circuit (IC) that includes a first plurality of ring oscillators configured to implement, in part, a physically unclonable function (PUF). The IC further includes a second plurality of ring oscillators configured to implement, in part, an age sensor circuit, and also a ring oscillator selection circuit that is coupled to the first plurality of ring oscillators and the second plurality of ring oscillators. The ring oscillator selection circuit is adapted to select at least two ring oscillator outputs from at least one of the first plurality of ring oscillators and/or the second plurality of ring oscillators. Notably, the ring oscillator selection circuit is commonly shared by the PUF and the age sensor circuit. Also, the IC may further include an output function circuit adapted to receive and compare the two ring oscillator outputs and generate an output signal.Type: ApplicationFiled: February 11, 2013Publication date: August 14, 2014Applicant: QUALCOMM IncorporatedInventors: Xu GUO, Brian M. Rosenberg
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Patent number: 8803558Abstract: An integrated circuit includes a plurality of semiconductor devices. Each of the semiconductor devices includes an internal voltage generation unit configured to generate a plurality of internal voltages, a voltage select output unit configured to output a default voltage of a plurality of internal voltages to a preset pad in response to an initial value of a select code, and selectively output the other voltages of the plurality of internal voltages to the pad in response to variations of the select code, and a stack operation control unit configured to control the voltage select output unit to output the default voltage to the pad in response to a stack signal and a predetermined value of the select code, instead of the initial value of the select code, and whether or not to activate the stack signal is determined according to whether or not the plurality of semiconductor devices are stacked.Type: GrantFiled: March 15, 2013Date of Patent: August 12, 2014Assignee: SK Hynix Inc.Inventor: Jae-Hyuk Im
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Patent number: 8773168Abstract: A maximum voltage selection circuit and method and a sub-selection circuit are provided. The maximum voltage selection circuit includes a peripheral signal circuit and a selection circuit with N channels of input voltages. The peripheral signal circuit provides an operating mode signal and a reference voltage to the selection circuit including N sub-selection circuits coupled to the N channels of input voltages respectively. A sub-selection circuit determines its operating mode according to the operating mode signal. In the operating mode, when an input voltage of a sub-selection circuit is larger than the reference voltage, the sub-selection circuit sets itself to the output enable state and sets other sub-selection circuits to the output disable state, and outputs its input voltage as a maximum voltage through a PMOS.Type: GrantFiled: June 10, 2013Date of Patent: July 8, 2014Assignee: Fairchild Semiconductor CorporationInventor: Lei Huang
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Patent number: 8760197Abstract: A system, method, and computer program product are provided for the switching of clock signals. A clock network switching system includes a first re-synchronization circuit coupled to a first input clock, and a second re-synchronization circuit coupled to a second input clock. There is also an input select decoder coupled to the first and second re-synchronization circuit that can dynamically select either the first or the second input clock to be active. When an input clock is selected to be active, the re-synchronization circuit associated with the selected input clock generates an output clock synchronized with the selected input clock where both a high pulse width and a low pulse width of the output clock are not less than those of the selected input clock.Type: GrantFiled: March 29, 2011Date of Patent: June 24, 2014Assignee: Broadcom CorporationInventor: Iraj Motabar
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Patent number: 8754696Abstract: Aspects of the invention provide a circuit structure that automatically monitors a plurality of ring oscillators and dynamically selects the fastest or the slowest ring oscillator for feedback into the plurality of ring oscillators. In one embodiment, a circuit includes: a plurality of delay elements, each delay element associated with a ring oscillator; a first logic gate for receiving outputs of each of the delay elements; a second logic gate for receiving outputs of each of the delay elements; and a multiplexer for receiving an output of the first logic gate and an output of the second logic gate and choosing one of the outputs, wherein a selection for the multiplexer is based on an output of the multiplexer. To select the fastest ring oscillator, a second multiplexer is provided.Type: GrantFiled: July 26, 2012Date of Patent: June 17, 2014Assignee: International Business Machines CorporationInventors: Margaret R. Charlebois, Rashmi D. Chatty, Christopher D. Hanudel, Robert D. Herzl, David W. Milton, Clarence R. Ogilvie, Paul M. Schanely, Matthew P. Szafir, Tad J. Wilder
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Patent number: 8742816Abstract: A delay circuit includes a delay unit configured to generate a delayed transmission signal by delaying a transmission signal activated when a first signal or a second signal is activated, a signal type storing unit configured to store whether the first signal and the second signal is activated, and a transmitting unit configured to transmits the delayed transmission signal as a first delayed signal or a second delayed signal in response to a value stored in the signal type storing unit.Type: GrantFiled: December 17, 2012Date of Patent: June 3, 2014Assignee: SK Hynix Inc.Inventor: Choung-Ki Song
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Publication number: 20140125382Abstract: Circuits and methods are provided for generating clock signals and correcting duty cycle distortion in clock signals. A circuit for generating a clock signal includes a multiplexer circuit and an edge-triggered flip-flop circuit. The multiplexer circuit selectively outputs one of a plurality of input clock signals. The edge-triggered flip-flop detects a transitioning edge of the input clock signal that is selectively output from the multiplexer circuit, and in response to the detection, samples a logic level of a received data signal, and generates a transition of an output clock signal at an output port of the edge-triggered flip-flop. The multiplexer circuit selectively outputs one of the plurality of input clock signals to a clock signal port of the edge-triggered flip-flop, based on a logic level of the output clock signal at the output port of the edge-triggered flip-flop, which is input to a select control port of the multiplexer circuit.Type: ApplicationFiled: January 10, 2014Publication date: May 8, 2014Applicant: International Business Machines CorporationInventors: John F. Bulzacchelli, Ankur Agrawal
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Publication number: 20140111249Abstract: Systems and methods for detecting the failure of a precision time source using an independent time source are disclosed. Additionally, detecting the failure of a GNSS based precision time source based on a calculated location of a GNSS receiver is disclosed. Moreover, the system may be further configured to distribute a time derived from the precision time source as a precision time reference to time dependent devices. In the event of a failure of the precision time source, the system may be configured to distribute a time derived from a second precision time source as the precision time signal during a holdover period.Type: ApplicationFiled: October 18, 2013Publication date: April 24, 2014Applicant: Schweitzer Engineering Laboratories, Inc.Inventors: David E. Whitehead, Shankar V. Achanta, Henry Loehner
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Patent number: 8698538Abstract: A level converter circuit is disclosed. The level converter circuit includes a first level converter that generates a first output signal, and a second level converter that generates a second output signal. The level converter circuit further includes an edge selector coupled to the first level converter and the second level converter that selects a rising edge of either the first output signal or the second output signal, and selects a falling edge of either the first output signal or the second output signal to generate an optimized output signal.Type: GrantFiled: February 2, 2011Date of Patent: April 15, 2014Assignee: Synopsys, IncInventor: Pedro Miguel Ferreira de Figueiredo
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Patent number: 8698531Abstract: An integrated circuit with automatic configuration is disclosed. The integrated circuit comprises a plurality of controllers and a clock detection device. The controllers share a plurality of common pins. The clock detection device coupled to a specified common pin for performing clock detection operations on an external clock signal through the specified common pin according to a plurality of predetermined thresholds and generating a plurality of control signals to the controllers so that only one controller is enabled and performs signal transmission through the common pins.Type: GrantFiled: February 5, 2013Date of Patent: April 15, 2014Assignee: Aspeed Technology, Inc.Inventors: Fu-Chou Hsu, Hung-Ju Huang, Chung-Yen Lu
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Publication number: 20140009187Abstract: An integrated circuit includes an outputting unit in which a CMOS inverter configured from a first MOS transistor and a second MOS transistor for outputting a second signal using a first signal as an input thereto and a third MOS transistor that includes a gate terminal to which a control signal for controlling the outputting of the second signal is inputted and that is in an off state when the control signal indicates inhibition of the outputting of the second signal are cascade-connected to each other, and a fixing unit that fixes a value of the first signal based on the control signal. When the control signal indicates inhibition of the outputting of the second signal, the fixing unit fixes the value of the first signal to a value with which the first or second MOS transistor is placed in an off state.Type: ApplicationFiled: September 6, 2013Publication date: January 9, 2014Applicant: Fujitsu LimitedInventors: Masao IDE, Tomohiro TANAKA
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Publication number: 20140009188Abstract: Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).Type: ApplicationFiled: September 10, 2013Publication date: January 9, 2014Applicant: Altera CorporationInventors: Toan Thanh Nguyen, Thungoc M. Tran, Sergey Shumarayev, Arch Zaliznyak, Shoujun Wang, Ramanand Venkata, Chong H. Lee
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Patent number: 8570014Abstract: In a switch mode power supply, a circuit and method for switching between an internal clock and an external synchronization clock when a stable external clock has been detected, and for switching back to operating the power supply using said internal clock when a predetermined number of sequential external clock pulses exceed a predetermined switching period dropout threshold or are otherwise missing. In one embodiment, a power system comprises a plurality of power supplies connected in parallel to a common load and where each power supply is synchronized to the external clock when a stable external clock has been detected by each.Type: GrantFiled: August 4, 2011Date of Patent: October 29, 2013Assignee: Intersil Americas, LLCInventors: Steven Patrick Laur, Zbigniew Jan Lata, Jinyu Yang
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Patent number: 8558600Abstract: A clock signal generation circuit includes a first oscillation circuit for generating a first oscillation clock signal having a first frequency; a second oscillation circuit for generating a second oscillation clock signal having a second frequency; a frequency division circuit for generating a frequency division clock signal obtained through dividing the first oscillation clock signal; and a clock selection circuit for outputting the first oscillation clock signal as a high speed clock signal. The clock selection circuit is configured to output the second oscillation clock signal as the low speed clock signal when the second oscillation circuit transmits the second oscillation clock signal, and to output the frequency division clock signal as the low speed clock signal when the second oscillation circuit does not transmit the second oscillation clock signal.Type: GrantFiled: March 27, 2012Date of Patent: October 15, 2013Assignee: Lapis Semiconductor Co., Ltd.Inventor: Kenichi Natsume
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Publication number: 20130254434Abstract: A semiconductor device including an input terminal to receive an input signal and an output terminal to output an output signal includes delay elements connected in series with the input terminal and each to assign the delay to the input signal input from the input terminal, selectors connected to output sides of the delay elements and each to select one of output signals of the delay elements based on a selection signal for selecting the one of the output signals of the delay elements to return the selected one of the output signals to the output terminal, and delay circuits disposed corresponding to the selectors and each to cause switching of the selection signal input into a corresponding one of the selectors to occur after switching of a signal level of the input signal input into the corresponding one of the selectors serving as a signal turning point.Type: ApplicationFiled: May 23, 2013Publication date: September 26, 2013Applicant: FUJITSU LIMITEDInventors: Masaki Fujioka, Koji Migita, Kazumasa Kubotera, Yasutaka Kanayama
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Patent number: 8525557Abstract: Various methods and structures related to tristate multiplexer circuits are disclosed. An embodiment provides a selection circuit in which selectively enabled input circuits are coupled to an output circuit through an output enable circuit such that a selected one of the selectively enabled input circuits is operable to provide a pathway for charging and discharging currents used to charge and discharge an output circuit transistor gate. This and other detailed embodiments are described more fully in the disclosure.Type: GrantFiled: November 4, 2011Date of Patent: September 3, 2013Assignee: Altera CorporationInventor: David Lewis