Abstract: In a clock switching apparatus, a corresponding mask clock signal is generated for at least one of first and second clock signals. A mask clock signal has an interval of a predetermined logical level near the switching between the clock signals. Each mask clock signal is synchronized to the first and/or second clock signals. Such an interval in the mask clock signal prevents occurrence of glitches in an output clock signal that is switched between at least one mask clock signal and/or at least one clock signal.

Abstract: A multiplexer circuit for selecting one of first and second input signals based on a first input select signal includes a multiplexer, a control circuit and an enable buffer. The multiplexer selects one of the first and second input signals based on a second input select signal generated by the control circuit and provides a second output signal. The control circuit receives the second output signal and the first input select signal to generate the second input select signal and an enable signal where the signals have transitions synchronized to the transitions of the second output signal. The enable buffer operates to allow or disallow the second output signal to be passed as the output signal of the multiplexer circuit in response to the enable signal. The multiplexer circuit operates to eliminate runt pulse generation during the switching over of the input signals to provide an error-free output data stream.

Abstract: An electronic device selects one of a plurality of input signals for coupling to an output channel. Individual pulldowns provide a separate pathway for each input, and are coupled to a common node which is pre-charged to a voltage less than a system voltage. Each pulldown is coupled to a select line for gating an associated input signal.

Abstract: A clock signal switching device includes: a plurality of signal synchronization generation means for generating mask signals and synchronized switching signals; a plurality of clock signal mask means for generating masked clock signals; a synchronized switching signal selection means for selecting one from among the synchronized switching signals; and a masked clock signal selection means for selecting one from among the masked clock signals.

Abstract: A method and device for generating a clock signal with predetermined clock signal properties firstly prepare a number of clock signals with an essentially identical frequency and with a respectively different phase relation with regard to a master clock signal in order to subsequently (on the basis of a control signal, which is prepared according to the clock signal to be generated), select predetermined clock signals from the number of prepared clock signals and to combine the selected clock signals in order to generate the desired clock signal.

Abstract: A multiplexer is disclosed. The multiplexer comprises a first input and a first channel coupled to the first input. The multiplexer further includes a second input and a second channel coupled to the second input. Finally, the multiplexer includes an output coupled to the first and second channels, wherein a coupling capacitance of an inactive one of the first and second channels is not coupled directly to the output. A method and system in accordance with the present invention reduces crosstalk and jitter in a multiplexer by eliminating the coupling capacitance between an inactive input and the output. In so doing, there is significantly better isolation between channels thereby minimizing the aforementioned cross-talk and jitter.

Abstract: In a signal processing system with an IC having an intrinsic signal provided at a pin of the IC, a first operational function (de-emphasis) for the signal is provided at the pin, and further along in the signal flow path, a second operational function (variable attenuation) for the signal is provided within the IC. An extrinsic signal is switchably coupled to the pin so that the second operational function can be used to operate on the extrinsic signal. The second signal is coupled to the pin at a low source impedance so that when the second signal is switched to be operational, the first operational function is defeated, and the first signal is severely attenuated. When the circuit is switched to not couple the second signal to the pin, the coupling path for the second signal and the low source impedance are both removed, thus restoring the first operational function and the first signal at the pin of the IC.

Abstract: A programmable system-on-a-chip integrated circuit device comprises at least one of a crystal oscillator circuit, an RC oscillator circuit, and an external oscillator input. A clock conditioning circuit is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A real-time clock is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A programmable logic block is coupled to the clock conditioning circuit and the real-time clock.

Abstract: A clock data recovery (CDR) circuit to recover a clock signal and data signal from an input signal. The CDR circuit includes a control circuit, a select circuit and a phase adjust circuit. The control circuit generates a first control signal according to a phase relationship between the input signal and a first clock signal. The select circuit is coupled to receive the first control signal from the control circuit and coupled to receive a second control signal. The select circuit is responsive to a select signal to select either the first control signal or the second control signal to be output as a selected control signal. The phase adjust circuit is coupled to receive the selected control signal from the select circuit, the phase adjust circuit being responsive to the selected control signal to adjust the phase of the first clock signal.

Abstract: A multiple-phase switching circuit includes an alternative signal generator for generating a plurality of alternative signals according to a switching signal, and a multiplexer for receiving a plurality of clock signals and outputting a target clock signal according to the alternative signals. Only one of the alternative signals generated by the alternative signal generator is in a first logic level, while the other alternative signals are in a second logic level. The alternative signal generator changes the logic level of a first alternative signal having the first logic level into the second logic level, and changes the logic level of a second alternative signal adjacent to the first alternative signal into the first logic level.

Abstract: An apparatus comprising a circuit configured to automatically select a clock mode in response to a state of a clock input.

Abstract: A clock selection circuit includes an output multiplexer, control logic, and edge detection logic. The multiplexer includes inputs to receive multiple input clock signals, an output to generate the output clock signal, and a control terminal to receive a synchronized clock select signal. The control logic includes a first input to receive a clock select signal, a second input to receive a first control clock signal, a third input to receive a synchronization signal, and an output to selectively update the synchronized clock select signal with transitions in the clock select signal. The edge detection logic includes first inputs to receive the multiple input clock signals, a second input to receive a second control clock signal, and an output to generate the synchronization signal.

Abstract: Method and apparatus for reducing power consumption within a logic device is described. A logic device comprises a clock gate and a flip-flop. The clock gate includes a clock enable terminal and a clock terminal. The flip-flop includes an input terminal, an output terminal, and a configuration terminal. The flip-flop is coupled to the clock gate. The flip-flop is configurable to trigger on at least one of a rising edge and a falling edge of a clock signal. The clock gate controllably gates the clock signal coupled to the clock terminal.

Abstract: A clock shaping device includes a first clock signal selection portion that selects between a reception clock signal and a back-up clock signal based on a detected loss in the reception clock signal. A second clock signal selection portion selects between a clock signal received from the first clock signal selection portion and a clock signal received from a quartz crystal oscillation circuit based on a detected loss in the back-up clock signal. A voltage controlled oscillation circuit has a frequency that varies with a control voltage being supplied and outputs a feedback loop output signal. A phase comparison portion generates a phase difference signal based on a comparison between the feedback loop output signal and a clock signal outputted from the second clock signal selection portion. A loop filter smoothes the phase difference signal and outputs the phase difference signal in the form of the control voltage.

Abstract: A processor clock control device is disclosed that is operable to control switching between clock signals input to a processor in a glitch-free way.

Abstract: A wavelength tunable mode-locked laser system including a complex laser cavity comprising a broadband reflective mirror at one end and a wavelength chirped selective mirror at the other end. The system further includes a gain element and a low finesse Fabry-Perot etalon element inside the laser cavity. The gain element may be a semiconductor laser chip, with a broadband high reflection coating at one end and a partially reflecting coating at its other end. The gain element has a well-defined length, such that its longitudinal modes match a required optical frequency grid. The system also includes an active modulation element applied externally on said complex laser cavity to provide mode-locking of a specific cavity length among said defined predetermined cavity lengths, such that all possible optical frequencies emitted by the laser system are stabilized to the linear grid dictated by the Fabry-Perot longitudinal modes, that could be in accordance with the International Telecommunications Union Standards.

Abstract: In one aspect, an embodiment provides a clock loss sense and switchover circuit and method in which clock switchover is responsive to loss of a primary signal and to additional switch command signaling. In another aspect, an embodiment provides a clock loss sense circuit and method that utilizes counters and reset signals to compare a primary clock and secondary clock signal.

Abstract: A clock switching circuit capable of preventing occurrence of hazards in an output clock signal at a time of clock switching, regardless of the frequency ratio of input clock signals. At a time of switching to a second input clock signal CLKIN_B from a first input clock signal CLKIN_A, the output of the first input clock signal is disabled based on an output signal of a first flip-flop group which takes in an inverted signal nSEL of a select signal SEL according to the first input clock signal CLKIN_A. In addition, the output of the second input clock signal CLKIN_B is resumed based on an output signal of a fourth flip-flop group which takes in an output signal from the first flip-flop group according to the second input clock signal CLKIN_B.

Abstract: A digital logic system includes a reset input for receiving a reset signal, and a clock input for receiving an externally generated main clock signal. An ancillary clock generator generates an ancillary clock signal. A clock selection multiplexer has a first input for receiving the externally generated main clock signal, a second input for receiving the internally generated ancillary clock signal, and an output for providing the externally generated main clock signal or the internally generated ancillary clock signal to a functional circuit. A resettable edge-triggered shift register has a first input for receiving the externally generated main clock signal, a second input for receiving the reset signal, and an output connected to the clock selection multiplexer for deselecting the internally generated ancillary clock signal and selecting the externally generated main clock signal after detecting a certain number of edges of the main clock signal following the reset signal.

Abstract: An analog switching circuit selects one of a first pair of differential outputs of a first circuit having a first common mode voltage and a second pair of differential outputs of a second circuit having a second common mode voltage. The analog switching circuit includes first and second switches having one of a source and drain that communicate with the first pair of differential outputs. Third and fourth switches have one of a source and drain that communicate with the second pair of differential outputs. An operational amplifier has a first input that communicates with the other of the source and drain of the first and third switches and a second input that communicates with the other of the source and drain of the second and fourth switches. A common mode feedback circuit communicates with the first and second inputs of the operational amplifier and maintains a common mode voltage input of the amplifier below the first and second common mode voltages.

Abstract: A multiplexer includes a first stage that has tri-state buffers each of which has split outputs and a final stage that has a tri-state buffer with an output. The multiplexer includes circuitry configured to enable or disable a signal at an input of a selected one of the first-stage buffers to propagate to the output of the final-stage buffer.

Abstract: A clock source selector for selecting either a first clock signal A or a second clock signal B in accordance with a switch request signal includes three retiming circuits each consisting of two clocked flip-flops. The switch request signal is first retimed relative to clock A to give a signal P, is then retimed relative to clock B to give a signal Q, and finally is retimed relative to clock A to give a signal R. Selector circuitry operates such that when signal Q is asserted, the second clock signal B is output, when neither signal P nor signal R, as combined by a NOR gate, are asserted, the first clock signal A is output, and at other times a zero level is output. The clock source selector can be used in an integrated circuit to form a glitch-free multiplexer.

Abstract: Described are glitchless clock control circuits capable of switching away from a failed clock. One embodiment supports three basic functions: clock select, clock enable, and clock ignore. The clock-select function provides a selected one of a plurality of clock signals on a clock-distribution node. The select signals used to switch between clock signals need to be synchronous with any of the clock signals. The clock-enable function allows the clock control circuit to synchronously block or pass a selected clock signal. Finally, the clock-ignore function allows the clock control circuit to ignore a selected clock if necessary, for example, to switch away from a failed clock.

Abstract: A two-input, two-output multiplexer circuit has two tri-state inverter circuits and two switch circuits. The multiplexer outputs may be interchanged depending on a control signal. Each tri-state inverter circuit is configured to receive one of the inputs, invert it, and provide the corresponding inverted signal at the corresponding multiplexer output when the control signal corresponds to a first logic level. If the control signal corresponds to a second logic level: each switch circuit is configured to turn on, and each tri-state inverter circuit is configured to provide a high-impedance output. The first switch circuit is configured to couple the first inverted signal to the second multiplexer output when the first switch circuit is on. Similarly, the second switch circuit is configured to couple the second inverted signal to the first multiplexer output when the second switch circuit is on.

Abstract: Method and circuitry for selecting phases while avoiding glitches in the output signal during phase switching. An integrated circuit having a plurality of input terminals coupled to receive a respective plurality of clock signals having different phases, and a plurality of control terminals coupled to receive a respective plurality of phase selection signals. The circuit is configured to output a first selected clock signal from the plurality of clock signals in response to a first combination of the phase selection signals, and further configured to switch from the first selected clock signal to a second selected clock signal in response to a second combination of the phase selection signal. The circuit disengages the first clock signal after the second phases selection signal is engaged.

Abstract: For generating a delay signal, a series of source signals based on the same high frequency signal are first provided. Every adjacent two of the source signals have a phase difference of a certain clock unit therebetween. A first and a second output signals are then generated on the basis of the plurality of source signals at a first and a second time points selected as desired. The first and the second output signals are processed by a logic operation to obtain the accurate and adjustable delay signal. For obtaining the first and the second output signals, the source signals are duplicated at first, and then respectively processed in response to respective clock signals.

Abstract: A clock signal selector circuit is disclosed including a synchronizer circuit, two switching circuits, and a multiplexer. The synchronizer circuit synchronizes a first control signal to a first clock signal, thereby producing a second control signal. A first switching circuit produces the first clock signal at a first node when the second control signal is asserted. The multiplexer drives a second node with a signal at the first node when the second control signal is asserted. The second switching circuit forms an electrical connection between the first and second nodes when the second control signal is deasserted. The two switching circuits significantly reduce a probability of error at the second node due to metastability when the second control signal transitions from asserted to deasserted and the first clock signal is deselected. The second switching circuit provides electrical feedback from the second node to the first node.

Abstract: A clock deciding apparatus generates a plurality of delay clock signals and outputs a clock signal most similar to an outer clock signal to reduce the time used to decide the clock greatly. Also, even if a frequency of the clock signal is changed slightly or phase shift happens due to outer causes, the clock deciding apparatus according to the present invention is able to correspond to the above situations rapidly, and therefore, stable clock signal can be provided to the system.

Abstract: Generating a waveform having one signal level periodically and different signal levels in other durations. Two input signals are received, one having a desired constant level and another having desired signal levels. The desired output waveform is generated by selecting one of the two input signals. As a result, the output waveform may be generated to have (transitions) with high frequency even if the signal levels between adjacent portions are substantially different. Such waveforms are useful to test CDS (correlated double sampling) samplers.

Abstract: For suppressing increase of terminals in number, a semiconductor device is proposed which includes an input terminal to which an external clock is to be inputted. The semiconductor device further includes a crystal oscillating circuit, a storing circuit, and a selecting circuit. The crystal oscillating circuit generates an internal clock on the basis of the vibrating frequency of a crystal oscillator. The input terminal is inputted with a using information signal for indicating using information of the external clock and an input signal composed of the external clock. The storing circuit holds the using information signal being inputted into the input terminal when a reset signal is being inputted into a reset terminal and then outputs the signal. The selecting circuit is inputted with the internal clock and the external clock inputted at the input terminal and then outputs one of the clocks in response to the using information signal outputted from the storing circuit.

Abstract: A clock switching circuit has a clock output circuit and clock signal transfer circuits. The output circuit provides a selected clock signal. The transfer circuits receive input clock signals and select signals, and output transfer signals to the output circuit. Each of the transfer circuits includes a transmitting circuit, a generating circuit and a passing circuit. The transmitting circuit is connected to the output circuit, and receives the select signal and provides the received select signal responsive to the selected clock signal. The generating circuit is connected to the transmitting circuit, and provides an internal select signal responsive to the received select signal and the input clock signal. The passing circuit is connected to the generating circuit and the output circuit, and provides the input clock signal to the output circuit responsive to the internal select signal.

Abstract: A semiconductor integrated circuit device employing two clock signal generating circuits which output clock signals for distribution to an internal circuit of the device, the first and second clock signal generating circuits having different clock-settling times and the selection thereof is effected from outside of the device. A first one of the clock signal generating circuits uses, for example, a phase-locked loop circuit which has a large clock-settling time, and the second clock signal generating circuit is implemented, for example, using a delay-locked loop circuit whose clock-settling time is small, for example, 2-3 periods. Due to the selective actuation of the second clock signal generating circuit, which has a small clock-settling time, the generating of clock signals for the internal circuits can also be halted when the internal circuits of the device are halted thereby to further lower power consumption without compromising clock oscillator responsiveness.

Abstract: A low power flip-flop is disclosed. The number of transistors which are coupled to the clock signal is reduced by more than half when compared with known flip-flop designs. The flip-flop comprises a pair of clocked transistors forming a pass gate and a plurality of inverters coupled thereto. By reducing the number of clock signal connections needed for reliable operation, the present invention reduces the power consumed by the flip-flop when operating at typical levels of activity by up to 70%.

Abstract: A device and a method are used for generating a selection signal provided for a multiplexing circuit. The multiplexing circuit generates an output signal from a plurality of source signals in response to the selection signal. The device includes an operational circuit and a toggle control circuit. The method includes steps of: performing an OR operation of the plurality of source signals to obtain an operational output signal; and latching the operational output signal in an active low manner in response to a selection command to obtain the selection signal. By prohibiting the selection signal from toggling when any of the plurality of source signals is at an output-enabled state, the accuracy of the selection signal can be improved.

Abstract: A system and method for monitoring internal voltage sources in an integrated circuit, such as a DRAM integrated circuit, includes an internal analog multiplexing circuit, an internal analog-to-digital converter, and an interface circuit. Through the analog multiplexing circuit, the analog-to-digital converter sequentially connects to each voltage source and converts the measured voltage level of the source to a binary word. The interface circuit presents the binary word, e.g., serially, to test equipment off the integrated circuit.

Abstract: Clock switching circuitry includes a clock switching control circuit for temporarily storing a clock select signal, which is input from the outside for selecting one of a plurality of clock signals different in phase from each other. The clock switching control circuit then outputs the clock select signal in accordance with the change in the level of a timing signal that switches the clock signals. A clock output circuit outputs one of the clock signals selected in accordance with the clock select signal. A masking circuit generates the timing signal while masking it to a preselected level by taking account of changes in the levels of the clock signals.

Abstract: A system for allowing an asynchronous clock signal to be selected from a plurality of asynchronous clock signals without causing glitches. In the system, a requestor is connected to control signals. The control signals indicate to the requestor which asynchronous clock signal, of the two or more clock signals, to request. The requestor informs a selector of the request. The selector determines which asynchronous clock signal was selected. The selected asynchronous clock is then detected by the detector. The detector feeds the selected asynchronous clock signal to a signal output. The signal output releases the selected asynchronous clock signal.

Abstract: A redundant clock system and communications cards for utilizing the system, the system including a clock source for providing a reference signal for communication cards; an alternate clock source, coupled to the clock source, for providing an alternate reference signal for the communication cards; each of the communication cards including a clock generator, referenced to one of the reference signals for providing clock signals at frequencies corresponding to functions provided by each of the communications cards, and each of the communication cards arranged to couple to a surviving one of the reference signals when a failure of the other is detected.

Abstract: A clock source selector for selecting either a first clock signal A or a second clock signal B in accordance with a switch request signal includes three retiming circuits each consisting of two clocked flip-flops. The switch request signal is first retimed relative to clock A to give a signal P, is then retimed relative to clock B to give a signal Q, and finally is retimed relative to clock A to give a signal R. Selector circuitry operates such that when signal Q is asserted, the second clock signal B is output, when neither signal P nor signal R, as combined by a NOR gate, are asserted, the first clock signal A is output, and at other times a zero level is output. The clock source selector can be used in an integrated circuit to form a glitch-free multiplexer.

Abstract: A clock signal generator, which requires no clock selection pin includes a multiplexer to which external and internal clocks are applied. The external clock is further coupled directly and via an inverting delay to a logic circuit, the output of which controls a switching device connected across a capacitor. The capacitor is coupled to a current source and to a comparator that is coupled to a reference voltage. The comparator output serves as the select control for the multiplexer. The switching device repeatedly discharges the capacitor in response to the external clock signal, but otherwise allows the capacitor to be charged by the current source. The external clock signal is coupled to the output of the multiplexer, as long as the capacitor is repeatedly discharged by the external clock signal at a frequency sufficient to maintain the voltage across the capacitor less than the reference voltage.

Abstract: An apparatus for a current mode logic variable delay element. A preferred embodiment comprises an input signal that is provided to a multiplexer (for example, multiplexer 210) in both buffered (via a buffer (for example, buffer 205)) and unbuffered form. A control signal of the multiplexer may be used to select from either the buffered or unbuffered input signals. By using a control signal at an intermediate value (somewhere in between values that selects the buffered or unbuffered input signals), the multiplexer may then combine the buffered and unbuffered input signals in proportion with the value of the control signal and imparts a delay upon the input signal that may be in between the delay imparted by the buffer.

Abstract: In a first aspect, a method is provided for selecting a signal from a plurality of signals. The method includes the steps of (1) providing a plurality of multiplexers, each multiplexer configured to selectively output one of a plurality of signals input by the multiplexer using an output of the multiplexer; (2) selecting an input signal from one of the plurality of multiplexers to output; (3) outputting the selected input signal from the output of the one of the plurality of multiplexers; (4) forcing the outputs of the other of the plurality of multiplexers to a predetermined logic state; and (5) combining the outputs of the plurality of multiplexers so as to output the selected input signal. Numerous other aspects are provided.

Abstract: A glitch free self-correcting clock switching mechanism operative to switch between two clocks in a glitch free manner while compensating for the ambiguity inherent in the switching operation. During the switching from fast to slow clock domains the mechanism measures the uncertainty or ambiguity of the first slow clock cycle duration during the switching operation and stores this value. At some time later, during the slow to fast clock switching the clock switch mechanism compensates for the metastability of the first slow clock cycle during fast to slow switching using the ambiguity value previously measured. In this manner the fast and slow clocks are switched between each other in a glitch-free and self compensating manner.

Abstract: A technique for glitchless switching among different frequency input clocks in a circuit includes monitoring each of the clocks and determining when the relative phases of the respective clocks are within a predetermined maximum of phase difference. Once the relative phases of the respective clocks are within an acceptable range, the system switches from one clock to another.

Abstract: The present invention is to provide a multiple phases switching circuit which is operable with a multiple phase signal generator and a succeeding circuit. The multiple-phase signal generator generates N multiple-phase clock signals. Phases of the multiple-phase clock signals are different. The multiple phases switching circuit comprises an alternative signal generator and a multiplexer. The alternative signal generator outputs an alternative signal according to an up/down switching signal. The multiplexer is coupled to the alternative signal generator for receiving the multiple-phase clock signals and proceeding a glitch/spike preventing process according to the alternative signal so as to output a target clock signal to the succeeding circuit.

Abstract: A clock switching circuit is provided for switching from a first clock signal being output to a freely selected second clock signal among a plurality of clock signals having different frequencies and phases while preventing generation of a hazard. The switching circuit has a plurality of unit circuits for respectively receiving as an input the clock signals, selection signals of the clock signals and enabling signals and controls supplying and stopping of the clock signals in accordance with the selection signals and the enabling signals. A feedback circuit monitors output conditions of the plurality of unit circuits and, when outputting of all clock signals of the plurality of unit circuits was stopped as a result of stopping the first clock signal, giving a plurality of the unit circuits the enabling signal for approving starting of a supply of the second clock signal.

Abstract: A clock generator and method generates a plurality of clocks of different frequencies using a delay lock loop and a sequencer. The delay lock loop receives an input clock signal having an input clock frequency and generates a plurality of delayed clock signals each having a frequency same as the input clock frequency and a different phase delay in relation to the input clock signal. The sequencer receives the delayed clock signals and selects one the delayed clock signals at any moment according to a predetermined sequence to generate an output clock signal having an output clock frequency corresponding to the predetermined sequence. The frequency of the output clock signal is controlled by the sequence in which the delayed clock signals are by the sequencer.

Abstract: Circuit interconnect communication circuitry dual edge triggered latching circuits transmit two data signals over a common interconnect line during one clock cycle; on signal is transmitted during each phase of a system clock over the common interconnect line. The latching circuits may be flip-flop circuits. A repeater circuit may have dual edge triggered flip-flop circuits for repeating the common interconnect line signal on a second common interconnect line. A receiver, including dual edge triggered latching circuitry, decodes the combined incoming data signals into separate outgoing data signals.

Abstract: The DC to DC converter has an oscillator and generates an output voltage to drive a system. The modulation frequency is used for modulating a pulse width modulation (PWM) circuit in the DC to DC converter. The method includes steps of: 1. providing the modulation frequency from the oscillator; 2. switching the source of the modulation frequency from the oscillator to the system clock to provide the modulation frequency when the system is driven by the output voltage from the DC to DC converter; and 3. stopping the oscillator for reducing a power loss.

Abstract: A symmetric glitch free clock multiplexing circuit allows the input clock to a digital or analog processing unit to be switched from one frequency to the other at any moment during the operation, assuming the respective clocks themselves are stable. There exist no restrictions on the clocks or the switch control signal to be synchronous in any fashion. This circuit guarantees a glitch free output and also prevents short cycling of the output clock. Since all the related clocks and switch control signal are asynchronous, this circuit further eliminates meta-stability problems. Its symmetrical architecture allows the circuit to function with the output clock being switched from slow clock to fast clock and vise versa.