Abstract: In a signal point arranging method for use with a quadrature amplitude modulator/demodulator device in which a desired number of signal points are arranged on a rectangular plane, a plurality of grid points are first set such that they are symmetrical with respect to the rectangular coordinate axes of the rectangular plane and arranged at intervals of a unit distance. Next, a plurality of concentric circles with their center at the coordinate origin of the rectangular plane are set, each of the concentric circles having a radius equal to a distance between the coordinate origin and a grid point. Then, a desired number of signal points are arranged on points of intersection of the grid points, the concentric circles beginning with the circle smallest in radius and continuing with circles of increasing radius. As a result, each of the signal points can be arranged as close to the coordinate origin as possible, thus enabling the peak power of modulated signals to be minimized.

Abstract: Convolutionally encoded information subjected to channel intersymbol interference is decoded by calculating the minimum cost path through a trellis. The trellis terminates in known states. Exploiting the open architecture of the coprocessor, the minimum cost state is checked to ascertain if it is the known, that is, correct state and if it is not, the possible known states are searched by the DSP inside the ECCP active register and the state with the lowest cost amont the possible states is selected.

Abstract: This delay detection circuit receives a digital-phase-modulated signal including an already-known preset symbol string and an unknown data symbol string following the already-known string, and detects a phase difference between an instantaneous phase of a reception signal and an instantaneous phase after a preset symbol time from the time of the reception signal received using a phase difference detector. Then, the delay detection circuit calculates a compensation phase difference necessary to demodulate the reception signal from the phase difference, the phase difference of demodulation symbol estimated from the already-known symbol string and the phase difference of demodulation symbol estimated from the data symbol string, and demodulate the reception signal based on the compensation phase difference.

Abstract: A digital quadrature demodulator for an intermediate frequency (IF) input signal with an analog-to-digital (A/D) converter having a sampling frequency f.sub.s and an input to which the IF input signal is applied where the IF input signal has a bandwith B<f.sub.s /4 centered about a frequency of f.sub.s /4. The demodulator includes an arrangement to direct even numbered output signals from the A/D converter to an inphase channel and odd numbered output signals from the A/D converter to a quadrature channel where each channel contains a highpass filter and the demodulator includes circuits to decimate by 4 signals of the channels to generate, together with the filters, a quadrature output signal Q(nT) at an output of the quadrature channel and an inphase output signal I(nT) at an output of the inphase channel. The quadrature highpass filter in the quadrature channel has an optimized transform architecture in which the filter coefficients h.sub.

Abstract: A method for demodulating the carrier signal of powerline communication networks. The method involves demodulating an HDLC data body that had been modulated through differential phase shift keyed modulation. Under the method, the data body is split with data input into a single bit digital delay circuit which outputs a delayed or "previous" binary data bit. A "present" binary data bit is input to one input of an XNOR circuit and the previous binary data bit is input into a second input of the XNOR circuit. When the present binary data bit and the previous binary data bit have unlike phases the XNOR circuit outputs a first binary data bit value. When the present binary data bit and the previous binary data bit have like phases, the XNOR circuit outputs a second binary data bit value. Preferably, the demodulated data is input into a post detection filter.

Abstract: A method and apparatus for use in estimating phase error in a phase-modulated carrier. The method and apparatus of the present invention may be embodied in a phase-error-estimator circuit which is typically incorporated into a demodulator of a digital communications receiver. In general, the phase-error-estimator circuit receives the I and Q components of a phase-modulated signal, and outputs an estimate of the phase error, if any, in the phase-modulated carrier signal associated with the received I and Q. Preferably, the phase-error-estimator circuit includes an index/polarity generator circuit coupled to a look-up table. The index/polarity generator receives I and Q and maps them onto a reduced range of phase angles represented by values X and Y. X and Y are fed to a reduced and substantially triangular look-up table which outputs the stored phase-error-estimate for the particular X and Y inputs.

Abstract: A method of demodulating an oversampled digitised analogue signal F(t) wherein n samples per bit of the digitised signal represent the instantaneous frequency and/or phase of the signal. The method includes the steps of selecting a sequence of bits containing bit value transitions, determining the magnitude of F(t) within the sequence so that all the extrema are maxima (or minima), whereby the maxima (or minima) of .vertline.F(t).vertline. provide a defined timing position in relation to the bits of the sequence. The value of .vertline.F(t).vertline. over a succession of said bits is averaged and a timing control signal is derived therefrom for demodulation of the digitised analogue signal.

Abstract: In a circuit arrangement for correcting phase errors of P-channel and Q-channel baseband signals of a QPSK signal, input registers are provided corresponding respectively to possible bit patterns which the unique words of the P-channel and Q-channel baseband signals may assume. Each input register stores 2N bits of incoming unique words of the P- and Q-channel signals. Reference registers corresponding to the possible bit patterns are provided for individually storing 2N bits of a corresponding one of the possible bit patterns. Mismatches between the bits stored in each input register and the corresponding reference register are detected and compared with thresholds to produce a phase error correcting signal. In response, the connecting paths of the P- and Q-channel baseband signals to output terminals are controlled and bit reversals are effected on the P- and Q-channel baseband signals.

Abstract: The invention relates to a method of reducing the peak power of a signal at the output of the transmit filter of a digital link, e.g. a microwave link. The invention is characterized by the use of a coding in transmission and a decoding in reception, adapted to reduce the peak power of the filtered signal. In the disclosed embodiment, not intended to be limiting, the encoder and the decoder can be realized through simple maps insertable in the baseband part of the system.

Abstract: A Manchester decoder and clock recovery circuit for recovering Manchester encoded data and a clock synchronized with the incoming data. The circuit uses an oversampling rate of eight times the data rate, and a reduction in circuit elements to reduce the circuit power consumption requirements. The circuit operates in a search mode and in a tracking mode. A clock phase generator produces eight phase clocks, used by a sampling and majority vote circuit to determine the decoded data value. During the tracking mode, the phase of the synchronized clock can be adjusted during data reception.

Abstract: A received carrier containing pseudonoise-modulation and with additive noise is correlated with a local pseudonoise signal having the same binary sequence but an unknown time delay. A second correlation is performed using a signal derived from the local pseudonoise signal (in a preferred embodiment, its time derivative). The bandpass filtered outputs of the two correlators are used as inputs to a third correlator, whose low-pass filtered output controls the time delay of the local pseudonoise signal to form a delay lock loop in which the delay may be measured and low-frequency modulation extracted from the signal. This delay lock loop has improved noise rejection as compared to prior art loops, and does not experience the "cycle slip" effects observed in coherent delay lock loops of conventional design.

Abstract: Binary signals that are transmitted by Manchester coding and frequency modulation are demodulated based on the behavior of the phase or complex vector value of the received signal. The polarities of the information bits may be determined by measuring the phase excursions in the middles of the Manchester symbols. A phase reference is established from a plurality of candidate phase references as a basis for comparison of the mid-symbol phase. The phase can be measured at the start-points and end-points of the symbols and averaged, or measured a plurality of times during each symbol period to generate a reference phase.

Abstract: In a complex modulation/demodulation method and system, the data frequency f.sub.C1 of data signals I and Q inputted to a constellation mapping circuit is converted by a digital interpolation circuit into a sampling frequency f.sub.C2 equal to f.sub.S /N, where f.sub.S is an operation sampling frequency and N is selected such that the signal maximum frequency of the data signals I and Q becomes lower than f.sub.C2 /2. The interpolated data signals I and Q are respectively inputted to real and imaginary input terminals of a complex coefficient band pass filter to extract a real signal output. An output signal of the complex coefficient band pass filter is converted by a DA converter into an analog signal from which desired frequency components are extracted by an analog band pass filter, thereby performing a quadrature modulation.

Abstract: A digital radio communications system employs a digital information source for providing digital information such as message bits, a transmitter for transmitting encoded digital information into data symbols in a radio-frequency (RF) signal to a plurality of antennae which sense the transmitted RF signal. A post detection measure of signal quality, the signal-to-impairment ratio, (SIR), is utilized by the receiver to perform post detection combining of signals received by a plurality of antennae. The antennae are coupled to a receiver which for each received signal: digitizes the signal, determines phase angles of the digitized signal, converts the signal to unit vectors, determines a signal-to-impairment ratio (SIR) estimates .gamma..sup.j of the digitized signals. The SIR estimate .gamma..sup.j is weighted by combining weight computation element and multiplied by each unit vector to provide an in-phase is component and a quadrature component for each signal.

Abstract: A radio receiver directly digitizes the phase of an intermediate frequency (IF) signal with a desired resolution. The frequency of the reference oscillator in the direct phase digitizer is reduced when compared to the frequency previously required for the same resolution. The reduction in the reference oscillator frequency is accomplished by differentiating between IF zero-crossings that occur during the first half of a reference oscillator cycle and zero-crossings which occur during the second half of the reference oscillator cycle. The apparatus utilizes 2 zero-crossing detectors, the first zero-crossing detector is driven by a positive edge of the reference oscillator signal and the second zero-crossing detector is driven by a negative edge of the reference oscillator signal. Depending upon the alignment of the negative edge zero-crossing indicator and the positive edge zero-crossing indicator, the N-bit phase signal is modified or shifted by one-half a phase sector.

Abstract: For a demodulator for radio data signals, where transmission of these signals is carried out through phase shifting of a suppressed subcarrier, where a multiplex signal, which contains a signal with the frequency of the subcarrier passes through a band-pass filter and an amplitude limiter, the amplitude-limited signal having a subcarrier frequency is transformed into digital sampling values, if necessary by additional filtering, and the sampling values are supplied to at least one phase control loop for deriving a bit clock signal.

Abstract: A clock recovery circuit having a feedback system in a .pi./4 shift QPSK demodulator, comprising a signal state transition detector for detecting state transitions between consecutive symbols of the demodulated baseband signal which is formed from the detected baseband signal by .pi./4 reverse shifting. According to degree of the detected symbol state transition, the 1/2-symbol delayed baseband signal is shifted by the amount of .pi./8 in phase. According to direction of the detected symbol state transition, the .pi./8 phase shifted baseband signal is converted into an error signal in use for the feedback system. An oscillator generates a clock signal of a frequency controlled by the error signal such that the error signal is reduced in the feedback system.

Abstract: A one-bit differential detector for a GMSK signal operates independently of an offset frequency. In particular, a decision signal used by a decision circuit to distinguish between logic "0" and logic "1" is always equal to sin[.DELTA..phi.(T)]. The inventive detector has an improved bit error rate performance in comparison to the prior art.

Abstract: A method and apparatus for concurrent communication of analog information and digital information. In general terms, when the communication channel is viewed as a multi-dimensional space, the digital information signal is divided into symbols, and the symbols are mapped onto the signal space with a preset distance between them. The analog signal, generally limited in magnitude to less than the distance separating the symbols, is converted to component signals and added (i.e., vector addition) to the symbols. The sum signal is then transmitted to the receiver where the symbols are detected and subtracted from the received signal to yield the analog signal components. The transmitted analog signal is recreated from those components. Both half-duplex and full-duplex operation is available in accordance with the disclosure.

Abstract: A system is described which achieves an increased rate of transmission by transmitting multiple symbols in one symbol time. The information in the overlapping symbols can be recovered if the symbol used for transmission is chosen so that a subset of the samples representing the symbol has an inverse. The construction of suitable symbols is illustrated. Effective operation of the system depends on equalizaton which will recover the the baseband signal shape. Methods of equalization are depicted which are suitable for use with this sytem including equalization realized by predistorting the signal at the transmitter so that it arrives at the receiver undistorted. The invention is applied to to baseband and passband systems and the application of predistortion equalization to the fading passband channel is described.

Abstract: A cost-effective, bandwidth-efficient, and power-efficient system is provided in which data streams received from several different video sources are converted into sequences of symbols selected from a predetermined constellation and are multiplexed on a symbol-by-symbol basis into a single sequence of symbols for transmission on a channel. Using a symbol multiplexer helps to mitigate the effect of bursty noise in the receiver and reduces the processing speed requirement in the receiver.

Abstract: A QPSK modulated wave is inputted to an in-phase detector and an orthogonal detector. The detected components are converted to substantially a base band, and each component is digital-converted by A/D converters. Each digital component is spectrum-shaped by digital LPFs. The outputs of digital LPFs are inputted to a complex multiplier and calculated by use of first and second reproduction carriers and expressed as first and second calculation outputs, and inputted to a phase detector. The phase detector obtains phase difference data between the phase expressed by the first and second calculation outputs and a predetermined phase and quadrant data of the phase. The phase difference data is used for a PLL. The phase difference data is is inputted to a frequency error detection circuit detecting a frequency error. The frequency error output is smoothed by a filter of an AFC loop, and used as a control signal controlling the oscillation frequency of the local oscillation unit.

Abstract: Symbols (18) of a burst (12) are sub-divided into symbol sections (20). Each symbol section (20) is sampled and converted into polar coordinates. A buffer bank (38) selectably delays the samples and replays a preamble (14). A demod bank (40) includes a coherent demod (58) and several differential demods (60). Each differential demod (60) processes its own stream of symbol sections (20). The differential demods (60) feed a preamble detector (66) and a symbol synchronization circuit (62). The symbol synchronization circuit (62) identifies the symbol section (20) which yields the smallest magnitude of frequency errors. This symbol section (20) is processed by the coherent demod (58) to acquire carrier phase and recover data. The coherent demod (58) is implemented in the phase domain so that only oscillation signal phase data need be generated in phase locked loops.

Abstract: A device for demodulating a signal modulated on two axes in phase quadrature using a .pi./4-QPSK type digital modulation technique employing alternately two phase-shifted constellations. The device includes: a voltage-controlled oscillator (28) supplying a local signal substantially at the carrier frequency; a demodulator means using the local signal and supplying, after filtering (30, 31), the phase component P and quadrature component Q of the demodulated received signal; a phase controller (32) producing a control signal (39) for controlling the oscillator (28) and including a phase estimator (33) producing a phase estimation signal E (35) involved in control of the oscillator (28), the phase estimation signal being derived from the phase component P and quadrature component Q of the demodulated received signal.

Abstract: In a demodulator for radio data signals the transmission of which is made by phase-keying of a suppressed subcarrier the occurence of transient times is avoided in that the received signal of subcarrier frequency is transformed into a first square wave signal (A) and that a second square wave signal of subcarrier of frequency is formed which is brought into such a time relationship to the first square wave signal that by means of a comparison of both square wave signals a phase information for the first square wave signal (A) is obtained. Demodulator can be implemented by means of only digital components.

Abstract: A modulator receives a main signal synchronizing with a clock and a secondary signal having start and stop bits for each character. The modulator contains a unit for removing the start and stop bits from the secondary signal to generate a clock-synchronizing secondary signal. Then, the clock-synchronizing secondary signal and the main signal are modulated in parallel synchronized with a clock, and modulated signals are frequency division multiplexed. A demodulator receives a frequency division multiplexed modulated signal, and a clock-synchronizing main signal and a clock-synchronizing secondary signal are respectively regenerated by modulation and band separation. The demodulator contains a unit for inserting start and stop bits respectively before and after each character contained in the clock-synchronizing secondary signal to generate a secondary signal in a start-stop system.

Abstract: A method is presented for efficient VLSI implementation of a narrowband BPSK or QPSK demodulator which minimizes filter processing requirements. The demodulator implements a digital filter which spans a time duration of 8 symbols to realize a square root of raised cosine filter. The disadvantage of a conventional FIR filter, is that it requires a fixed ratio between the input sample rate and the FIR filter output rate. The subject invention employs a unique, flexible digital filter which provides one output per symbol while the input sample rate may vary from a low rate approaching two samples per symbol to over 128 samples per symbol. A key element of this approach is the digital phase locked loop used for symbol tracking which employs a direct digital synthesizer (DDS) as the frequency control element. In addition to providing symbol timing to the accuracy of the sample clock, the DDS also provides a fine measure of symbol timing phase at each sample clock.

Abstract: A radio modulator/demodulator particularly suitable for TDMA mobile telephone use employs digital techniques for GMSK phase modulation. Phase numbers representative respectively of an intermediate frequency carrier and modulation symbols are combined digitally to combination phase numbers which are subjected to a single folded cosine table to produce a digital trignometric sequence of numbers for modulating the transmitter. Economy of components and memory is achieved and some of the modulator components are used in demodulation which is effected by the single look-up table used in sine and cosine mode alternately.

Abstract: A four quadrant multiplier circuit having a high dynamic range and capable of operating at low voltages includes a dual transconductance amplifier circuit (TAC) consisting of NPN transistors (20 to 23 and 64 to 67), coupled to a first input port (36), first and second folded Darlington circuits (57,58), and a resistive element (78). Each Darlington circuit includes first and second NPN transistors (68,70 and 69,71) whose emitter-collector paths are connected in series and a third PNP transistor (72,73) having its emitter-collector path connected between the collector of the first transistor (68,69) and the base electrode of the second transistor (70,71). The emitter-collector junction (76,77) of the first and second transistors (68,70 and 69,71) is connected to the base electrode of the third transistor (72,73). The resistive element (78) is connected between the base electrodes of the third transistors (72,73). A second input port (56) is connected to the base electrodes of the first transistors (68,69).

Abstract: In a demodulator for use in the Radio Data System (RDS) as defined by the European Broadcasting Union, transmission of these signals is carried out through phase shift modulation of a suppressed subcarrier, a multiplex signal, which contains a signal with the frequency of the subcarrier passes through a band-pass filter and an amplitude limiter, and the amplitude-limited signal, having a carrier frequency, is sampled at a sampling frequency that is a multiple of the frequency of the subcarrier. The sampling values are summed over a preset portion of one period of the subcarrier. The summed sampling values are supplied to a digital signal processing circuit.

Abstract: A method and apparatus for normalizing the I and Q components of a complex signal is provided which includes an iterative determination of the multiplier constant required for normalization. The I and Q components are squared and added together to create a digital word A constrained between certain limits. An iterative approach is implemented to arrive at a multiplier constant K which is equal to ##EQU1## without resorting to the use of multipliers. The constant K is then used to normalize the I and Q components.

Abstract: Multilevel coded modulation equipment includes a transmission unit and a reception unit. The transmission unit includes a first converting unit, a first encoding unit, a first differential encoding unit, a second encoding unit, a mapping unit, and a modulating unit. The reception unit includes a demodulating unit, a first decoding unit, an inverting unit, a phase shifting unit, a second decoding unit, a differential decoding unit, a decision unit, and a second converting unit. The first converting unit distributes an input serial digital signal to a plurality of levels containing a level 1 indicating a level which is transparent to a 90.degree. phase ambiguity, and a level 2 indicating a level which is transparent to a 180.degree. phase rotation. The second converting unit receives outputs from the inverting unit, the differential decoding unit, and the decision unit, multiplexes the received signals into a serial digital signal, and outputs the serial digital signal.

Abstract: In a modulation system, a demodulator demodulates an intermediate frequency modulated signal and outputs an analog-baseband signal, and an analog-digital converter analog-digital converts this baseband signal. An adaptive matched filter inputs the output of the analog-digital converter and makes symmetrical the impulse response of the propagation path. A decision feedback equalizer inputs the output of the adaptive matched filter and eliminates the intersymbol interference. A reset circuit judges the fading type using tap coefficients within the decision feedback equalizer, and stops the operation of the adaptive matched filter in cases of minimum phase shift type fading. The adaptive matched filter is constructed so as to operate in an intermediate frequency band as well as in a baseband.

Abstract: A communication system (10) includes a modulation section (12) and a demodulation section (14). The modulation section (12) performs frequency modulation in accordance with a frequency trajectory signal (28, 30, 32). An intersymbol interference (ISI) prediction filter (20) adjusts the amplitude of the frequency trajectory signal (28, 30, 32) in response to data code (16) sequences being conveyed over a plurality of symbols (18). More frequent data changes in the sequence of the data codes (16) lead to greater amplitudes in the frequency trajectory signal. The demodulation section (14) applies a distorted phase signal to a decision circuit (38). The distorted phase signal conveys a received phase (46) that includes ISI. Due to the equalization applied by the ISI prediction filter (20), the received phase (46) approximates a target phase (40, 42) in spite of the ISI.

Abstract: A technique for determining the constellation size of a QAM signal received by a QAM receiver. In general, the implementation of my technique has, as an input signal, a QAM signal having one of a plurality of constellation sizes and determines of constellation size, e.g., 4, 16, 32-ary, by analyzing the probability density function (pdf) of the QAM signal over a pre-established time period. To properly analyze the QAM signal, the signal is-first squared and then normalized to a preset value, e.g., 2.0. As such, the signal power in any of the various constellations is normalized to a fixed level. By generating a histogram of the squared and normalized QAM signal, the technique determines the number of levels of modulation contained in the QAM signal. Each constellation size has a unique number of modulation levels and thus forms unique histogram. From the histogram, a particular constellation size can be determined.

Abstract: A DQPSK delay detection circuit includes a semi-synchronous detector synchronously detecting an input signal to obtain two demodulated signals, a low-pass filter for extracting a baseband signal from the demodulated signals, an A-D convertor sampling the baseband signal by a clock signal with a frequency 32 times higher than a symbol rate frequency and converting them to digital values with a predetermined number of quantization bits, a clock pulse generator generating clock signals synchronized with the baseband signal and having a frequency equal to and two times as high as the symbol rate frequency with a phase adjusted in accordance with a change of an eye pattern of an output of the A-D convertor, a data delay unit delaying the output of the A-D convertor by a time equivalent to one time slot according to a clock signal synchronized with the baseband signal and having a frequency equal to the symbol rate frequency, an operation unit generating signals I and Q from the output of the A-D convertor and a on

Abstract: A low complexity adaptive equalizer for use in U.S. digital cellular radios demodulates .pi./4-shifted differentially encoded quadrature phase shift keyed (DQPSK) encoding in the presence of intersymbol interference (ISI) with reduced decoding complexity by employing an estimated received constellation which takes into account channel changes over time and ISI. The decoding complexity is reduced by tracking a reduced number of estimated reference symbol constellation points and taking advantage of the geometry to estimate the remaining symbol constellation points. Reference symbol constellation points are updated directly to compensate for changes in the channel, instead of determining channel impulse response (CIR) coefficients, and convolving the CIR coefficients with received symbols to determine new reference symbol constellation points.

Abstract: A data burst is modulated on an IF carrier, and a spectral null is artificially created in the center frequency region of the spectrum of the modulated data burst by taking the difference between delayed and non-delayed versions of the IF data burst. A sync burst is modulated on the IF carrier so that its spectrum corresponds to the center frequency region of the data burst and superimposed on the IF data burst and transmitted. At a receive site, the IF sync burst is recovered by passing the superimposed IF signal through a bandpass filter having a passband corresponding to the spectrum of the IF sync burst and the IF carrier is recovered from the recovered sync burst. The sync burst at baseband frequency is recovered from the IF sync burst by a demodulator using the recovered carrier.

Abstract: A quadrature amplitude modulation (QAM) communication system is provided in which data can be communicated in any one of a plurality of QAM modes, such as 16-QAM, 32-QAM, and 64-QAM. A receiver detects the particular QAM mode transmitted on a trial and error basis, by attempting to decode the received data using different QAM modes until a synchronization condition is detected. The synchronization condition can require that a plurality of different synchronization tests be met. In a specific embodiment, a first synchronization test is met when a renormalization rate of a trellis decoder is below a threshold value. A second synchronization test is met when a first synchronization word is detected in the received data. A third and final synchronization test is met when a second synchronization word is detected in the received data. In order to reduce the cost of the receiver, most of the QAM mode dependent components are implemented using look-up tables stored in PROMs.

Abstract: Supplied with an input signal into which a carrier signal is modulated at a frame period by a data signal and unique words periodically interspersed throughout the data signal, a demodulating circuit (14) demodulates the input signal into a demodulated signal. A frame synchronizing circuit (23) produces an aperture signal which defines an aperture interval determined by the frame period when the demodulated signal has a level which is lower than a predetermined threshold level. Responsive to the aperture signal, a cross-correlating circuit (24) calculates a cross-correlation coefficient between the demodulated signal and a locally known unique word. By the use of the cross-correlation coefficient, a phase error calculating circuit (25) calculates a phase error between a reproduced carrier signal reproduced from the demodulated signal and a regenerated carrier signal which is a correct regeneration of the carrier signal.

Abstract: A modulation circuit includes a mapping position detector as well as a circuit for differentially phase coding a plurality of separated data streams. The differentially phase coding circuit is adapted to differentially phase code the plurality of data streams for each pulse time and generate a coded signal containing amplitude information. The mapping position detector detects the phase mapping position of the coded signal based on the amplitude information in the coded signal which is output from the differentially phase coding circuit. Information representing the detected phase mapping position is supplied to the differentially phase coding circuit so as to achieve a differential phase coding at a pulse time following one pulse time.

Abstract: Apparatus for demodulating an incoming digitally phase modulated analog signal to reproduce symbol data carried by the signal. Specifically, the demodulator relies on first counting, on a free-running and modulo basis, pulses of a fixed-frequency reference clock signal to form a counted value. The incoming signal is converted to a one-bit phase modulated digital signal. At the occurrence of a pre-defined point in the one-bit phase modulated signal, typically a rising edge occurring at the symbol rate, the counted value is stored as phase information. Within each symbol period, a difference between current and immediately prior counted values, i.e. the latter being a current value but delayed by one symbol period, is determined. This difference, i.e. phase change data, is subsequently sampled and decoded to yield reproduced symbol data, as well as, used, through a phase locked loop, to generate a data clock and the symbol clock.

Abstract: In a QAM demodulator, gain-controlled amplifiers are provided respectively for the in-phase and quadrature channel baseband components of the signal, and a set of data and error signals is recovered from the output of each gain-controlled amplifier. To determine the location of the signal point of each channel component, the QAM signal constellation is divided along the axis of the channel into two outermost regions A, an innermost region B and two intermediate regions C, and further divided along the axis of the channel into two outer regions E and an inner region D therebetween. In response to each set of data and error signals, the location of the signal point of each baseband component is determined with respect to the regions A, B and C to produce a first logical output signal and with respect to the regions D and E to produce a second logical output signal.

Abstract: A data receiver which enhances a probability of frame synchronization even if a transmission line quality is bad detects a specific bit sequence in a received signal demodulated by a demodulator to deduce a transmission line quality by a line quality deducer. If the transmission line quality is so bad that a frame synchronization detector cannot detect the specific bit sequence, the specific bit sequence is detected from a received signal demodulated by an equalizer after the elimination of a transmission line distortion.

Abstract: The invention is a method and a circuit for detecting the carrier-to-noise ("CN") ratio of a quaterary phase-shift keying ("QPSK") signal. A binary signal including in the QPSK signal is reproduced by a converting circuit including a QPSK demodulator and a difference converter. The binary signal is then error-controlled by an error detecting circuit and the detection of a double-error. The occurrence number of the double-error is counted during a predetermined time period which is long enough to compare with the occurrence time when two successive double-errors occur. A microcomputer stores a conversion table corresponding to the theoretical relation between the CN ratio and the occurrence number. The microcomputer computes the CN ratio from the detected occurrence number. The theoretical relation is formulated based on the assumption that noise distributes isotopically around the QPSK signal in the signal space in accordance with the nomal distribution.

Abstract: An arrangement for detecting quadrature phase errors introduced by a synchronous demodulator between the two quadrature channels, in-phase (I) and quadrature-phase (Q), of a synchronous demodulator, and for correcting for such detected quadrature phase errors without the need for high data sampling rates. During an initial test period, a periodic symmetrical test signal of known frequency is introduced into the synchronous demodulator. During the test period, the output of the synchronous demodulator is integrated over an integer multiple of periods to detect the quadrature phase error introduced by the synchronous demodulator, and an error signal is generated representative of the detected quadrature phase error. During a following period of operation of the synchronous demodulator, the in-phase (I) and quadrature-phase (Q) signals produced by the synchronous demodulator are applied to a quadrature phase error correction network, along with the generated quadrature phase error signal.

Abstract: In a phase divider, a complex signal containing a sequence of samples of real and imaginary values is limited to a unit amplitude and multiplied by a first complex multiplier with a first feedback complex signal, the output the multiplier being fed through a loop filter to a second complex multiplier where the signal is multiplied with a second feedback complex signal. The output of the second multiplier is limited to a unit amplitude, delayed by a sample interval and applied to the second complex multiplier as the second feedback complex signal. The first feedback complex signal is derived by a circuit that raises the frequency the delayed signal by a desired factor.

Abstract: An optimum communication system for communicating on adjacent frequency bands with minimal interference between adjacent channels comprises an encoder that is serially coupled to a mapper and two parallel processing branches, each processing branch having a transmit filter a digital-to-analog converter, a low pass filter and a modulator coupled in series. Both modulators are coupled to a summer, and an rf amplifier having a transmit antenna. The encoder is optimized by choosing a desired minimum Euclidean distance (DMED) between symbols, an encoder alphabet and a number of constellation points, permutating all possible encoder states and all possible input symbols to result in a plurality of encoder sets U, determining an in-band to adjacent band power ratio P.sub.ib /P.sub.

Abstract: An optimum communication system employs an encoder coupled to a mapper and two parallel branches, each branch having a transmit filter a digital-to-analog converter, a low pass filter and a modulator coupled in series. Both modulators are coupled to a summer which provides an rf signal to a transmit antenna. A second antenna is coupled to a first down converter, an IF filter, a second down converter, an analog-to-digital converter and a decoder. The encoder is optimized by choosing a desired minimum Euclidean distance between symbols multiplied by the average to peak transmit power ratio (MPDR), an encoder alphabet and a number of constellation points. All possible encoder states and all possible input symbols are permutated to result in a plurality of encoder sets. The minimum distance between coded symbols and a P.sub.ib /P.sub.ab power ratio for each code set is determined. The encoder is adapted to output an encoder set U having a largest P.sub.ib /P.sub.

Abstract: A receiver designed for use in a mobile environment, which includes an adaptive equalizer driven by phase estimation and rotation circuitry, and which is operable in multipath fading channels. The present invention uses an AFC loop and a phase rotation circuit in front of the adaptive equalizer to improve equalizer performance in the fading channel. The present invention uses .pi./4 phase rotation circuitry before a phase quantization decision is made. This .pi./4 phase rotation circuitry allows for decisions to be made on a QPSK constellation, rather than on an input 8PSK constellation, thus improving detection performance.